1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5 * Original from Linux kernel 3.0.1
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include <ipxe/vsprintf.h>
21 #include <ipxe/io.h>
22
23 #include "hw.h"
24 #include "hw-ops.h"
25 #include "ar9003_mac.h"
26
27 static int ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
28
29 /* Private hardware callbacks */
30
ath9k_hw_init_cal_settings(struct ath_hw * ah)31 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
32 {
33 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
34 }
35
ath9k_hw_init_mode_regs(struct ath_hw * ah)36 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
37 {
38 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
39 }
40
ath9k_hw_compute_pll_control(struct ath_hw * ah,struct ath9k_channel * chan)41 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
42 struct ath9k_channel *chan)
43 {
44 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
45 }
46
ath9k_hw_init_mode_gain_regs(struct ath_hw * ah)47 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
48 {
49 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
50 return;
51
52 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
53 }
54
ath9k_hw_ani_cache_ini_regs(struct ath_hw * ah)55 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
56 {
57 /* You will not have this callback if using the old ANI */
58 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
59 return;
60
61 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
62 }
63
64 /********************/
65 /* Helper Functions */
66 /********************/
67
ath9k_hw_set_clockrate(struct ath_hw * ah)68 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
69 {
70 struct ath_common *common = ath9k_hw_common(ah);
71 struct net80211_device *dev = common->dev;
72 unsigned int clockrate;
73
74 if (!ah->curchan) /* should really check for CCK instead */
75 clockrate = ATH9K_CLOCK_RATE_CCK;
76 else if ((dev->channels + dev->channel)->band == NET80211_BAND_2GHZ)
77 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
78 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
79 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
80 else
81 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
82
83 common->clockrate = clockrate;
84 }
85
ath9k_hw_mac_to_clks(struct ath_hw * ah,u32 usecs)86 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
87 {
88 struct ath_common *common = ath9k_hw_common(ah);
89
90 return usecs * common->clockrate;
91 }
92
ath9k_hw_wait(struct ath_hw * ah,u32 reg,u32 mask,u32 val,u32 timeout)93 int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
94 {
95 unsigned int i;
96
97 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
98 if ((REG_READ(ah, reg) & mask) == val)
99 return 1;
100
101 udelay(AH_TIME_QUANTUM);
102 }
103
104 DBG("ath9k: "
105 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
106 timeout, reg, REG_READ(ah, reg), mask, val);
107
108 return 0;
109 }
110
ath9k_hw_write_array(struct ath_hw * ah,struct ar5416IniArray * array,int column,unsigned int * writecnt)111 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
112 int column, unsigned int *writecnt)
113 {
114 unsigned int r;
115
116 ENABLE_REGWRITE_BUFFER(ah);
117 for (r = 0; r < array->ia_rows; r++) {
118 REG_WRITE(ah, INI_RA(array, r, 0),
119 INI_RA(array, r, column));
120 DO_DELAY(*writecnt);
121 }
122 REGWRITE_BUFFER_FLUSH(ah);
123 }
124
ath9k_hw_reverse_bits(u32 val,u32 n)125 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
126 {
127 u32 retval;
128 unsigned int i;
129
130 for (i = 0, retval = 0; i < n; i++) {
131 retval = (retval << 1) | (val & 1);
132 val >>= 1;
133 }
134 return retval;
135 }
136
ath9k_hw_computetxtime(struct ath_hw * ah,u8 phy,int kbps,u32 frameLen,u16 rateix,int shortPreamble)137 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
138 u8 phy, int kbps,
139 u32 frameLen, u16 rateix,
140 int shortPreamble)
141 {
142 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
143
144 if (kbps == 0)
145 return 0;
146
147 switch (phy) {
148 case CHANNEL_CCK:
149 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
150 if (shortPreamble)
151 phyTime >>= 1;
152 numBits = frameLen << 3;
153 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
154 break;
155 case CHANNEL_OFDM:
156 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
157 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
158 numBits = OFDM_PLCP_BITS + (frameLen << 3);
159 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
160 txTime = OFDM_SIFS_TIME_QUARTER
161 + OFDM_PREAMBLE_TIME_QUARTER
162 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
163 } else if (ah->curchan &&
164 IS_CHAN_HALF_RATE(ah->curchan)) {
165 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
166 numBits = OFDM_PLCP_BITS + (frameLen << 3);
167 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
168 txTime = OFDM_SIFS_TIME_HALF +
169 OFDM_PREAMBLE_TIME_HALF
170 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
171 } else {
172 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
173 numBits = OFDM_PLCP_BITS + (frameLen << 3);
174 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
175 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
176 + (numSymbols * OFDM_SYMBOL_TIME);
177 }
178 break;
179 default:
180 DBG("ath9k: "
181 "Unknown phy %d (rate ix %d)\n", phy, rateix);
182 txTime = 0;
183 break;
184 }
185
186 return txTime;
187 }
188
ath9k_hw_get_channel_centers(struct ath_hw * ah __unused,struct ath9k_channel * chan,struct chan_centers * centers)189 void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused,
190 struct ath9k_channel *chan,
191 struct chan_centers *centers)
192 {
193 int8_t extoff;
194
195 if (!IS_CHAN_HT40(chan)) {
196 centers->ctl_center = centers->ext_center =
197 centers->synth_center = chan->channel;
198 return;
199 }
200
201 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
202 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
203 centers->synth_center =
204 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
205 extoff = 1;
206 } else {
207 centers->synth_center =
208 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
209 extoff = -1;
210 }
211
212 centers->ctl_center =
213 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
214 /* 25 MHz spacing is supported by hw but not on upper layers */
215 centers->ext_center =
216 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
217 }
218
219 /******************/
220 /* Chip Revisions */
221 /******************/
222
ath9k_hw_read_revisions(struct ath_hw * ah)223 static void ath9k_hw_read_revisions(struct ath_hw *ah)
224 {
225 u32 val;
226
227 switch (ah->hw_version.devid) {
228 case AR5416_AR9100_DEVID:
229 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
230 break;
231 case AR9300_DEVID_AR9340:
232 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
233 val = REG_READ(ah, AR_SREV);
234 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
235 return;
236 }
237
238 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
239
240 if (val == 0xFF) {
241 val = REG_READ(ah, AR_SREV);
242 ah->hw_version.macVersion =
243 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
244 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
245 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
246 } else {
247 if (!AR_SREV_9100(ah))
248 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
249
250 ah->hw_version.macRev = val & AR_SREV_REVISION;
251
252 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
253 ah->is_pciexpress = 1;
254 }
255 }
256
257 /************************************/
258 /* HW Attach, Detach, Init Routines */
259 /************************************/
260
ath9k_hw_disablepcie(struct ath_hw * ah)261 static void ath9k_hw_disablepcie(struct ath_hw *ah)
262 {
263 if (!AR_SREV_5416(ah))
264 return;
265
266 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
267 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
268 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
269 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
270 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
271 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
272 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
273 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
274 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
275
276 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
277 }
278
279 /* This should work for all families including legacy */
ath9k_hw_chip_test(struct ath_hw * ah)280 static int ath9k_hw_chip_test(struct ath_hw *ah)
281 {
282 u32 regAddr[2] = { AR_STA_ID0 };
283 u32 regHold[2];
284 static const u32 patternData[4] = {
285 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
286 };
287 int i, j, loop_max;
288
289 if (!AR_SREV_9300_20_OR_LATER(ah)) {
290 loop_max = 2;
291 regAddr[1] = AR_PHY_BASE + (8 << 2);
292 } else
293 loop_max = 1;
294
295 for (i = 0; i < loop_max; i++) {
296 u32 addr = regAddr[i];
297 u32 wrData, rdData;
298
299 regHold[i] = REG_READ(ah, addr);
300 for (j = 0; j < 0x100; j++) {
301 wrData = (j << 16) | j;
302 REG_WRITE(ah, addr, wrData);
303 rdData = REG_READ(ah, addr);
304 if (rdData != wrData) {
305 DBG("ath9k: "
306 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
307 addr, wrData, rdData);
308 return 0;
309 }
310 }
311 for (j = 0; j < 4; j++) {
312 wrData = patternData[j];
313 REG_WRITE(ah, addr, wrData);
314 rdData = REG_READ(ah, addr);
315 if (wrData != rdData) {
316 DBG("ath9k: "
317 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
318 addr, wrData, rdData);
319 return 0;
320 }
321 }
322 REG_WRITE(ah, regAddr[i], regHold[i]);
323 }
324 udelay(100);
325
326 return 1;
327 }
328
ath9k_hw_init_config(struct ath_hw * ah)329 static void ath9k_hw_init_config(struct ath_hw *ah)
330 {
331 int i;
332
333 ah->config.dma_beacon_response_time = 2;
334 ah->config.sw_beacon_response_time = 10;
335 ah->config.additional_swba_backoff = 0;
336 ah->config.ack_6mb = 0x0;
337 ah->config.cwm_ignore_extcca = 0;
338 ah->config.pcie_powersave_enable = 0;
339 ah->config.pcie_clock_req = 0;
340 ah->config.pcie_waen = 0;
341 ah->config.analog_shiftreg = 1;
342 ah->config.enable_ani = 1;
343
344 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
345 ah->config.spurchans[i][0] = AR_NO_SPUR;
346 ah->config.spurchans[i][1] = AR_NO_SPUR;
347 }
348
349 /* PAPRD needs some more work to be enabled */
350 ah->config.paprd_disable = 1;
351
352 ah->config.rx_intr_mitigation = 1;
353 ah->config.pcieSerDesWrite = 1;
354 }
355
ath9k_hw_init_defaults(struct ath_hw * ah)356 static void ath9k_hw_init_defaults(struct ath_hw *ah)
357 {
358 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
359
360 regulatory->country_code = CTRY_DEFAULT;
361 regulatory->power_limit = MAX_RATE_POWER;
362 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
363
364 ah->hw_version.magic = AR5416_MAGIC;
365 ah->hw_version.subvendorid = 0;
366
367 ah->atim_window = 0;
368 ah->sta_id1_defaults =
369 AR_STA_ID1_CRPT_MIC_ENABLE |
370 AR_STA_ID1_MCAST_KSRCH;
371 if (AR_SREV_9100(ah))
372 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
373 ah->enable_32kHz_clock = DONT_USE_32KHZ;
374 ah->slottime = 20;
375 ah->globaltxtimeout = (u32) -1;
376 ah->power_mode = ATH9K_PM_UNDEFINED;
377 }
378
ath9k_hw_init_macaddr(struct ath_hw * ah)379 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
380 {
381 struct ath_common *common = ath9k_hw_common(ah);
382 u32 sum;
383 int i;
384 u16 eeval;
385 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
386
387 sum = 0;
388 for (i = 0; i < 3; i++) {
389 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
390 sum += eeval;
391 common->macaddr[2 * i] = eeval >> 8;
392 common->macaddr[2 * i + 1] = eeval & 0xff;
393 }
394 if (sum == 0 || sum == 0xffff * 3)
395 return -EADDRNOTAVAIL;
396
397 return 0;
398 }
399
ath9k_hw_post_init(struct ath_hw * ah)400 static int ath9k_hw_post_init(struct ath_hw *ah)
401 {
402 struct ath_common *common = ath9k_hw_common(ah);
403 int ecode;
404
405 if (common->bus_ops->ath_bus_type != ATH_USB) {
406 if (!ath9k_hw_chip_test(ah))
407 return -ENODEV;
408 }
409
410 if (!AR_SREV_9300_20_OR_LATER(ah)) {
411 ecode = ar9002_hw_rf_claim(ah);
412 if (ecode != 0)
413 return ecode;
414 }
415
416 ecode = ath9k_hw_eeprom_init(ah);
417 if (ecode != 0)
418 return ecode;
419
420 DBG("ath9k: "
421 "Eeprom VER: %d, REV: %d\n",
422 ah->eep_ops->get_eeprom_ver(ah),
423 ah->eep_ops->get_eeprom_rev(ah));
424
425 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
426 if (ecode) {
427 DBG("ath9k: "
428 "Failed allocating banks for external radio\n");
429 ath9k_hw_rf_free_ext_banks(ah);
430 return ecode;
431 }
432
433 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
434 ath9k_hw_ani_setup(ah);
435 ath9k_hw_ani_init(ah);
436 }
437
438 return 0;
439 }
440
ath9k_hw_attach_ops(struct ath_hw * ah)441 static void ath9k_hw_attach_ops(struct ath_hw *ah)
442 {
443 if (AR_SREV_9300_20_OR_LATER(ah))
444 ar9003_hw_attach_ops(ah);
445 else
446 ar9002_hw_attach_ops(ah);
447 }
448
449 /* Called for all hardware families */
__ath9k_hw_init(struct ath_hw * ah)450 static int __ath9k_hw_init(struct ath_hw *ah)
451 {
452 struct ath_common *common = ath9k_hw_common(ah);
453 int r = 0;
454
455 ath9k_hw_read_revisions(ah);
456
457 /*
458 * Read back AR_WA into a permanent copy and set bits 14 and 17.
459 * We need to do this to avoid RMW of this register. We cannot
460 * read the reg when chip is asleep.
461 */
462 ah->WARegVal = REG_READ(ah, AR_WA);
463 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
464 AR_WA_ASPM_TIMER_BASED_DISABLE);
465
466 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
467 DBG("ath9k: Couldn't reset chip\n");
468 return -EIO;
469 }
470
471 ath9k_hw_init_defaults(ah);
472 ath9k_hw_init_config(ah);
473
474 ath9k_hw_attach_ops(ah);
475
476 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
477 DBG("ath9k: Couldn't wakeup chip\n");
478 return -EIO;
479 }
480
481 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
482 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
483 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
484 !ah->is_pciexpress)) {
485 ah->config.serialize_regmode =
486 SER_REG_MODE_ON;
487 } else {
488 ah->config.serialize_regmode =
489 SER_REG_MODE_OFF;
490 }
491 }
492
493 DBG2("ath9k: serialize_regmode is %d\n",
494 ah->config.serialize_regmode);
495
496 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
497 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
498 else
499 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
500
501 switch (ah->hw_version.macVersion) {
502 case AR_SREV_VERSION_5416_PCI:
503 case AR_SREV_VERSION_5416_PCIE:
504 case AR_SREV_VERSION_9160:
505 case AR_SREV_VERSION_9100:
506 case AR_SREV_VERSION_9280:
507 case AR_SREV_VERSION_9285:
508 case AR_SREV_VERSION_9287:
509 case AR_SREV_VERSION_9271:
510 case AR_SREV_VERSION_9300:
511 case AR_SREV_VERSION_9485:
512 case AR_SREV_VERSION_9340:
513 break;
514 default:
515 DBG("ath9k: "
516 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
517 ah->hw_version.macVersion, ah->hw_version.macRev);
518 return -EOPNOTSUPP;
519 }
520
521 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah))
522 ah->is_pciexpress = 0;
523
524 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
525 ath9k_hw_init_cal_settings(ah);
526
527 ah->ani_function = ATH9K_ANI_ALL;
528 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
529 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
530 if (!AR_SREV_9300_20_OR_LATER(ah))
531 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
532
533 ath9k_hw_init_mode_regs(ah);
534
535
536 if (ah->is_pciexpress)
537 ath9k_hw_configpcipowersave(ah, 0, 0);
538 else
539 ath9k_hw_disablepcie(ah);
540
541 if (!AR_SREV_9300_20_OR_LATER(ah))
542 ar9002_hw_cck_chan14_spread(ah);
543
544 r = ath9k_hw_post_init(ah);
545 if (r)
546 return r;
547
548 ath9k_hw_init_mode_gain_regs(ah);
549 r = ath9k_hw_fill_cap_info(ah);
550 if (r)
551 return r;
552
553 r = ath9k_hw_init_macaddr(ah);
554 if (r) {
555 DBG("ath9k: Failed to initialize MAC address\n");
556 return r;
557 }
558
559 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
560 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
561 else
562 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
563
564 common->state = ATH_HW_INITIALIZED;
565
566 return 0;
567 }
568
ath9k_hw_init(struct ath_hw * ah)569 int ath9k_hw_init(struct ath_hw *ah)
570 {
571 int ret;
572 struct ath_common *common = ath9k_hw_common(ah);
573
574 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
575 switch (ah->hw_version.devid) {
576 case AR5416_DEVID_PCI:
577 case AR5416_DEVID_PCIE:
578 case AR5416_AR9100_DEVID:
579 case AR9160_DEVID_PCI:
580 case AR9280_DEVID_PCI:
581 case AR9280_DEVID_PCIE:
582 case AR9285_DEVID_PCIE:
583 case AR9287_DEVID_PCI:
584 case AR9287_DEVID_PCIE:
585 case AR2427_DEVID_PCIE:
586 case AR9300_DEVID_PCIE:
587 case AR9300_DEVID_AR9485_PCIE:
588 case AR9300_DEVID_AR9340:
589 break;
590 default:
591 if (common->bus_ops->ath_bus_type == ATH_USB)
592 break;
593 DBG("ath9k: Hardware device ID 0x%04x not supported\n",
594 ah->hw_version.devid);
595 return -EOPNOTSUPP;
596 }
597
598 ret = __ath9k_hw_init(ah);
599 if (ret) {
600 DBG("ath9k: "
601 "Unable to initialize hardware; initialization status: %d\n",
602 ret);
603 return ret;
604 }
605
606 return 0;
607 }
608
ar9003_get_pll_sqsum_dvc(struct ath_hw * ah)609 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
610 {
611 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
612 udelay(100);
613 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
614
615 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
616 udelay(100);
617
618 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
619 }
620
ath9k_hw_init_pll(struct ath_hw * ah,struct ath9k_channel * chan)621 static void ath9k_hw_init_pll(struct ath_hw *ah,
622 struct ath9k_channel *chan)
623 {
624 u32 pll;
625
626 if (AR_SREV_9485(ah)) {
627
628 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
629 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
630 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
631 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
632 AR_CH0_DPLL2_KD, 0x40);
633 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
634 AR_CH0_DPLL2_KI, 0x4);
635
636 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
637 AR_CH0_BB_DPLL1_REFDIV, 0x5);
638 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
639 AR_CH0_BB_DPLL1_NINI, 0x58);
640 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
641 AR_CH0_BB_DPLL1_NFRAC, 0x0);
642
643 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
644 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
645 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
646 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
647 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
648 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
649
650 /* program BB PLL phase_shift to 0x6 */
651 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
652 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
653
654 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
655 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
656 udelay(1000);
657 } else if (AR_SREV_9340(ah)) {
658 u32 regval, pll2_divint, pll2_divfrac, refdiv;
659
660 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
661 udelay(1000);
662
663 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
664 udelay(100);
665
666 if (ah->is_clk_25mhz) {
667 pll2_divint = 0x54;
668 pll2_divfrac = 0x1eb85;
669 refdiv = 3;
670 } else {
671 pll2_divint = 88;
672 pll2_divfrac = 0;
673 refdiv = 5;
674 }
675
676 regval = REG_READ(ah, AR_PHY_PLL_MODE);
677 regval |= (0x1 << 16);
678 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
679 udelay(100);
680
681 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
682 (pll2_divint << 18) | pll2_divfrac);
683 udelay(100);
684
685 regval = REG_READ(ah, AR_PHY_PLL_MODE);
686 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
687 (0x4 << 26) | (0x18 << 19);
688 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
689 REG_WRITE(ah, AR_PHY_PLL_MODE,
690 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
691 udelay(1000);
692 }
693
694 pll = ath9k_hw_compute_pll_control(ah, chan);
695
696 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
697
698 if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
699 udelay(1000);
700
701 /* Switch the core clock for ar9271 to 117Mhz */
702 if (AR_SREV_9271(ah)) {
703 udelay(500);
704 REG_WRITE(ah, 0x50040, 0x304);
705 }
706
707 udelay(RTC_PLL_SETTLE_DELAY);
708
709 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
710
711 if (AR_SREV_9340(ah)) {
712 if (ah->is_clk_25mhz) {
713 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
714 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
715 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
716 } else {
717 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
718 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
719 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
720 }
721 udelay(100);
722 }
723 }
724
ath9k_hw_init_interrupt_masks(struct ath_hw * ah)725 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah)
726 {
727 u32 sync_default = AR_INTR_SYNC_DEFAULT;
728 u32 imr_reg = AR_IMR_TXERR |
729 AR_IMR_TXURN |
730 AR_IMR_RXERR |
731 AR_IMR_RXORN;;
732
733 if (AR_SREV_9340(ah))
734 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
735
736 if (AR_SREV_9300_20_OR_LATER(ah)) {
737 imr_reg |= AR_IMR_RXOK_HP;
738 if (ah->config.rx_intr_mitigation)
739 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
740 else
741 imr_reg |= AR_IMR_RXOK_LP;
742
743 } else {
744 if (ah->config.rx_intr_mitigation)
745 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
746 else
747 imr_reg |= AR_IMR_RXOK;
748 }
749
750 if (ah->config.tx_intr_mitigation)
751 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
752 else
753 imr_reg |= AR_IMR_TXOK;
754
755 ENABLE_REGWRITE_BUFFER(ah);
756
757 REG_WRITE(ah, AR_IMR, imr_reg);
758 // ah->imrs2_reg |= AR_IMR_S2_GTT;
759 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
760
761 if (!AR_SREV_9100(ah)) {
762 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
763 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
764 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
765 }
766
767 REGWRITE_BUFFER_FLUSH(ah);
768
769 if (AR_SREV_9300_20_OR_LATER(ah)) {
770 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
771 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
772 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
773 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
774 }
775 }
776
ath9k_hw_setslottime(struct ath_hw * ah,u32 us)777 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
778 {
779 u32 val = ath9k_hw_mac_to_clks(ah, us);
780 val = min(val, (u32) 0xFFFF);
781 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
782 }
783
ath9k_hw_set_ack_timeout(struct ath_hw * ah,u32 us)784 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
785 {
786 u32 val = ath9k_hw_mac_to_clks(ah, us);
787 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
788 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
789 }
790
ath9k_hw_set_cts_timeout(struct ath_hw * ah,u32 us)791 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
792 {
793 u32 val = ath9k_hw_mac_to_clks(ah, us);
794 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
795 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
796 }
797
ath9k_hw_set_global_txtimeout(struct ath_hw * ah,u32 tu)798 static int ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
799 {
800 if (tu > 0xFFFF) {
801 DBG("ath9k: "
802 "bad global tx timeout %d\n", tu);
803 ah->globaltxtimeout = (u32) -1;
804 return 0;
805 } else {
806 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
807 ah->globaltxtimeout = tu;
808 return 1;
809 }
810 }
811
ath9k_hw_init_global_settings(struct ath_hw * ah)812 void ath9k_hw_init_global_settings(struct ath_hw *ah)
813 {
814 int acktimeout;
815 int slottime;
816 int sifstime;
817
818 DBG2("ath9k: ah->misc_mode 0x%x\n",
819 ah->misc_mode);
820
821 if (ah->misc_mode != 0)
822 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
823
824 if ((ah->dev->channels + ah->dev->channel)->band == NET80211_BAND_5GHZ)
825 sifstime = 16;
826 else
827 sifstime = 10;
828
829 /* As defined by IEEE 802.11-2007 17.3.8.6 */
830 slottime = ah->slottime + 3 * ah->coverage_class;
831 acktimeout = slottime + sifstime;
832
833 /*
834 * Workaround for early ACK timeouts, add an offset to match the
835 * initval's 64us ack timeout value.
836 * This was initially only meant to work around an issue with delayed
837 * BA frames in some implementations, but it has been found to fix ACK
838 * timeout issues in other cases as well.
839 */
840 if ((ah->dev->channels + ah->dev->channel)->band == NET80211_BAND_2GHZ)
841 acktimeout += 64 - sifstime - ah->slottime;
842
843 ath9k_hw_setslottime(ah, ah->slottime);
844 ath9k_hw_set_ack_timeout(ah, acktimeout);
845 ath9k_hw_set_cts_timeout(ah, acktimeout);
846 if (ah->globaltxtimeout != (u32) -1)
847 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
848 }
849
ath9k_hw_deinit(struct ath_hw * ah)850 void ath9k_hw_deinit(struct ath_hw *ah)
851 {
852 struct ath_common *common = ath9k_hw_common(ah);
853
854 if (common->state < ATH_HW_INITIALIZED)
855 goto free_hw;
856
857 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
858
859 free_hw:
860 ath9k_hw_rf_free_ext_banks(ah);
861 }
862
863 /*******/
864 /* INI */
865 /*******/
866
ath9k_regd_get_ctl(struct ath_regulatory * reg,struct ath9k_channel * chan)867 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
868 {
869 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
870
871 if (IS_CHAN_B(chan))
872 ctl |= CTL_11B;
873 else if (IS_CHAN_G(chan))
874 ctl |= CTL_11G;
875 else
876 ctl |= CTL_11A;
877
878 return ctl;
879 }
880
881 /****************************************/
882 /* Reset and Channel Switching Routines */
883 /****************************************/
884
ath9k_hw_set_dma(struct ath_hw * ah)885 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
886 {
887 struct ath_common *common = ath9k_hw_common(ah);
888
889 ENABLE_REGWRITE_BUFFER(ah);
890
891 /*
892 * set AHB_MODE not to do cacheline prefetches
893 */
894 if (!AR_SREV_9300_20_OR_LATER(ah))
895 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
896
897 /*
898 * let mac dma reads be in 128 byte chunks
899 */
900 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
901
902 REGWRITE_BUFFER_FLUSH(ah);
903
904 /*
905 * Restore TX Trigger Level to its pre-reset value.
906 * The initial value depends on whether aggregation is enabled, and is
907 * adjusted whenever underruns are detected.
908 */
909 if (!AR_SREV_9300_20_OR_LATER(ah))
910 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
911
912 ENABLE_REGWRITE_BUFFER(ah);
913
914 /*
915 * let mac dma writes be in 128 byte chunks
916 */
917 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
918
919 /*
920 * Setup receive FIFO threshold to hold off TX activities
921 */
922 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
923
924 if (AR_SREV_9300_20_OR_LATER(ah)) {
925 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
926 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
927
928 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
929 ah->caps.rx_status_len);
930 }
931
932 /*
933 * reduce the number of usable entries in PCU TXBUF to avoid
934 * wrap around issues.
935 */
936 if (AR_SREV_9285(ah)) {
937 /* For AR9285 the number of Fifos are reduced to half.
938 * So set the usable tx buf size also to half to
939 * avoid data/delimiter underruns
940 */
941 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
942 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
943 } else if (!AR_SREV_9271(ah)) {
944 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
945 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
946 }
947
948 REGWRITE_BUFFER_FLUSH(ah);
949
950 if (AR_SREV_9300_20_OR_LATER(ah))
951 ath9k_hw_reset_txstatus_ring(ah);
952 }
953
ath9k_hw_set_operating_mode(struct ath_hw * ah)954 static void ath9k_hw_set_operating_mode(struct ath_hw *ah)
955 {
956 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
957 u32 set = AR_STA_ID1_KSRCH_MODE;
958
959 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
960
961 REG_RMW(ah, AR_STA_ID1, set, mask);
962 }
963
ath9k_hw_get_delta_slope_vals(struct ath_hw * ah __unused,u32 coef_scaled,u32 * coef_mantissa,u32 * coef_exponent)964 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah __unused, u32 coef_scaled,
965 u32 *coef_mantissa, u32 *coef_exponent)
966 {
967 u32 coef_exp, coef_man;
968
969 for (coef_exp = 31; coef_exp > 0; coef_exp--)
970 if ((coef_scaled >> coef_exp) & 0x1)
971 break;
972
973 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
974
975 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
976
977 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
978 *coef_exponent = coef_exp - 16;
979 }
980
ath9k_hw_set_reset(struct ath_hw * ah,int type)981 static int ath9k_hw_set_reset(struct ath_hw *ah, int type)
982 {
983 u32 rst_flags;
984 u32 tmpReg;
985
986 if (AR_SREV_9100(ah)) {
987 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
988 AR_RTC_DERIVED_CLK_PERIOD, 1);
989 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
990 }
991
992 ENABLE_REGWRITE_BUFFER(ah);
993
994 if (AR_SREV_9300_20_OR_LATER(ah)) {
995 REG_WRITE(ah, AR_WA, ah->WARegVal);
996 udelay(10);
997 }
998
999 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1000 AR_RTC_FORCE_WAKE_ON_INT);
1001
1002 if (AR_SREV_9100(ah)) {
1003 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1004 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1005 } else {
1006 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1007 if (tmpReg &
1008 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1009 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1010 u32 val;
1011 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1012
1013 val = AR_RC_HOSTIF;
1014 if (!AR_SREV_9300_20_OR_LATER(ah))
1015 val |= AR_RC_AHB;
1016 REG_WRITE(ah, AR_RC, val);
1017
1018 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1019 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1020
1021 rst_flags = AR_RTC_RC_MAC_WARM;
1022 if (type == ATH9K_RESET_COLD)
1023 rst_flags |= AR_RTC_RC_MAC_COLD;
1024 }
1025
1026 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1027
1028 REGWRITE_BUFFER_FLUSH(ah);
1029
1030 udelay(50);
1031
1032 REG_WRITE(ah, AR_RTC_RC, 0);
1033 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1034 DBG("ath9k: "
1035 "RTC stuck in MAC reset\n");
1036 return 0;
1037 }
1038
1039 if (!AR_SREV_9100(ah))
1040 REG_WRITE(ah, AR_RC, 0);
1041
1042 if (AR_SREV_9100(ah))
1043 udelay(50);
1044
1045 return 1;
1046 }
1047
ath9k_hw_set_reset_power_on(struct ath_hw * ah)1048 static int ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1049 {
1050 ENABLE_REGWRITE_BUFFER(ah);
1051
1052 if (AR_SREV_9300_20_OR_LATER(ah)) {
1053 REG_WRITE(ah, AR_WA, ah->WARegVal);
1054 udelay(10);
1055 }
1056
1057 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1058 AR_RTC_FORCE_WAKE_ON_INT);
1059
1060 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1061 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1062
1063 REG_WRITE(ah, AR_RTC_RESET, 0);
1064
1065 REGWRITE_BUFFER_FLUSH(ah);
1066
1067 if (!AR_SREV_9300_20_OR_LATER(ah))
1068 udelay(2);
1069
1070 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1071 REG_WRITE(ah, AR_RC, 0);
1072
1073 REG_WRITE(ah, AR_RTC_RESET, 1);
1074
1075 if (!ath9k_hw_wait(ah,
1076 AR_RTC_STATUS,
1077 AR_RTC_STATUS_M,
1078 AR_RTC_STATUS_ON,
1079 AH_WAIT_TIMEOUT)) {
1080 DBG("ath9k: "
1081 "RTC not waking up\n");
1082 return 0;
1083 }
1084
1085 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1086 }
1087
ath9k_hw_set_reset_reg(struct ath_hw * ah,u32 type)1088 static int ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1089 {
1090 if (AR_SREV_9300_20_OR_LATER(ah)) {
1091 REG_WRITE(ah, AR_WA, ah->WARegVal);
1092 udelay(10);
1093 }
1094
1095 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1096 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1097
1098 switch (type) {
1099 case ATH9K_RESET_POWER_ON:
1100 return ath9k_hw_set_reset_power_on(ah);
1101 case ATH9K_RESET_WARM:
1102 case ATH9K_RESET_COLD:
1103 return ath9k_hw_set_reset(ah, type);
1104 default:
1105 return 0;
1106 }
1107 }
1108
ath9k_hw_chip_reset(struct ath_hw * ah,struct ath9k_channel * chan)1109 static int ath9k_hw_chip_reset(struct ath_hw *ah,
1110 struct ath9k_channel *chan)
1111 {
1112 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1113 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1114 return 0;
1115 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1116 return 0;
1117
1118 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1119 return 0;
1120
1121 ah->chip_fullsleep = 0;
1122 ath9k_hw_init_pll(ah, chan);
1123 ath9k_hw_set_rfmode(ah, chan);
1124
1125 return 1;
1126 }
1127
ath9k_hw_channel_change(struct ath_hw * ah,struct ath9k_channel * chan)1128 static int ath9k_hw_channel_change(struct ath_hw *ah,
1129 struct ath9k_channel *chan)
1130 {
1131 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1132 struct net80211_channel *channel = chan->chan;
1133 u32 qnum;
1134 int r;
1135
1136 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1137 if (ath9k_hw_numtxpending(ah, qnum)) {
1138 DBG("ath9k: "
1139 "Transmit frames pending on queue %d\n", qnum);
1140 return 0;
1141 }
1142 }
1143
1144 if (!ath9k_hw_rfbus_req(ah)) {
1145 DBG("ath9k: Could not kill baseband RX\n");
1146 return 0;
1147 }
1148
1149 ath9k_hw_set_channel_regs(ah, chan);
1150
1151 r = ath9k_hw_rf_set_freq(ah, chan);
1152 if (r) {
1153 DBG("ath9k: Failed to set channel\n");
1154 return 0;
1155 }
1156 ath9k_hw_set_clockrate(ah);
1157
1158 ah->eep_ops->set_txpower(ah, chan,
1159 ath9k_regd_get_ctl(regulatory, chan),
1160 0,
1161 channel->maxpower * 2,
1162 min((u32) MAX_RATE_POWER,
1163 (u32) regulatory->power_limit), 0);
1164
1165 ath9k_hw_rfbus_done(ah);
1166
1167 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1168 ath9k_hw_set_delta_slope(ah, chan);
1169
1170 ath9k_hw_spur_mitigate_freq(ah, chan);
1171
1172 return 1;
1173 }
1174
ath9k_hw_apply_gpio_override(struct ath_hw * ah)1175 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1176 {
1177 u32 gpio_mask = ah->gpio_mask;
1178 int i;
1179
1180 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1181 if (!(gpio_mask & 1))
1182 continue;
1183
1184 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1185 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1186 }
1187 }
1188
ath9k_hw_check_alive(struct ath_hw * ah)1189 int ath9k_hw_check_alive(struct ath_hw *ah)
1190 {
1191 int count = 50;
1192 u32 reg;
1193
1194 if (AR_SREV_9285_12_OR_LATER(ah))
1195 return 1;
1196
1197 do {
1198 reg = REG_READ(ah, AR_OBS_BUS_1);
1199
1200 if ((reg & 0x7E7FFFEF) == 0x00702400)
1201 continue;
1202
1203 switch (reg & 0x7E000B00) {
1204 case 0x1E000000:
1205 case 0x52000B00:
1206 case 0x18000B00:
1207 continue;
1208 default:
1209 return 1;
1210 }
1211 } while (count-- > 0);
1212
1213 return 0;
1214 }
1215
ath9k_hw_reset(struct ath_hw * ah,struct ath9k_channel * chan,struct ath9k_hw_cal_data * caldata,int bChannelChange)1216 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1217 struct ath9k_hw_cal_data *caldata, int bChannelChange)
1218 {
1219 struct ath_common *common = ath9k_hw_common(ah);
1220 u32 saveLedState;
1221 struct ath9k_channel *curchan = ah->curchan;
1222 u32 saveDefAntenna;
1223 u32 macStaId1;
1224 int i, r;
1225
1226 ah->txchainmask = common->tx_chainmask;
1227 ah->rxchainmask = common->rx_chainmask;
1228
1229 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1230 return -EIO;
1231
1232 if (curchan && !ah->chip_fullsleep)
1233 ath9k_hw_getnf(ah, curchan);
1234
1235 ah->caldata = caldata;
1236 if (caldata &&
1237 (chan->channel != caldata->channel ||
1238 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1239 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1240 /* Operating channel changed, reset channel calibration data */
1241 memset(caldata, 0, sizeof(*caldata));
1242 ath9k_init_nfcal_hist_buffer(ah, chan);
1243 }
1244
1245 if (bChannelChange &&
1246 (ah->chip_fullsleep != 1) &&
1247 (ah->curchan != NULL) &&
1248 (chan->channel != ah->curchan->channel) &&
1249 ((chan->channelFlags & CHANNEL_ALL) ==
1250 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1251 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1252
1253 if (ath9k_hw_channel_change(ah, chan)) {
1254 ath9k_hw_loadnf(ah, ah->curchan);
1255 ath9k_hw_start_nfcal(ah, 1);
1256 if (AR_SREV_9271(ah))
1257 ar9002_hw_load_ani_reg(ah, chan);
1258 return 0;
1259 }
1260 }
1261
1262 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1263 if (saveDefAntenna == 0)
1264 saveDefAntenna = 1;
1265
1266 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1267
1268 saveLedState = REG_READ(ah, AR_CFG_LED) &
1269 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1270 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1271
1272 ath9k_hw_mark_phy_inactive(ah);
1273
1274 ah->paprd_table_write_done = 0;
1275
1276 /* Only required on the first reset */
1277 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1278 REG_WRITE(ah,
1279 AR9271_RESET_POWER_DOWN_CONTROL,
1280 AR9271_RADIO_RF_RST);
1281 udelay(50);
1282 }
1283
1284 if (!ath9k_hw_chip_reset(ah, chan)) {
1285 DBG("ath9k: Chip reset failed\n");
1286 return -EINVAL;
1287 }
1288
1289 /* Only required on the first reset */
1290 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1291 ah->htc_reset_init = 0;
1292 REG_WRITE(ah,
1293 AR9271_RESET_POWER_DOWN_CONTROL,
1294 AR9271_GATE_MAC_CTL);
1295 udelay(50);
1296 }
1297
1298 if (AR_SREV_9280_20_OR_LATER(ah))
1299 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1300
1301 if (!AR_SREV_9300_20_OR_LATER(ah))
1302 ar9002_hw_enable_async_fifo(ah);
1303
1304 r = ath9k_hw_process_ini(ah, chan);
1305 if (r)
1306 return r;
1307
1308 /* Setup MFP options for CCMP */
1309 if (AR_SREV_9280_20_OR_LATER(ah)) {
1310 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1311 * frames when constructing CCMP AAD. */
1312 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1313 0xc7ff);
1314 ah->sw_mgmt_crypto = 0;
1315 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1316 /* Disable hardware crypto for management frames */
1317 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1318 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1319 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1320 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1321 ah->sw_mgmt_crypto = 1;
1322 } else
1323 ah->sw_mgmt_crypto = 1;
1324
1325 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1326 ath9k_hw_set_delta_slope(ah, chan);
1327
1328 ath9k_hw_spur_mitigate_freq(ah, chan);
1329 ah->eep_ops->set_board_values(ah, chan);
1330
1331 ENABLE_REGWRITE_BUFFER(ah);
1332
1333 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1334 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1335 | macStaId1
1336 | AR_STA_ID1_RTS_USE_DEF
1337 | (ah->config.
1338 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1339 | ah->sta_id1_defaults);
1340 ath_hw_setbssidmask(common);
1341 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1342 ath9k_hw_write_associd(ah);
1343 REG_WRITE(ah, AR_ISR, ~0);
1344 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1345
1346 REGWRITE_BUFFER_FLUSH(ah);
1347
1348 ath9k_hw_set_operating_mode(ah);
1349
1350 r = ath9k_hw_rf_set_freq(ah, chan);
1351 if (r)
1352 return r;
1353
1354 ath9k_hw_set_clockrate(ah);
1355
1356 ENABLE_REGWRITE_BUFFER(ah);
1357
1358 for (i = 0; i < AR_NUM_DCU; i++)
1359 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1360
1361 REGWRITE_BUFFER_FLUSH(ah);
1362
1363 ah->intr_txqs = 0;
1364 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1365 ath9k_hw_resettxqueue(ah, i);
1366
1367 ath9k_hw_init_interrupt_masks(ah);
1368 ath9k_hw_ani_cache_ini_regs(ah);
1369
1370 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1371 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1372
1373 ath9k_hw_init_global_settings(ah);
1374
1375 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1376 ar9002_hw_update_async_fifo(ah);
1377 ar9002_hw_enable_wep_aggregation(ah);
1378 }
1379
1380 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1381
1382 ath9k_hw_set_dma(ah);
1383
1384 REG_WRITE(ah, AR_OBS, 8);
1385
1386 if (ah->config.rx_intr_mitigation) {
1387 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1388 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1389 }
1390
1391 if (ah->config.tx_intr_mitigation) {
1392 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1393 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1394 }
1395
1396 ath9k_hw_init_bb(ah, chan);
1397
1398 if (!ath9k_hw_init_cal(ah, chan))
1399 return -EIO;
1400
1401 ENABLE_REGWRITE_BUFFER(ah);
1402
1403 ath9k_hw_restore_chainmask(ah);
1404 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1405
1406 REGWRITE_BUFFER_FLUSH(ah);
1407
1408 /*
1409 * For big endian systems turn on swapping for descriptors
1410 */
1411 if (AR_SREV_9100(ah)) {
1412 u32 mask;
1413 mask = REG_READ(ah, AR_CFG);
1414 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1415 DBG2("ath9k: "
1416 "CFG Byte Swap Set 0x%x\n", mask);
1417 } else {
1418 mask =
1419 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1420 REG_WRITE(ah, AR_CFG, mask);
1421 DBG2("ath9k: "
1422 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1423 }
1424 } else {
1425 if (common->bus_ops->ath_bus_type == ATH_USB) {
1426 /* Configure AR9271 target WLAN */
1427 if (AR_SREV_9271(ah))
1428 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1429 else
1430 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1431 }
1432 #if __BYTE_ORDER == __BIG_ENDIAN
1433 else if (AR_SREV_9340(ah))
1434 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1435 else
1436 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1437 #endif
1438 }
1439
1440 if (AR_SREV_9300_20_OR_LATER(ah)) {
1441 ar9003_hw_disable_phy_restart(ah);
1442 }
1443
1444 ath9k_hw_apply_gpio_override(ah);
1445
1446 return 0;
1447 }
1448
1449 /******************************/
1450 /* Power Management (Chipset) */
1451 /******************************/
1452
1453 /*
1454 * Notify Power Mgt is disabled in self-generated frames.
1455 * If requested, force chip to sleep.
1456 */
ath9k_set_power_sleep(struct ath_hw * ah,int setChip)1457 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1458 {
1459 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1460 if (setChip) {
1461 /*
1462 * Clear the RTC force wake bit to allow the
1463 * mac to go to sleep.
1464 */
1465 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1466 AR_RTC_FORCE_WAKE_EN);
1467 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1468 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1469
1470 /* Shutdown chip. Active low */
1471 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1472 REG_CLR_BIT(ah, (AR_RTC_RESET),
1473 AR_RTC_RESET_EN);
1474 }
1475
1476 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1477 if (AR_SREV_9300_20_OR_LATER(ah))
1478 REG_WRITE(ah, AR_WA,
1479 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1480 }
1481
ath9k_hw_set_power_awake(struct ath_hw * ah,int setChip)1482 static int ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1483 {
1484 u32 val;
1485 int i;
1486
1487 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1488 if (AR_SREV_9300_20_OR_LATER(ah)) {
1489 REG_WRITE(ah, AR_WA, ah->WARegVal);
1490 udelay(10);
1491 }
1492
1493 if (setChip) {
1494 if ((REG_READ(ah, AR_RTC_STATUS) &
1495 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1496 if (ath9k_hw_set_reset_reg(ah,
1497 ATH9K_RESET_POWER_ON) != 1) {
1498 return 0;
1499 }
1500 if (!AR_SREV_9300_20_OR_LATER(ah))
1501 ath9k_hw_init_pll(ah, NULL);
1502 }
1503 if (AR_SREV_9100(ah))
1504 REG_SET_BIT(ah, AR_RTC_RESET,
1505 AR_RTC_RESET_EN);
1506
1507 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1508 AR_RTC_FORCE_WAKE_EN);
1509 udelay(50);
1510
1511 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1512 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1513 if (val == AR_RTC_STATUS_ON)
1514 break;
1515 udelay(50);
1516 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1517 AR_RTC_FORCE_WAKE_EN);
1518 }
1519 if (i == 0) {
1520 DBG("ath9k: "
1521 "Failed to wakeup in %dus\n",
1522 POWER_UP_TIME / 20);
1523 return 0;
1524 }
1525 }
1526
1527 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1528
1529 return 1;
1530 }
1531
ath9k_hw_setpower(struct ath_hw * ah,enum ath9k_power_mode mode)1532 int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1533 {
1534 int status = 1, setChip = 1;
1535 static const char *modes[] = {
1536 "AWAKE",
1537 "FULL-SLEEP",
1538 "NETWORK SLEEP",
1539 "UNDEFINED"
1540 };
1541
1542 if (ah->power_mode == mode)
1543 return status;
1544
1545 DBG2("ath9k: %s -> %s\n",
1546 modes[ah->power_mode], modes[mode]);
1547
1548 switch (mode) {
1549 case ATH9K_PM_AWAKE:
1550 status = ath9k_hw_set_power_awake(ah, setChip);
1551 break;
1552 case ATH9K_PM_FULL_SLEEP:
1553 ath9k_set_power_sleep(ah, setChip);
1554 ah->chip_fullsleep = 1;
1555 break;
1556 default:
1557 DBG("ath9k: Unknown power mode %d\n", mode);
1558 return 0;
1559 }
1560 ah->power_mode = mode;
1561
1562 return status;
1563 }
1564
1565 /*******************/
1566 /* HW Capabilities */
1567 /*******************/
1568
ath9k_hw_fill_cap_info(struct ath_hw * ah)1569 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1570 {
1571 struct ath9k_hw_capabilities *pCap = &ah->caps;
1572 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1573 struct ath_common *common = ath9k_hw_common(ah);
1574
1575 u16 eeval;
1576 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1577
1578 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1579 regulatory->current_rd = eeval;
1580
1581 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1582 if (AR_SREV_9285_12_OR_LATER(ah))
1583 eeval |= AR9285_RDEXT_DEFAULT;
1584 regulatory->current_rd_ext = eeval;
1585
1586 if (ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1587 if (regulatory->current_rd == 0x64 ||
1588 regulatory->current_rd == 0x65)
1589 regulatory->current_rd += 5;
1590 else if (regulatory->current_rd == 0x41)
1591 regulatory->current_rd = 0x43;
1592 DBG2("ath9k: "
1593 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1594 }
1595
1596 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1597 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1598 DBG("ath9k: "
1599 "no band has been marked as supported in EEPROM\n");
1600 return -EINVAL;
1601 }
1602
1603 if (eeval & AR5416_OPFLAGS_11A)
1604 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1605
1606 if (eeval & AR5416_OPFLAGS_11G)
1607 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1608
1609 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1610 /*
1611 * For AR9271 we will temporarilly uses the rx chainmax as read from
1612 * the EEPROM.
1613 */
1614 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1615 !(eeval & AR5416_OPFLAGS_11A) &&
1616 !(AR_SREV_9271(ah)))
1617 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1618 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1619 else if (AR_SREV_9100(ah))
1620 pCap->rx_chainmask = 0x7;
1621 else
1622 /* Use rx_chainmask from EEPROM. */
1623 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1624
1625 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1626
1627 /* enable key search for every frame in an aggregate */
1628 if (AR_SREV_9300_20_OR_LATER(ah))
1629 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1630
1631 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1632
1633 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1634
1635 if (AR_SREV_9271(ah))
1636 pCap->num_gpio_pins = AR9271_NUM_GPIO;
1637 else if (AR_DEVID_7010(ah))
1638 pCap->num_gpio_pins = AR7010_NUM_GPIO;
1639 else if (AR_SREV_9285_12_OR_LATER(ah))
1640 pCap->num_gpio_pins = AR9285_NUM_GPIO;
1641 else if (AR_SREV_9280_20_OR_LATER(ah))
1642 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1643 else
1644 pCap->num_gpio_pins = AR_NUM_GPIO;
1645
1646 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1647 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1648 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1649 } else {
1650 pCap->rts_aggr_limit = (8 * 1024);
1651 }
1652
1653 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1654 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1655 ah->rfkill_gpio =
1656 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1657 ah->rfkill_polarity =
1658 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1659
1660 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1661 }
1662
1663 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1664
1665 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1666 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1667 else
1668 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1669
1670 if (AR_SREV_9300_20_OR_LATER(ah)) {
1671 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
1672 if (!AR_SREV_9485(ah))
1673 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1674
1675 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1676 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1677 pCap->rx_status_len = sizeof(struct ar9003_rxs);
1678 pCap->tx_desc_len = sizeof(struct ar9003_txc);
1679 pCap->txs_len = sizeof(struct ar9003_txs);
1680 if (!ah->config.paprd_disable &&
1681 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1682 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1683 } else {
1684 pCap->tx_desc_len = sizeof(struct ath_desc);
1685 if (AR_SREV_9280_20(ah) &&
1686 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1687 AR5416_EEP_MINOR_VER_16) ||
1688 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
1689 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
1690 }
1691
1692 if (AR_SREV_9300_20_OR_LATER(ah))
1693 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
1694
1695 if (AR_SREV_9300_20_OR_LATER(ah))
1696 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
1697
1698 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
1699 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1700
1701 if (AR_SREV_9285(ah))
1702 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
1703 ant_div_ctl1 =
1704 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1705 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1706 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
1707 }
1708 if (AR_SREV_9300_20_OR_LATER(ah)) {
1709 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
1710 pCap->hw_caps |= ATH9K_HW_CAP_APM;
1711 }
1712
1713
1714 if (AR_SREV_9485(ah)) {
1715 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1716 /*
1717 * enable the diversity-combining algorithm only when
1718 * both enable_lna_div and enable_fast_div are set
1719 * Table for Diversity
1720 * ant_div_alt_lnaconf bit 0-1
1721 * ant_div_main_lnaconf bit 2-3
1722 * ant_div_alt_gaintb bit 4
1723 * ant_div_main_gaintb bit 5
1724 * enable_ant_div_lnadiv bit 6
1725 * enable_ant_fast_div bit 7
1726 */
1727 if ((ant_div_ctl1 >> 0x6) == 0x3)
1728 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
1729 }
1730
1731 if (AR_SREV_9485_10(ah)) {
1732 pCap->pcie_lcr_extsync_en = 1;
1733 pCap->pcie_lcr_offset = 0x80;
1734 }
1735
1736 tx_chainmask = pCap->tx_chainmask;
1737 rx_chainmask = pCap->rx_chainmask;
1738 while (tx_chainmask || rx_chainmask) {
1739 if (tx_chainmask & BIT(0))
1740 pCap->max_txchains++;
1741 if (rx_chainmask & BIT(0))
1742 pCap->max_rxchains++;
1743
1744 tx_chainmask >>= 1;
1745 rx_chainmask >>= 1;
1746 }
1747
1748 return 0;
1749 }
1750
1751 /****************************/
1752 /* GPIO / RFKILL / Antennae */
1753 /****************************/
1754
ath9k_hw_gpio_cfg_output_mux(struct ath_hw * ah,u32 gpio,u32 type)1755 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
1756 u32 gpio, u32 type)
1757 {
1758 int addr;
1759 u32 gpio_shift, tmp;
1760
1761 if (gpio > 11)
1762 addr = AR_GPIO_OUTPUT_MUX3;
1763 else if (gpio > 5)
1764 addr = AR_GPIO_OUTPUT_MUX2;
1765 else
1766 addr = AR_GPIO_OUTPUT_MUX1;
1767
1768 gpio_shift = (gpio % 6) * 5;
1769
1770 if (AR_SREV_9280_20_OR_LATER(ah)
1771 || (addr != AR_GPIO_OUTPUT_MUX1)) {
1772 REG_RMW(ah, addr, (type << gpio_shift),
1773 (0x1f << gpio_shift));
1774 } else {
1775 tmp = REG_READ(ah, addr);
1776 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
1777 tmp &= ~(0x1f << gpio_shift);
1778 tmp |= (type << gpio_shift);
1779 REG_WRITE(ah, addr, tmp);
1780 }
1781 }
1782
ath9k_hw_cfg_gpio_input(struct ath_hw * ah,u32 gpio)1783 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
1784 {
1785 u32 gpio_shift;
1786
1787 if (AR_DEVID_7010(ah)) {
1788 gpio_shift = gpio;
1789 REG_RMW(ah, AR7010_GPIO_OE,
1790 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
1791 (AR7010_GPIO_OE_MASK << gpio_shift));
1792 return;
1793 }
1794
1795 gpio_shift = gpio << 1;
1796 REG_RMW(ah,
1797 AR_GPIO_OE_OUT,
1798 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
1799 (AR_GPIO_OE_OUT_DRV << gpio_shift));
1800 }
1801
ath9k_hw_gpio_get(struct ath_hw * ah,u32 gpio)1802 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
1803 {
1804 #define MS_REG_READ(x, y) \
1805 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
1806
1807 if (gpio >= ah->caps.num_gpio_pins)
1808 return 0xffffffff;
1809
1810 if (AR_DEVID_7010(ah)) {
1811 u32 val;
1812 val = REG_READ(ah, AR7010_GPIO_IN);
1813 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
1814 } else if (AR_SREV_9300_20_OR_LATER(ah))
1815 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
1816 AR_GPIO_BIT(gpio)) != 0;
1817 else if (AR_SREV_9271(ah))
1818 return MS_REG_READ(AR9271, gpio) != 0;
1819 else if (AR_SREV_9287_11_OR_LATER(ah))
1820 return MS_REG_READ(AR9287, gpio) != 0;
1821 else if (AR_SREV_9285_12_OR_LATER(ah))
1822 return MS_REG_READ(AR9285, gpio) != 0;
1823 else if (AR_SREV_9280_20_OR_LATER(ah))
1824 return MS_REG_READ(AR928X, gpio) != 0;
1825 else
1826 return MS_REG_READ(AR, gpio) != 0;
1827 }
1828
ath9k_hw_cfg_output(struct ath_hw * ah,u32 gpio,u32 ah_signal_type)1829 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
1830 u32 ah_signal_type)
1831 {
1832 u32 gpio_shift;
1833
1834 if (AR_DEVID_7010(ah)) {
1835 gpio_shift = gpio;
1836 REG_RMW(ah, AR7010_GPIO_OE,
1837 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
1838 (AR7010_GPIO_OE_MASK << gpio_shift));
1839 return;
1840 }
1841
1842 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
1843 gpio_shift = 2 * gpio;
1844 REG_RMW(ah,
1845 AR_GPIO_OE_OUT,
1846 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
1847 (AR_GPIO_OE_OUT_DRV << gpio_shift));
1848 }
1849
ath9k_hw_set_gpio(struct ath_hw * ah,u32 gpio,u32 val)1850 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
1851 {
1852 if (AR_DEVID_7010(ah)) {
1853 val = val ? 0 : 1;
1854 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
1855 AR_GPIO_BIT(gpio));
1856 return;
1857 }
1858
1859 if (AR_SREV_9271(ah))
1860 val = ~val;
1861
1862 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
1863 AR_GPIO_BIT(gpio));
1864 }
1865
ath9k_hw_getdefantenna(struct ath_hw * ah)1866 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
1867 {
1868 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
1869 }
1870
ath9k_hw_setantenna(struct ath_hw * ah,u32 antenna)1871 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
1872 {
1873 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
1874 }
1875
1876 /*********************/
1877 /* General Operation */
1878 /*********************/
1879
ath9k_hw_getrxfilter(struct ath_hw * ah)1880 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
1881 {
1882 u32 bits = REG_READ(ah, AR_RX_FILTER);
1883 u32 phybits = REG_READ(ah, AR_PHY_ERR);
1884
1885 if (phybits & AR_PHY_ERR_RADAR)
1886 bits |= ATH9K_RX_FILTER_PHYRADAR;
1887 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
1888 bits |= ATH9K_RX_FILTER_PHYERR;
1889
1890 return bits;
1891 }
1892
ath9k_hw_setrxfilter(struct ath_hw * ah,u32 bits)1893 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
1894 {
1895 u32 phybits;
1896
1897 ENABLE_REGWRITE_BUFFER(ah);
1898
1899 REG_WRITE(ah, AR_RX_FILTER, bits);
1900
1901 phybits = 0;
1902 if (bits & ATH9K_RX_FILTER_PHYRADAR)
1903 phybits |= AR_PHY_ERR_RADAR;
1904 if (bits & ATH9K_RX_FILTER_PHYERR)
1905 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
1906 REG_WRITE(ah, AR_PHY_ERR, phybits);
1907
1908 if (phybits)
1909 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
1910 else
1911 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
1912
1913 REGWRITE_BUFFER_FLUSH(ah);
1914 }
1915
ath9k_hw_phy_disable(struct ath_hw * ah)1916 int ath9k_hw_phy_disable(struct ath_hw *ah)
1917 {
1918 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1919 return 0;
1920
1921 ath9k_hw_init_pll(ah, NULL);
1922 return 1;
1923 }
1924
ath9k_hw_disable(struct ath_hw * ah)1925 int ath9k_hw_disable(struct ath_hw *ah)
1926 {
1927 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1928 return 0;
1929
1930 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
1931 return 0;
1932
1933 ath9k_hw_init_pll(ah, NULL);
1934 return 1;
1935 }
1936
ath9k_hw_set_txpowerlimit(struct ath_hw * ah,u32 limit,int test)1937 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, int test)
1938 {
1939 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1940 struct ath9k_channel *chan = ah->curchan;
1941 struct net80211_channel *channel = chan->chan;
1942
1943 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
1944
1945 ah->eep_ops->set_txpower(ah, chan,
1946 ath9k_regd_get_ctl(regulatory, chan),
1947 0,
1948 channel->maxpower * 2,
1949 min((u32) MAX_RATE_POWER,
1950 (u32) regulatory->power_limit), test);
1951 }
1952
ath9k_hw_setopmode(struct ath_hw * ah)1953 void ath9k_hw_setopmode(struct ath_hw *ah)
1954 {
1955 ath9k_hw_set_operating_mode(ah);
1956 }
1957
ath9k_hw_setmcastfilter(struct ath_hw * ah,u32 filter0,u32 filter1)1958 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
1959 {
1960 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
1961 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
1962 }
1963
ath9k_hw_write_associd(struct ath_hw * ah)1964 void ath9k_hw_write_associd(struct ath_hw *ah)
1965 {
1966 struct ath_common *common = ath9k_hw_common(ah);
1967
1968 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
1969 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
1970 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
1971 }
1972
ath9k_hw_set11nmac2040(struct ath_hw * ah)1973 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
1974 {
1975 u32 macmode;
1976
1977 macmode = 0;
1978
1979 REG_WRITE(ah, AR_2040_MODE, macmode);
1980 }
1981
1982 static struct {
1983 u32 version;
1984 const char * name;
1985 } ath_mac_bb_names[] = {
1986 /* Devices with external radios */
1987 { AR_SREV_VERSION_5416_PCI, "5416" },
1988 { AR_SREV_VERSION_5416_PCIE, "5418" },
1989 { AR_SREV_VERSION_9100, "9100" },
1990 { AR_SREV_VERSION_9160, "9160" },
1991 /* Single-chip solutions */
1992 { AR_SREV_VERSION_9280, "9280" },
1993 { AR_SREV_VERSION_9285, "9285" },
1994 { AR_SREV_VERSION_9287, "9287" },
1995 { AR_SREV_VERSION_9271, "9271" },
1996 { AR_SREV_VERSION_9300, "9300" },
1997 { AR_SREV_VERSION_9485, "9485" },
1998 };
1999
2000 /* For devices with external radios */
2001 static struct {
2002 u16 version;
2003 const char * name;
2004 } ath_rf_names[] = {
2005 { 0, "5133" },
2006 { AR_RAD5133_SREV_MAJOR, "5133" },
2007 { AR_RAD5122_SREV_MAJOR, "5122" },
2008 { AR_RAD2133_SREV_MAJOR, "2133" },
2009 { AR_RAD2122_SREV_MAJOR, "2122" }
2010 };
2011
2012 /*
2013 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2014 */
ath9k_hw_mac_bb_name(u32 mac_bb_version)2015 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2016 {
2017 unsigned int i;
2018
2019 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2020 if (ath_mac_bb_names[i].version == mac_bb_version) {
2021 return ath_mac_bb_names[i].name;
2022 }
2023 }
2024
2025 return "????";
2026 }
2027
2028 /*
2029 * Return the RF name. "????" is returned if the RF is unknown.
2030 * Used for devices with external radios.
2031 */
ath9k_hw_rf_name(u16 rf_version)2032 static const char *ath9k_hw_rf_name(u16 rf_version)
2033 {
2034 unsigned int i;
2035
2036 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2037 if (ath_rf_names[i].version == rf_version) {
2038 return ath_rf_names[i].name;
2039 }
2040 }
2041
2042 return "????";
2043 }
2044
ath9k_hw_name(struct ath_hw * ah,char * hw_name,size_t len)2045 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2046 {
2047 int used;
2048
2049 /* chipsets >= AR9280 are single-chip */
2050 if (AR_SREV_9280_20_OR_LATER(ah)) {
2051 used = snprintf(hw_name, len,
2052 "Atheros AR%s Rev:%x",
2053 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2054 ah->hw_version.macRev);
2055 }
2056 else {
2057 used = snprintf(hw_name, len,
2058 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2059 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2060 ah->hw_version.macRev,
2061 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2062 AR_RADIO_SREV_MAJOR)),
2063 ah->hw_version.phyRev);
2064 }
2065
2066 hw_name[used] = '\0';
2067 }
2068