1 /* Copyright 2013-2017 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #ifndef __SPIRA_H
18 #define __SPIRA_H
19
20 #include "hdif.h"
21
22 /*
23 * To help the FSP to distinguish between physical address and TCE mapped address.
24 * Also to help hostboot to distinguish physical and relative address.
25 */
26 #define HRMOR_BIT (1ul << 63)
27
28 /*
29 * The SPIRA structure
30 *
31 * NOTE: This is one of the only HDIF structure that we layout entirely
32 * as a C struct because it's provided by us to the FSP. Almost everything
33 * else is generated by the FSP, and thus must be "parsed" since the various
34 * offsets and alignments might change.
35 */
36
37 #define SPIRA_VERSION 0x20 /* Like 730 ? */
38
39 struct spira_ntuple {
40 __be64 addr;
41 __be16 alloc_cnt;
42 __be16 act_cnt;
43 __be32 alloc_len;
44 __be32 act_len;
45 __be32 tce_off;
46 __be64 padding;
47 } __packed;
48
49 #define SPIRA_NTUPLES_COUNT 0x19
50
51 struct spira_ntuples {
52 struct HDIF_array_hdr array_hdr;
53 struct spira_ntuple sp_subsys; /* 0x040 */
54 struct spira_ntuple ipl_parms; /* 0x060 */
55 struct spira_ntuple nt_enclosure_vpd; /* 0x080 */
56 struct spira_ntuple slca; /* 0x0a0 */
57 struct spira_ntuple backplane_vpd; /* 0x0c0 */
58 struct spira_ntuple system_vpd; /* 0x0e0 */
59 struct spira_ntuple chip_tod; /* 0x100 */
60 struct spira_ntuple proc_init; /* 0x120 */
61 struct spira_ntuple clock_vpd; /* 0x140 */
62 struct spira_ntuple anchor_vpd; /* 0x160 */
63 struct spira_ntuple op_panel_vpd; /* 0x180 */
64 struct spira_ntuple ext_cache_fru_vpd; /* 0x1a0 */
65 struct spira_ntuple misc_cec_fru_vpd; /* 0x1c0 */
66 struct spira_ntuple paca; /* 0x1e0 */
67 struct spira_ntuple ms_vpd; /* 0x200 */
68 struct spira_ntuple cec_iohub_fru; /* 0x220 */
69 struct spira_ntuple cpu_ctrl; /* 0x240 */
70 struct spira_ntuple mdump_src; /* 0x260 */
71 struct spira_ntuple mdump_dst; /* 0x280 */
72 struct spira_ntuple mdump_res; /* 0x2a0 */
73 struct spira_ntuple heap; /* 0x2c0 */
74 struct spira_ntuple pcia; /* 0x2e0 */
75 struct spira_ntuple proc_chip; /* 0x300 */
76 struct spira_ntuple hs_data; /* 0x320 */
77 struct spira_ntuple ipmi_sensor; /* 0x360 */
78 struct spira_ntuple node_stb_data; /* 0x380 */
79 };
80
81 struct spira {
82 struct HDIF_common_hdr hdr;
83 struct HDIF_idata_ptr ntuples_ptr;
84 __be64 pad;
85 struct spira_ntuples ntuples;
86 /*
87 * We reserve 0xc0 rather than 0x4c0 so we fit SPIRAH/SPIRAS here
88 * while preserving compatibility with existing P7/P8 systems.
89 *
90 * According to FSP engineers, this is an okay thing to do.
91 */
92 u8 reserved[0x80];
93 } __packed __align(0x100);
94
95 extern struct spira spira;
96
97 /* SPIRA-H signature */
98 #define SPIRAH_HDIF_SIG "SPIRAH"
99
100 /* First version of the secure boot compliant design. */
101 #define SPIRAH_VERSION 0x50
102
103 /* N-tuples in SPIRAH */
104 #define SPIRAH_NTUPLES_COUNT 0x6
105
106 struct spirah_ntuples {
107 struct HDIF_array_hdr array_hdr; /* 0x030 */
108 struct spira_ntuple hs_data_area; /* 0x040 */
109 struct spira_ntuple proc_init; /* 0x060 */
110 struct spira_ntuple cpu_ctrl; /* 0x080 */
111 struct spira_ntuple mdump_src; /* 0x0a0 */
112 struct spira_ntuple mdump_dst; /* 0x0c0 */
113 struct spira_ntuple mdump_res; /* 0x0e0 */
114 struct spira_ntuple proc_dump_area; /* 0x100 */
115 };
116
117 struct spirah {
118 struct HDIF_common_hdr hdr;
119 struct HDIF_idata_ptr ntuples_ptr;
120 __be64 pad;
121 struct spirah_ntuples ntuples;
122 u8 reserved[0xE0];
123 } __packed __align(0x100);
124
125 extern struct spirah spirah;
126
127 /* SPIRA-S signature */
128 #define SPIRAS_HDIF_SIG "SPIRAS"
129
130 /* First version on 810 release */
131 #define SPIRAS_VERSION_P8 0x40
132 #define SPIRAS_VERSION_P9 0x50
133
134 /* N-tuples in SPIRAS */
135 #define SPIRAS_NTUPLES_COUNT 0x10
136
137 struct spiras_ntuples {
138 struct HDIF_array_hdr array_hdr; /* 0x030 */
139 struct spira_ntuple sp_subsys; /* 0x040 */
140 struct spira_ntuple ipl_parms; /* 0x060 */
141 struct spira_ntuple nt_enclosure_vpd; /* 0x080 */
142 struct spira_ntuple slca; /* 0x0a0 */
143 struct spira_ntuple backplane_vpd; /* 0x0c0 */
144 struct spira_ntuple system_vpd; /* 0x0e0 */
145 struct spira_ntuple clock_vpd; /* 0x100 */
146 struct spira_ntuple anchor_vpd; /* 0x120 */
147 struct spira_ntuple op_panel_vpd; /* 0x140 */
148 struct spira_ntuple misc_cec_fru_vpd; /* 0x160 */
149 struct spira_ntuple ms_vpd; /* 0x180 */
150 struct spira_ntuple cec_iohub_fru; /* 0x1a0 */
151 struct spira_ntuple pcia; /* 0x1c0 */
152 struct spira_ntuple proc_chip; /* 0x1e0 */
153 struct spira_ntuple hs_data; /* 0x200 */
154 struct spira_ntuple hbrt_data; /* 0x220 */
155 struct spira_ntuple ipmi_sensor; /* 0x240 */
156 struct spira_ntuple node_stb_data; /* 0x260 */
157 };
158
159 struct spiras {
160 struct HDIF_common_hdr hdr;
161 struct HDIF_idata_ptr ntuples_ptr;
162 __be64 pad;
163 struct spiras_ntuples ntuples;
164 u8 reserved[0x180];
165 } __packed __align(0x100);
166
167 extern struct spiras *spiras;
168
169
170 /* This macro can be used to check the validity of a pointer returned
171 * by one of the HDIF API functions. It returns true if the pointer
172 * appears valid. If it's not valid and not NULL, it will print some
173 * error in the log as well.
174 */
175 #define CHECK_SPPTR(_ptr) spira_check_ptr(_ptr, __FILE__, __LINE__)
176
177 #define get_hdif(ntuple, id) __get_hdif((ntuple), (id), __FILE__, __LINE__)
178
179 extern struct HDIF_common_hdr *__get_hdif(struct spira_ntuple *n,
180 const char id[],
181 const char *file, int line);
182
183 #define for_each_ntuple_idx(_ntuples, _p, _idx, _id) \
184 for (_p = get_hdif((_ntuples), _id ""), _idx = 0; \
185 _p && _idx < be16_to_cpu((_ntuples)->act_cnt); \
186 _p = (void *)_p + be32_to_cpu((_ntuples)->alloc_len), _idx++)
187
188 #define for_each_ntuple(_ntuples, _p, _id) \
189 for (_p = get_hdif((_ntuples), _id ""); \
190 _p && (void *)_p < ntuple_addr(_ntuples) \
191 + (be16_to_cpu((_ntuples)->act_cnt) * \
192 be32_to_cpu((_ntuples)->alloc_len)); \
193 _p = (void *)_p + be32_to_cpu((_ntuples)->alloc_len))
194
195 #define for_each_paca(p) for_each_ntuple(&spira.ntuples.paca, p, PACA_HDIF_SIG)
196
197 #define for_each_pcia(p) for_each_ntuple(&spira.ntuples.pcia, p, SPPCIA_HDIF_SIG)
198
199
200 /* We override these for testing. */
201 #ifndef ntuple_addr
202 #define ntuple_addr(_ntuples) ((void *)BE64_TO_CPU((_ntuples)->addr))
203 #endif
204
205 #ifndef spira_check_ptr
206 extern bool spira_check_ptr(const void *ptr, const char *file,
207 unsigned int line);
208 #endif
209
210 struct proc_init_data {
211 struct HDIF_common_hdr hdr;
212 struct HDIF_idata_ptr regs_ptr;
213 struct {
214 __be64 nia;
215 __be64 msr;
216 __be64 nia_charm_time;
217 __be64 msr_charm_time;
218 } regs;
219 } __packed __align(0x10);
220
221 /*
222 * The FRU ID structure is used in several tuples, so we
223 * define it generically here
224 */
225 struct spira_fru_id {
226 __be16 slca_index;
227 __be16 rsrc_id; /* formerly VPD port number */
228 } __packed;
229
230 /*
231 * The FRU operational status structure is used in several
232 * tuples, so we define it generically here
233 */
234 struct spira_fru_op_status {
235 uint8_t flags;
236 #define FRU_OP_STATUS_FLAG_USED 0x02 /* If 0 -> not used (redundant) */
237 #define FRU_OP_STATUS_FLAG_FUNCTIONAL 0x01 /* If 0 -> non-functional */
238 uint8_t reserved[3];
239 } __packed;
240
241 /*
242 * Move VPD related stuff to another file ...
243 */
244 #define VPD_ID(_a, _b) ((_a) << 8 | (_b))
245
246 /*
247 * Service Processor Subsystem Structure
248 *
249 * This structure contains several internal data blocks
250 * describing the service processor(s) in the system
251 */
252
253 #define SPSS_HDIF_SIG "SPINFO"
254
255 /* Idata index 0 : FRU ID Data */
256 #define SPSS_IDATA_FRU_ID 0
257
258 /* Idata index 1 : Keyword VPD for the FSP instance */
259 #define SPSS_IDATA_KEYWORD_VPD 1
260
261 /* Idata index 2 : SP Implementation */
262 #define SPSS_IDATA_SP_IMPL 2
263
264 struct spss_sp_impl {
265 __be16 hw_version;
266 __be16 sw_version;
267 __be16 func_flags;
268 #define SPSS_SP_IMPL_FLAGS_INSTALLED 0x8000
269 #define SPSS_SP_IMPL_FLAGS_FUNCTIONAL 0x4000
270 #define SPSS_SP_IMPL_FLAGS_PRIMARY 0x2000
271 u8 chip_version;
272 u8 reserved;
273 u8 sp_family[64];
274 } __packed;
275
276 /* Idata index 3 is deprecated */
277
278 /* Idata index 4 : SP Memory Locator */
279 #define SPSS_IDATA_SP_MEMLOC 4
280
281 /* Idata index 5 : SP I/O path array */
282 #define SPSS_IDATA_SP_IOPATH 5
283
284 /* An HDIF array of IO path */
285 struct spss_iopath {
286 __be16 iopath_type;
287 #define SPSS_IOPATH_TYPE_IOHUB_PHB 0x0001
288 #define SPSS_IOPATH_TYPE_PSI 0x0002
289 #define SPSS_IOPATH_TYPE_LPC 0x0003
290 union {
291 struct {
292 __be16 iohub_chip_inst;
293 __be16 iohub_chip_port;
294 __be16 phb_id;
295 } __packed iohub_phb;
296
297 struct {
298 __be16 link_status;
299 #define SPSS_IO_PATH_PSI_LINK_BAD_FRU 0x0000
300 #define SPSS_IO_PATH_PSI_LINK_CURRENT 0x0001
301 #define SPSS_IO_PATH_PSI_LINK_BACKUP 0x0002
302 u8 ml2_version;
303 u8 reserved;
304 __be16 slca_count;
305 u8 slca_idx[16];
306 __be32 proc_chip_id;
307 __be32 reserved2;
308 __be64 gxhb_base;
309 } __packed psi;
310
311 struct { /* only populated after version 0x30 */
312 __be16 link_status;
313 #define LPC_STATUS_STUFFED 0x0000
314 #define LPC_STATUS_ACTIVE 0x0001
315 uint8_t ml2_version;
316 uint8_t reserved[3];
317 __be32 chip_id;
318
319 __be32 io_bar;
320 __be32 memory_bar;
321 __be32 firmware_bar;
322 __be32 internal_bar;
323
324 __be32 reserved2;
325
326 __be64 uart_base;
327 __be32 uart_size;
328 __be32 uart_clk; /* UART baud clock in Hz */
329 __be32 uart_baud; /* UART baud rate */
330
331 uint8_t uart_int_number;
332 uint8_t uart_int_type;
333 #define UART_INT_LVL_LOW 0x1
334 #define UART_INT_RISING 0x2
335 #define UART_INT_LVL_HIGH 0x3
336 uint8_t reserved3[2];
337
338 __be64 bt_base;
339 __be32 bt_size;
340 uint8_t bt_sms_int_num;
341 uint8_t bt_bmc_response_int_num;
342 uint8_t reserved4[2];
343 } __packed lpc;
344 };
345 } __packed;
346
347 /*
348 * IPL Parms structure
349 *
350 */
351
352 /* Idata index 0: System Parameters */
353 #define IPLPARAMS_SYSPARAMS 0
354
355 struct iplparams_sysparams {
356 char sys_model[4];
357 char cpu_feature_code[4];
358 __be32 effective_pvr;
359 __be32 system_type;
360 uint8_t num_lpar_oct[8];
361 __be32 abc_bus_speed;
362 __be32 wxyz_bus_speed;
363 __be32 sys_eco_mode;
364 #define SYS_ATTR_MULTIPLE_TPM PPC_BIT32(0)
365 #define SYS_ATTR_RISK_LEVEL PPC_BIT32(3)
366 __be32 sys_attributes;
367 __be32 mem_scrubbing;
368 __be16 cur_spl_value;
369 uint8_t pump_mode; /* Reserved */
370 uint8_t use_pore_sleep;
371 __be32 pore_image_size; /* Reserved */
372 uint8_t vtpm_enabled;
373 uint8_t hw_page_table_size; /* >= 0x59 */
374 __be16 hv_disp_wheel; /* >= 0x58 */
375 __be32 nest_freq_mhz; /* >= 0x5b */
376 uint8_t split_core_mode; /* >= 0x5c */
377 uint8_t reserved[3];
378 uint8_t sys_vendor[64]; /* >= 0x5f */
379 #define SEC_CONTAINER_SIG_CHECKING PPC_BIT16(0)
380 #define SEC_HASHES_EXTENDED_TO_TPM PPC_BIT16(1)
381 __be16 sys_sec_setting; /* >= 0x60 */
382 __be16 tpm_config_bit; /* >= 0x60 */
383 __be16 tpm_drawer; /* >= 0x60 */
384 __be16 hw_key_hash_size; /* >= 0x60 */
385 #define SYSPARAMS_HW_KEY_HASH_MAX 64
386 uint8_t hw_key_hash[SYSPARAMS_HW_KEY_HASH_MAX]; /* >= 0x60 */
387 uint8_t sys_family_str[64]; /* vendor,name */
388 uint8_t sys_type_str[64]; /* vendor,type */
389 } __packed;
390
391 /* Idata index 1: IPL parameters */
392 #define IPLPARAMS_IPLPARAMS 1
393
394 struct iplparams_iplparams {
395 uint8_t reserved;
396 uint8_t hv_ipl_dest;
397 uint8_t ipl_side;
398 #define IPLPARAMS_CEC_FW_IPL_SIDE_TEMP 0x10
399 #define IPLPARAMS_FSP_FW_IPL_SIDE_TEMP 0x01
400 uint8_t ipl_speed;
401 __be16 cec_ipl_attrib;
402 uint8_t cec_ipl_maj_type;
403 uint8_t cec_ipl_min_type;
404 uint8_t os_ipl_mode;
405 uint8_t keylock_pos;
406 uint8_t lmb_size;
407 uint8_t deprecated;
408 __be32 max_hsl_opticonnect;
409 __be32 other_attrib;
410 #define IPLPARAMS_OATTR_RST_PCI_BUSNO 0x08000000
411 #define IPLPARAMS_OATTR_CLEAR_NVRAM 0x04000000
412 #define IPLPARAMS_OATRR_LIGHT_PATH 0x00000004
413 __be16 huge_page_count;
414 uint8_t huge_page_size;
415 #define IPLPARAMS_HUGE_PG_SIZE_16G 0
416 uint8_t num_vlan_switches;
417 __be32 reserved2;
418 __be32 enlarge_io; /* >= 0x5a */
419 uint8_t core_config;
420 #define IPLPARAMS_CORE_NORMAL 0x00
421 #define IPLPARAMS_CORE_FUSE 0x01
422 } __packed;
423
424 /* Idata index 4: Platform Dump Descriptor */
425 #define IPLPARAMS_PLATFORM_DUMP 4
426
427 struct iplparams_dump {
428 __be16 flags;
429 uint8_t reserved1;
430 uint8_t policy;
431 #define HYP_DUMP_POLICY_NORMAL 0x00
432 __be32 dump_id;
433 __be64 reserved2;
434 __be64 act_dump_sz;
435 __be32 max_hw_dump_sz;
436 __be32 act_hw_dump_sz;
437 __be32 max_sp_dump_sz;
438 __be32 plid;
439 } __packed;
440
441 /* Idata index 8: serial ports */
442 #define IPLPARMS_IDATA_SERIAL 8
443
444 /* An HDIF array of serial descriptions */
445 struct iplparms_serial {
446 uint8_t loc_code[LOC_CODE_SIZE];
447 __be16 rsrc_id;
448 __be16 flags;
449 #define PLPARMS_SERIAL_FLAGS_CALLHOME 0x8000
450 } __packed;
451
452 /* Idata index 9: FW features */
453 #define IPLPARAMS_FEATURES 9
454 struct iplparams_feature {
455 char name[64];
456 __be64 flags;
457 } __packed;
458
459 /*
460 * Chip TOD structure
461 *
462 * This is an array of 32 entries (I assume per possible chip)
463 */
464
465 /* Idata index 0: Chip ID data (array) */
466 #define CHIPTOD_IDATA_CHIPID 0
467
468 struct chiptod_chipid {
469 __be32 chip_id;
470 __be32 flags;
471 #define CHIPTOD_ID_FLAGS_PRIMARY 0x02
472 #define CHIPTOD_ID_FLAGS_SECONDARY 0x01
473 #define CHIPTOD_ID_FLAGS_STATUS_MASK 0x0c
474 #define CHIPTOD_ID_FLAGS_STATUS_OK 0x04
475 #define CHIPTOD_ID_FLAGS_STATUS_NOK 0x08
476 } __packed;
477
478 /* Idata index 0: Chip Initialization data */
479 #define CHIPTOD_IDATA_CHIPINIT 1
480
481 struct chiptod_chipinit {
482 __be32 ctrl_reg_internal;
483 __be32 tod_ctrl_reg;
484 } __packed;
485
486 /*
487 * MS VPD - Memory Description Tree
488 *
489 * One such structure pointing to the various memory arrays
490 * along with other infos about the BCRs, Page Mover, XSCOM,...
491 */
492 #define MSVPD_HDIF_SIG "MS VPD"
493
494 /* Idata index 0: Mainstore address config */
495 #define MSVPD_IDATA_MS_ADDR_CONFIG 0
496
497 /* Mainstore Address Configuration */
498 struct msvpd_ms_addr_config {
499 __be64 max_configured_ms_address;
500 __be64 max_possible_ms_address;
501 __be32 deprecated;
502 __be64 mirrorable_memory_starting_address;
503 } __packed;
504
505 /* Idata index 1: Total configured mainstore */
506 #define MSVPD_IDATA_TOTAL_CONFIG_MS 1
507
508 struct msvpd_total_config_ms {
509 __be64 total_in_mb;
510 } __packed;
511
512 /* Idata index 2: Page mover and sync structure */
513 #define MSVPD_IDATA_PMOVER_SYNCHRO 2
514
515 struct msvpd_pmover_bsr_synchro {
516 __be32 flags;
517 #define MSVPD_PMS_FLAG_HWLOCK_EN 0x80000000
518 #define MSVPD_PMS_FLAG_PMOVER_EN 0x40000000
519 #define MSVPD_PMS_FLAG_BSR_EN 0x20000000
520 #define MSVPD_PMS_FLAG_XSCOMBASE_VALID 0x10000000
521 __be32 hwlocks_per_page;
522 __be64 hwlock_addr;
523 __be64 pmover_addr;
524 __be64 bsr_addr;
525 __be64 xscom_addr;
526 } __packed;
527
528 /* Idata index 3: Memory Trace Array */
529 #define MSVPD_IDATA_TRACE_AREAS 3
530 struct msvpd_trace {
531 __be64 start, end;
532 char reserved[16];
533 };
534
535 /* Idata index 4: UE Address Array */
536
537 /* Idata index 5: Hostboot reserved memory address range */
538 #define MSVPD_IDATA_HB_RESERVED_MEM 5
539 #define HB_RESERVE_MEM_LABEL_SIZE 64
540 struct msvpd_hb_reserved_mem {
541 #define MSVPD_HBRMEM_RANGE_TYPE PPC_BITMASK32(0,7)
542 #define HBRMEM_CONTAINER_VERIFICATION_CODE 0x3
543 __be32 type_instance;
544 __be64 start_addr;
545 __be64 end_addr;
546 __be32 label_size;
547 uint8_t label[HB_RESERVE_MEM_LABEL_SIZE];
548 uint8_t rw_perms;
549 #define HB_RESERVE_READABLE 0x80
550 #define HB_RESERVE_WRITEABLE 0x40
551 uint8_t reserved[7];
552 } __packed;
553
554 /* Child index 0: MS area child structure */
555 #define MSVPD_CHILD_MS_AREAS 0
556
557 /*
558 * CEC I/O Hub FRU
559 *
560 * This is an array of CEC Hub FRU HDIF structures
561 *
562 * Each of these has some idata pointers to generic info about the
563 * hub and a possible child pointer for daughter card.
564 *
565 * Actual ports are in the SLCA and need to be cross referenced
566 *
567 * Note that slots meant for the addition of GX+ adapters that
568 * are currently unpopulated but support hotplug will have a
569 * minimum "placeholder" entry, which will be fully populated
570 * when the array is rebuild during concurrent maintenance.
571 * This "placeholder" is called a "reservation".
572 *
573 * WARNING: The array rebuild by concurrent maintenance is not
574 * guaranteed to be in the same order as the IPL array, not is
575 * the order stable between concurrent maintenance operations.
576 *
577 * There's also a child pointer to daughter card structures but
578 * we aren't going to handle that just yet.
579 */
580 #define CECHUB_FRU_HDIF_SIG "IO HUB"
581 #define IOKID_FRU_HDIF_SIG "IO KID"
582 #define IOSLOT_FRU_HDIF_SIG "IOSLOT"
583
584 /* Idata index 0: FRU ID data
585 *
586 * This is a generic struct spira_fru_id defined above
587 */
588 #define CECHUB_FRU_ID_DATA 0
589
590 /* Idata index 1: ASCII Keyword VPD */
591 #define CECHUB_ASCII_KEYWORD_VPD 1
592
593 /* Idata index 2: Hub FRU ID data area */
594 #define CECHUB_FRU_ID_DATA_AREA 2
595
596 struct cechub_hub_fru_id {
597 __be32 card_type;
598 #define CECHUB_FRU_TYPE_IOHUB_RSRV 0
599 #define CECHUB_FRU_TYPE_IOHUB_CARD 1
600 #define CECHUB_FRU_TYPE_CPU_CARD 2
601 #define CECHUB_FRU_TYPE_CEC_BKPLANE 3
602 #define CECHUB_FRU_TYPE_BKPLANE_EXT 4
603 __be32 unused;
604 __be16 total_chips;
605 uint8_t flags;
606 #define CECHUB_FRU_FLAG_HEADLESS 0x80 /* not connected to CPU */
607 #define CECHUB_FRU_FLAG_PASSTHROUGH 0x40 /* connected to passhtrough
608 port of another hub */
609 uint8_t reserved;
610 __be16 parent_hub_id; /* chip instance number of the
611 hub that contains the passthrough
612 port this one is connected to */
613 __be16 reserved2;
614 } __packed;
615
616
617 /* Idata index 3: IO HUB array */
618
619 #define CECHUB_FRU_IO_HUBS 3
620
621 /* This is an HDIF array of IO Hub structures */
622 struct cechub_io_hub {
623 __be64 fmtc_address;
624 __be32 fmtc_tce_size;
625 __be16 hub_num; /* unique hub number (I/O Hub ID) */
626 uint8_t flags;
627 #define CECHUB_HUB_FLAG_STATE_MASK 0xc0
628 #define CECHUB_HUB_FLAG_STATE_OK 0x00
629 #define CECHUB_HUB_FLAG_STATE_FAILURES 0x40
630 #define CECHUB_HUB_FLAG_STATE_NOT_INST 0x80
631 #define CECHUB_HUB_FLAG_STATE_UNUSABLE 0xc0
632 #define CECHUB_HUB_FLAG_MASTER_HUB 0x20 /* HDAT < v9.x only */
633 #define CECHUB_HUB_FLAG_GARD_MASK_VALID 0x08 /* HDAT < v9.x only */
634 #define CECHUB_HUB_FLAG_SWITCH_MASK_PDT 0x04 /* HDAT < v9.x only */
635 #define CECHUB_HUB_FLAG_FAB_BR0_PDT 0x02 /* HDAT < v9.x only */
636 #define CECHUB_HUB_FLAG_FAB_BR1_PDT 0x01 /* HDAT < v9.x only */
637 uint8_t nr_ports; /* HDAT < v9.x only */
638 uint8_t fab_br0_pdt; /* p5ioc2 PCI-X or P8 PHB3's */
639 #define CECHUB_HUB_FAB_BR0_PDT_PHB0 0x80
640 #define CECHUB_HUB_FAB_BR0_PDT_PHB1 0x40
641 #define CECHUB_HUB_FAB_BR0_PDT_PHB2 0x20
642 #define CECHUB_HUB_FAB_BR0_PDT_PHB3 0x10
643 #define CECHUB_HUB_FAB_BR0_PDT_PHB4 0x08
644 #define CECHUB_HUB_FAB_BR0_PDT_PHB5 0x04
645 uint8_t fab_br1_pdt; /* p5ioc2 & p7ioc PCI-E */
646 #define CECHUB_HUB_FAB_BR1_PDT_PHB0 0x80
647 #define CECHUB_HUB_FAB_BR1_PDT_PHB1 0x40
648 #define CECHUB_HUB_FAB_BR1_PDT_PHB2 0x20
649 #define CECHUB_HUB_FAB_BR1_PDT_PHB3 0x10
650 #define CECHUB_HUB_FAB_BR1_PDT_PHB4 0x08 /* p7ioc only */
651 #define CECHUB_HUB_FAB_BR1_PDT_PHB5 0x04 /* p7ioc only */
652 __be16 iohub_id; /* the type of hub */
653 #define CECHUB_HUB_MURANO 0x20ef /* Murano from spec */
654 #define CECHUB_HUB_MURANO_SEGU 0x0001 /* Murano+Seguso from spec */
655 #define CECHUB_HUB_VENICE_WYATT 0x0010 /* Venice+Wyatt from spec */
656 #define CECHUB_HUB_NIMBUS_SFORAZ 0x0020 /* Nimbus+sforaz from spec */
657 #define CECHUB_HUB_NIMBUS_MONZA 0x0021 /* Nimbus+monza from spec */
658 #define CECHUB_HUB_NIMBUS_LAGRANGE 0x0022 /* Nimbus+lagrange from spec */
659 #define CECHUB_HUB_CUMULUS_DUOMO 0x0030 /* cumulus+duomo from spec */
660 __be32 ec_level;
661 __be32 aff_dom2; /* HDAT < v9.x only */
662 __be32 aff_dom3; /* HDAT < v9.x only */
663 __be64 reserved;
664 __be32 proc_chip_id;
665
666 union {
667 /* HDAT < v9.x */
668 struct {
669 __be32 gx_index; /* GX bus index on cpu */
670 __be32 buid_ext; /* BUID Extension */
671 __be32 xscom_chip_id; /* TORRENT ONLY */
672 };
673 /* HDAT >= v9.x */
674 struct {
675 __be32 reserved1;
676 __be32 reserved2;
677 __be16 reserved3;
678 __be16 hw_topology;
679 };
680 };
681 __be32 mrid;
682 __be32 mem_map_vers;
683 union {
684 /* HDAT < v9.x */
685 struct {
686 __be64 gx_ctrl_bar0;
687 __be64 gx_ctrl_bar1;
688 __be64 gx_ctrl_bar2;
689 __be64 gx_ctrl_bar3;
690 __be64 gx_ctrl_bar4;
691 __be32 sw_mask_pdt;
692 __be16 gard_mask;
693 __be16 gx_bus_speed; /* Version 0x58 */
694 };
695
696 /* HDAT >= v9.x, HDIF version 0x6A adds phb_lane_eq with four
697 * words per PHB (4 PHBs).
698 *
699 * HDAT >= 10.x, HDIF version 0x7A adds space for another two
700 * two PHBs (6 total) and the gen4 EQ values.
701 */
702 struct {
703 /* Gen 3 PHB eq values, 6 PHBs */
704 __be64 phb_lane_eq[6][4];
705
706 /* Gen 4 PHB eq values */
707 __be64 phb4_lane_eq[6][4];
708 };
709 };
710 } __packed;
711
712 /* We support structures as small as 0x68 bytes */
713 #define CECHUB_IOHUB_MIN_SIZE 0x68
714
715 /* Child index 0: IO Daugther Card */
716 #define CECHUB_CHILD_IO_KIDS 0
717
718 /* Child index 1: PCIe Slot Mapping Information */
719 #define CECHUB_CHILD_IOSLOTS 1
720
721 #define IOSLOT_IDATA_SLOTMAP 0
722
723 struct slot_map_entry {
724 __be16 entry_id;
725 __be16 parent_id;
726 uint8_t phb_index; /* only valid for ROOT and SWITCH_UP */
727
728 uint8_t type;
729 #define SLOT_TYPE_ROOT_COMPLEX 0x0
730 #define SLOT_TYPE_SWITCH_UP 0x1
731 #define SLOT_TYPE_SWITCH_DOWN 0x2
732 #define SLOT_TYPE_BUILTIN 0x3
733
734 uint8_t lane_swapped;
735 uint8_t reserved;
736 __be16 lane_mask;
737 __be16 lane_reverse;
738
739 /* what can I do with this? reference something under/vpd/ ? */
740 __be16 slca_idx;
741
742 __be16 mrw_slot_id;
743
744 __be32 features;
745 #define SLOT_FEAT_SLOT 0x1
746
747 uint8_t up_port;
748 uint8_t down_port; /* the switch port this device is attached to */
749
750 __be32 vendor_id;
751 __be32 device_id;
752 __be32 sub_vendor_id;
753 __be32 sub_device_id;
754 char name[8];
755 } __packed;
756
757 #define IOSLOT_IDATA_DETAILS 1
758
759 struct slot_map_details {
760 __be16 entry;
761
762 /* Phyp junk, ignore */
763 uint8_t mgc_load_source;
764 uint8_t hddw_order;
765 __be16 mmio_size_32; /* In MB */
766 __be16 mmio_size_64;
767 __be16 dma_size_32;
768 __be16 dma_size_64;
769
770 uint8_t power_ctrl_type; /* slot power control source */
771 #define SLOT_PWR_NONE 0x0
772 #define SLOT_PWR_I2C 0x1
773
774 uint8_t presence_det_type; /* slot presence detect source */
775 #define SLOT_PRESENCE_NONE 0x0
776 #define SLOT_PRESENCE_PCI 0x1
777 #define SLOT_PRESENCE_I2C 0x2
778
779 uint8_t perst_ctl_type; /* slot PERST source */
780 #define SLOT_PERST_NONE 0x0
781 #define SLOT_PERST_PHB_OR_SW 0x1
782 #define SLOT_PERST_SW_GPIO 0x2
783 uint8_t perst_gpio;
784
785 __be16 max_power; /* in W? */
786
787 __be32 slot_caps;
788 #define SLOT_CAP_LSI 0x01 /* phyp junk? */
789 #define SLOT_CAP_CAPI 0x02
790 #define SLOT_CAP_CCARD 0x04
791 #define SLOT_CAP_HOTPLUG 0x08
792 #define SLOT_CAP_SRIOV 0x10 /* phyp junk */
793 #define SLOT_CAP_ELLOCO 0x20 /* why is this seperate from the nvlink cap? */
794 #define SLOT_CAP_NVLINK 0x30
795
796 __be16 reserved1;
797
798 /* I2C Link IDs */
799 __be32 i2c_power_ctl;
800 __be32 i2c_pgood;
801 __be32 i2c_cable_card; /* opencapi presence detect? */
802 __be32 i2c_mex_fpga;
803 };
804
805 /*
806 * IO KID is a dauther card structure
807 */
808 #define IOKID_FRU_ID_DATA 0
809 #define IOKID_KW_VPD 1
810
811 /*
812 * CPU Controls Legacy Structure
813 */
814 struct cpu_ctl_legacy {
815 __be64 addr;
816 __be64 size;
817 } __packed;
818
819 /*
820 * CPU Control Legacy table
821 *
822 * Format of this table is defined in FIPS PHYP Attn spec.
823 */
824 struct cpu_ctl_legacy_table {
825 struct cpu_ctl_legacy spat;
826 struct cpu_ctl_legacy sp_attn_area1;
827 struct cpu_ctl_legacy sp_attn_area2;
828 struct cpu_ctl_legacy hsr_area;
829 struct cpu_ctl_legacy reserved[12];
830 } __packed;
831
832 /*
833 * CPU Controls Header Structure
834 */
835 #define CPU_CTL_HDIF_SIG "CPUCTL"
836 struct cpu_ctl_init_data {
837 struct HDIF_common_hdr hdr;
838 struct HDIF_idata_ptr cpu_ctl;
839 uint8_t reserved[8];
840 struct cpu_ctl_legacy_table cpu_ctl_lt;
841 } __packed __align(0x10);
842
843 /*
844 * Slot Location Code Array (aka SLCA)
845 *
846 * This is a pile of location codes referenced by various other
847 * structures such as the IO Hubs for things on the CEC. Not
848 * everything in there is a physical port. The SLCA is actually
849 * a tree which represent the topology of the system.
850 *
851 * The tree works as follow: A parent has a pointer to the first
852 * child. A child has a pointer to its parent. Siblings are
853 * consecutive entries.
854 *
855 * Note: If we ever support concurrent maintenance... this is
856 * completely rebuilt, invalidating all indices, though other
857 * structures that may reference SLCA by index will be rebuilt
858 * as well.
859 *
860 * Note that a lot of that stuff is based on VPD documentation
861 * such as the identification keywords. I will list the ones
862 * I manage to figure out without the doc separately.
863 */
864 #define SLCA_HDIF_SIG "SLCA "
865
866 /* Idata index 0 : SLCA root pointer
867 *
868 * The SLCA array is an HDIF array of all the entries. The tree
869 * structure is based on indices inside the entries and order of
870 * the entries
871 */
872 #define SLCA_IDATA_ARRAY 0
873
874 #define SLCA_ROOT_INDEX 0
875
876 /* Note: An "index" (or idx) is always an index into the SLCA array
877 * and "id" is a reference to some other object.
878 */
879 struct slca_entry {
880 __be16 my_index; /* redundant, useful */
881 __be16 rsrc_id; /* formerly VPD port number */
882 uint8_t fru_id[2]; /* ASCII VPD ID */
883 #define SLCA_ROOT_VPD_ID VPD_ID('V','V')
884 #define SLCA_SYSTEM_VPD_ID VPD_ID('S','V')
885 #define SLCA_SAI_INDICATOR_ID VPD_ID('S','A')
886 __be16 parent_index; /* Parent entry index */
887 uint8_t flags;
888 #define SLCA_FLAG_NON_FUNCTIONAL 0x02 /* For redundant entries */
889 #define SLCA_FLAG_IMBEDDED 0x01 /* not set => pluggable */
890 uint8_t old_nr_child; /* Legacy: Nr of children */
891 __be16 child_index; /* First child index */
892 __be16 child_rsrc_id; /* Resource ID of first child */
893 uint8_t loc_code_allen; /* Alloc len of loc code */
894 uint8_t loc_code_len; /* Loc code len */
895 uint8_t loc_code[LOC_CODE_SIZE]; /* NULL terminated (thus max 79 chr) */
896 __be16 first_dup_idx; /* First redundant resource index */
897 uint8_t nr_dups; /* Number of redundant entries */
898 uint8_t reserved;
899 __be16 nr_child; /* New version */
900 uint8_t install_indic; /* Installed indicator */
901 #define SLCA_INSTALL_NO_HW_PDT 1 /* No HW presence detect */
902 #define SLCA_INSTALL_INSTALLED 2
903 #define SLCA_INSTALL_NOT_INSTALLED 3
904 uint8_t vpd_collected;
905 #define SLCA_VPD_COLLECTED 2
906 #define SLCA_VPD_NOT_COLLECTED 3
907 } __packed;
908
909 /*
910 * System VPD
911 */
912 #define SYSVPD_HDIF_SIG "SYSVPD"
913
914 /* Idata index 0 : FRU ID Data */
915 #define SYSVPD_IDATA_FRU_ID 0
916
917 /* Idata index 1 : Keyword VPD */
918 #define SYSVPD_IDATA_KW_VPD 1
919
920 /* Idata index 2 : Operational status */
921 #define SYSVPD_IDATA_OP_STATUS 2
922
923 /*
924 * FRU keyword VPD structure
925 */
926 #define FRUVPD_HDIF_SIG "FRUVPD"
927
928 /* Idata index 0 : FRU ID Data */
929 #define FRUVPD_IDATA_FRU_ID 0
930
931 /* Idata index 1 : Keyword VPD */
932 #define FRUVPD_IDATA_KW_VPD 1
933
934 /* Idata index 2 : Operational status */
935 #define FRUVPD_IDATA_OP_STATUS 2
936
937
938 /*
939 * SPPACA structure. The SPIRA contain an array of these, one
940 * per processor thread
941 */
942 #define PACA_HDIF_SIG "SPPACA"
943
944 /* Idata index 0 : FRU ID Data */
945 #define SPPACA_IDATA_FRU_ID 0
946
947 /* Idata index 1 : Keyword VPD */
948 #define SPPACA_IDATA_KW_VPD 1
949
950 /* Idata index 2 : CPU ID data area */
951 #define SPPACA_IDATA_CPU_ID 2
952
953 struct sppaca_cpu_id {
954 __be32 pir;
955 __be32 fru_id;
956 __be32 hardware_proc_id;
957 #define CPU_ID_VERIFY_MASK 0xC0000000
958 #define CPU_ID_VERIFY_SHIFT 30
959 #define CPU_ID_VERIFY_USABLE_NO_FAILURES 0
960 #define CPU_ID_VERIFY_USABLE_FAILURES 1
961 #define CPU_ID_VERIFY_NOT_INSTALLED 2
962 #define CPU_ID_VERIFY_UNUSABLE 3
963 #define CPU_ID_SECONDARY_THREAD 0x20000000
964 #define CPU_ID_PACA_RESERVED 0x10000000
965 #define CPU_ID_NUM_SECONDARY_THREAD_MASK 0x00FF0000
966 #define CPU_ID_NUM_SECONDARY_THREAD_SHIFT 16
967 __be32 verify_exists_flags;
968 __be32 chip_ec_level;
969 __be32 processor_chip_id;
970 __be32 logical_processor_id;
971 /* This is the resource number, too. */
972 __be32 process_interrupt_line;
973 __be32 reserved1;
974 __be32 hardware_module_id;
975 __be64 ibase;
976 __be32 deprecated1;
977 __be32 physical_thread_id;
978 __be32 deprecated2;
979 __be32 ccm_node_id;
980 /* This fields are not always present, check struct size */
981 #define SPIRA_CPU_ID_MIN_SIZE 0x40
982 __be32 hw_card_id;
983 __be32 internal_drawer_node_id;
984 __be32 drawer_book_octant_blade_id;
985 __be32 memory_interleaving_scope;
986 __be32 lco_target;
987 } __packed;
988
989 /* Idata index 3 : Timebase data */
990 #define SPPACA_IDATA_TIMEBASE 3
991
992 struct sppaca_cpu_timebase {
993 __be32 cycle_time;
994 __be32 time_base;
995 __be32 actual_clock_speed;
996 __be32 memory_bus_frequency;
997 } __packed;
998
999 /* Idata index 4 : Cache size structure */
1000 #define SPPACA_IDATA_CACHE_SIZE 4
1001
1002 struct sppaca_cpu_cache {
1003 __be32 icache_size_kb;
1004 __be32 icache_line_size;
1005 __be32 l1_dcache_size_kb;
1006 __be32 l1_dcache_line_size;
1007 __be32 l2_dcache_size_kb;
1008 __be32 l2_line_size;
1009 __be32 l3_dcache_size_kb;
1010 __be32 l3_line_size;
1011 __be32 dcache_block_size;
1012 __be32 icache_block_size;
1013 __be32 dcache_assoc_sets;
1014 __be32 icache_assoc_sets;
1015 __be32 dtlb_entries;
1016 __be32 dtlb_assoc_sets;
1017 __be32 itlb_entries;
1018 __be32 itlb_assoc_sets;
1019 __be32 reservation_size;
1020 __be32 l2_cache_assoc_sets;
1021 __be32 l35_dcache_size_kb;
1022 __be32 l35_cache_line_size;
1023 } __packed;
1024
1025 /* Idata index 6 : CPU Attributes */
1026 #define SPPACA_IDATA_CPU_ATTR 6
1027
1028 #define sppaca_cpu_attr sppcia_cpu_attr
1029
1030 /*
1031 * SPPCIA structure. The SPIRA contain an array of these, one
1032 * per processor core
1033 */
1034 #define SPPCIA_HDIF_SIG "SPPCIA"
1035
1036 /* Idata index 0 : Core unique data */
1037 #define SPPCIA_IDATA_CORE_UNIQUE 0
1038
1039 /* NOTE: This is the same layout as "struct sppaca_cpu_id",
1040 * with essentially some fields removed and a reserved
1041 * field added
1042 */
1043 struct sppcia_core_unique {
1044 __be32 reserved;
1045 __be32 proc_fru_id;
1046 __be32 hw_proc_id;
1047 __be32 verif_exist_flags; /* Same as PACA */
1048 __be32 chip_ec_level;
1049 __be32 proc_chip_id;
1050 __be32 reserved2;
1051 __be32 reserved3;
1052 __be32 reserved4;
1053 __be32 hw_module_id;
1054 __be64 reserved5;
1055 __be32 reserved6;
1056 __be32 reserved7;
1057 __be32 reserved8;
1058 __be32 ccm_node_id;
1059 __be32 hw_card_id;
1060 __be32 internal_drawer_node_id;
1061 __be32 drawer_book_octant_blade_id;
1062 __be32 memory_interleaving_scope;
1063 __be32 lco_target;
1064 __be32 reserved9;
1065 } __packed;
1066
1067 /* Idata index 1 : CPU Time base structure */
1068 #define SPPCIA_IDATA_TIMEBASE 1
1069
1070 #define sppcia_cpu_timebase sppaca_cpu_timebase
1071
1072 /* Idata index 2 : CPU Cache Size Structure */
1073 #define SPPCIA_IDATA_CPU_CACHE 2
1074
1075 #define sppcia_cpu_cache sppaca_cpu_cache
1076
1077 /* Idata index 3 : Thread Array Data
1078 *
1079 * HDIF array of
1080 */
1081 #define SPPCIA_IDATA_THREAD_ARRAY 3
1082
1083 struct sppcia_cpu_thread {
1084 __be32 proc_int_line;
1085 __be32 phys_thread_id;
1086 __be64 ibase;
1087 __be32 pir;
1088 } __packed;
1089
1090 /* Idata index 4 : CPU Attributes */
1091 #define SPPCIA_IDATA_CPU_ATTR 4
1092
1093 struct sppcia_cpu_attr {
1094 #define CPU_ATTR_UNIFIED_PL1 0x80
1095 #define CPU_ATTR_SPLIT_TLB 0x40
1096 #define CPU_ATTR_TLBIA 0x20
1097 #define CPU_ATTR_PERF_MONITOR 0x10
1098 #define CPU_ATTR_EXTERN_CONT 0x02
1099 __be32 attr;
1100 } __packed;
1101
1102 /*
1103 * Processor Chip Related Data. The SPIRA contain an array of these, one
1104 * per chip
1105 */
1106 #define SPPCRD_HDIF_SIG "SPPCRD"
1107
1108 /* Idata index 0 : Chip info */
1109 #define SPPCRD_IDATA_CHIP_INFO 0
1110
1111 struct sppcrd_chip_info {
1112 __be32 proc_chip_id;
1113 __be32 verif_exist_flags;
1114 #define CHIP_VERIFY_MASK 0xC0000000
1115 #define CHIP_VERIFY_SHIFT 30
1116 #define CHIP_VERIFY_USABLE_NO_FAILURES 0
1117 #define CHIP_VERIFY_USABLE_FAILURES 1
1118 #define CHIP_VERIFY_NOT_INSTALLED 2
1119 #define CHIP_VERIFY_UNUSABLE 3
1120 #define CHIP_VERIFY_MASTER_PROC PPC_BIT32(4)
1121 __be32 nx_state;
1122 __be32 pore_state;
1123 __be32 xscom_id;
1124 /* Version 0xA */
1125 __be32 reserved;
1126 __be32 dbob_id;
1127 __be32 occ_state;
1128 /* Version 0xC - none of these are used */
1129 __be32 processor_fru_id;
1130 __be32 chip_ec_level;
1131 __be32 hw_module_id;
1132 __be32 hw_card_id;
1133 __be32 internal_drawer_nid;
1134 __be32 ccm_nid;
1135 /* Version 0xD */
1136 __be32 capp0_func_state;
1137 /* Version 0xE */
1138 __be32 capp1_func_state;
1139 /* *possibly* from Version 0x20 - check spec */
1140 __be32 stop_levels;
1141 /* From latest version (possibly 0x21 and later) */
1142 __be32 sw_xstop_fir_scom;
1143 uint8_t sw_xstop_fir_bitpos;
1144 uint8_t reserved_1[3];
1145 } __packed;
1146
1147 /* Idata index 1 : Chip TOD */
1148 #define SPPCRD_IDATA_CHIP_TOD 1
1149
1150 struct sppcrd_chip_tod {
1151 __be32 flags;
1152 /* CHIPTOD_ID_... values */
1153 __be32 ctrl_reg_internal;
1154 __be32 tod_ctrl_reg;
1155 } __packed;
1156
1157 /* Idata index 2 : FRU ID */
1158 #define SPPCRD_IDATA_FRU_ID 2
1159
1160 /* Idata index 3 : ASCII Keyword data */
1161 #define SPPCRD_IDATA_KW_VPD 3
1162
1163 /* Idata index 4 : Module VPD */
1164 #define SPPCRD_IDATA_MODULE_VPD 4
1165
1166 /* Idata index 5 : Chip attached I2C devices */
1167 #define SPPCRD_IDATA_HOST_I2C 5
1168
1169 /* Idata index 5 : Chip attached I2C devices */
1170 #define SPPCRD_IDATA_PNOR 6
1171
1172 /* Idata index 6 : OpenCAPI/NVlink info */
1173 #define SPPCRD_IDATA_SMP_LINK 7
1174 struct sppcrd_smp_link {
1175 __be32 link_id;
1176 __be32 usage;
1177 #define SMP_LINK_USE_NONE 0
1178 #define SMP_LINK_USE_GPU 1
1179 #define SMP_LINK_USE_OPENCAPI 2
1180 #define SMP_LINK_USE_INTERPOSER 3
1181 #define SMP_LINK_USE_DRAWER 4
1182 #define SMP_LINK_USE_D2D 5 /* GPU to GPU */
1183 __be32 brick_id;
1184 __be32 lane_mask;
1185
1186 /* bonded pci slots (mostly a NVLink thing) */
1187 __be16 pci_slot_idx;
1188 __be16 pci_sideband_slot_idx;
1189
1190 __be16 slca_idx; /* SLCA index of the *external* port */
1191 __be16 reserved;
1192
1193 /* nvlink/ocapi detection devices */
1194 __be32 i2c_link_cable;
1195 __be32 i2c_presence;
1196 __be32 i2c_micro;
1197 uint8_t link_speed;
1198 uint8_t occ_flag_bit;
1199 __be16 gpu_slca;
1200 } __packed;
1201
1202 /* Idata index 8 : chip EC Level array */
1203 #define SPPCRD_IDATA_EC_LEVEL 8
1204
1205 struct sppcrd_ecid {
1206 __be32 chip_id;
1207 __be32 ec_level;
1208 __be64 low; /* Processor ECID bit 0-63 */
1209 __be64 high; /* Processor ECID bit 64-127 */
1210 } __packed;
1211
1212 /*
1213 * Host Services Data.
1214 */
1215 #define HSERV_HDIF_SIG "HOSTSR"
1216
1217 /* Idata index 0 : System attribute data */
1218 #define HSERV_IDATA_SYS_ATTR 0
1219
1220 /* IPMI sensors mapping data */
1221 #define IPMI_SENSORS_HDIF_SIG "FRUSE "
1222
1223 /* Idata index 0 : Sensor mapping data */
1224 #define IPMI_SENSORS_IDATA_SENSORS 0
1225
1226 struct ipmi_sensors_data {
1227 __be32 slca_index;
1228 uint8_t type;
1229 uint8_t id;
1230 __be16 reserved;
1231 } __packed;
1232
1233 struct ipmi_sensors {
1234 __be32 count;
1235 struct ipmi_sensors_data data[];
1236 } __packed;
1237
1238 /* Idata index 1 : LED - sensors ID mapping data */
1239 #define IPMI_SENSORS_IDATA_LED 1
1240
1241 /*
1242 * Node Secure and Trusted Boot Related Data
1243 */
1244 #define STB_HDIF_SIG "TPMREL"
1245
1246 /*
1247 * Idata index 0 : Secure Boot and TPM Instance Info
1248 *
1249 * There can be multiple entries with each entry corresponding to
1250 * a master processor that has a TPM device
1251 */
1252 #define TPMREL_IDATA_SECUREBOOT_TPM_INFO 0
1253
1254 struct secureboot_tpm_info {
1255 __be32 chip_id;
1256 __be32 dbob_id;
1257 uint8_t locality1;
1258 uint8_t locality2;
1259 uint8_t locality3;
1260 uint8_t locality4;
1261 #define TPM_PRESENT_AND_FUNCTIONAL 0x01
1262 #define TPM_PRESENT_AND_NOT_FUNCTIONAL 0x02
1263 #define TPM_NOT_PRESENT 0x03
1264 uint8_t tpm_status;
1265 uint8_t reserved[3];
1266 /* zero indicates no tpm log data */
1267 __be32 srtm_log_offset;
1268 __be32 srtm_log_size;
1269 /* zero indicates no tpm log data */
1270 __be32 drtm_log_offset;
1271 __be32 drtm_log_size;
1272 } __packed;
1273
1274 /* Idata index 2: Hash and Verification Function Offsets Array */
1275 #define TPMREL_IDATA_HASH_VERIF_OFFSETS 2
1276
1277 struct hash_and_verification {
1278 #define TPMREL_HV_SHA512 0x00
1279 #define TPMREL_HV_VERIFY 0x01
1280 __be32 type;
1281 __be32 version;
1282 __be32 dbob_id;
1283 __be32 offset;
1284 } __packed;
1285
cpu_state(u32 flags)1286 static inline const char *cpu_state(u32 flags)
1287 {
1288 switch ((flags & CPU_ID_VERIFY_MASK) >> CPU_ID_VERIFY_SHIFT) {
1289 case CPU_ID_VERIFY_USABLE_NO_FAILURES:
1290 return "OK";
1291 case CPU_ID_VERIFY_USABLE_FAILURES:
1292 return "FAILURES";
1293 case CPU_ID_VERIFY_NOT_INSTALLED:
1294 return "NOT-INSTALLED";
1295 case CPU_ID_VERIFY_UNUSABLE:
1296 return "UNUSABLE";
1297 }
1298 return "**UNKNOWN**";
1299 }
1300 #endif /* __SPIRA_H */
1301