1 /* Copyright 2013-2019 IBM Corp. 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 12 * implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __OPAL_API_H 18 #define __OPAL_API_H 19 20 /****** OPAL APIs ******/ 21 22 /* Return codes */ 23 #define OPAL_SUCCESS 0 24 #define OPAL_PARAMETER -1 25 #define OPAL_BUSY -2 26 #define OPAL_PARTIAL -3 27 #define OPAL_CONSTRAINED -4 28 #define OPAL_CLOSED -5 29 #define OPAL_HARDWARE -6 30 #define OPAL_UNSUPPORTED -7 31 #define OPAL_PERMISSION -8 32 #define OPAL_NO_MEM -9 33 #define OPAL_RESOURCE -10 34 #define OPAL_INTERNAL_ERROR -11 35 #define OPAL_BUSY_EVENT -12 36 #define OPAL_HARDWARE_FROZEN -13 37 #define OPAL_WRONG_STATE -14 38 #define OPAL_ASYNC_COMPLETION -15 39 #define OPAL_EMPTY -16 40 #define OPAL_I2C_TIMEOUT -17 41 #define OPAL_I2C_INVALID_CMD -18 42 #define OPAL_I2C_LBUS_PARITY -19 43 #define OPAL_I2C_BKEND_OVERRUN -20 44 #define OPAL_I2C_BKEND_ACCESS -21 45 #define OPAL_I2C_ARBT_LOST -22 46 #define OPAL_I2C_NACK_RCVD -23 47 #define OPAL_I2C_STOP_ERR -24 48 #define OPAL_XSCOM_BUSY OPAL_BUSY 49 #define OPAL_XSCOM_CHIPLET_OFF OPAL_WRONG_STATE 50 #define OPAL_XSCOM_PARTIAL_GOOD -25 51 #define OPAL_XSCOM_ADDR_ERROR -26 52 #define OPAL_XSCOM_CLOCK_ERROR -27 53 #define OPAL_XSCOM_PARITY_ERROR -28 54 #define OPAL_XSCOM_TIMEOUT -29 55 #define OPAL_XSCOM_CTR_OFFLINED -30 56 #define OPAL_XIVE_PROVISIONING -31 57 #define OPAL_XIVE_FREE_ACTIVE -32 58 #define OPAL_TIMEOUT -33 59 60 /* API Tokens (in r0) */ 61 #define OPAL_INVALID_CALL -1 62 #define OPAL_TEST 0 63 #define OPAL_CONSOLE_WRITE 1 64 #define OPAL_CONSOLE_READ 2 65 #define OPAL_RTC_READ 3 66 #define OPAL_RTC_WRITE 4 67 #define OPAL_CEC_POWER_DOWN 5 68 #define OPAL_CEC_REBOOT 6 69 #define OPAL_READ_NVRAM 7 70 #define OPAL_WRITE_NVRAM 8 71 #define OPAL_HANDLE_INTERRUPT 9 72 #define OPAL_POLL_EVENTS 10 73 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11 /* Removed, p5ioc only */ 74 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12 /* Removed, p5ioc only */ 75 #define OPAL_PCI_CONFIG_READ_BYTE 13 76 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14 77 #define OPAL_PCI_CONFIG_READ_WORD 15 78 #define OPAL_PCI_CONFIG_WRITE_BYTE 16 79 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17 80 #define OPAL_PCI_CONFIG_WRITE_WORD 18 81 #define OPAL_SET_XIVE 19 82 #define OPAL_GET_XIVE 20 83 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */ 84 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22 85 #define OPAL_PCI_EEH_FREEZE_STATUS 23 86 #define OPAL_PCI_SHPC 24 87 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25 88 #define OPAL_PCI_EEH_FREEZE_CLEAR 26 89 #define OPAL_PCI_PHB_MMIO_ENABLE 27 90 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28 91 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29 92 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30 /* never implemented */ 93 #define OPAL_PCI_SET_PE 31 94 #define OPAL_PCI_SET_PELTV 32 95 #define OPAL_PCI_SET_MVE 33 96 #define OPAL_PCI_SET_MVE_ENABLE 34 97 #define OPAL_PCI_GET_XIVE_REISSUE 35 /* never implemented */ 98 #define OPAL_PCI_SET_XIVE_REISSUE 36 /* never implemented */ 99 #define OPAL_PCI_SET_XIVE_PE 37 100 #define OPAL_GET_XIVE_SOURCE 38 101 #define OPAL_GET_MSI_32 39 102 #define OPAL_GET_MSI_64 40 103 #define OPAL_START_CPU 41 104 #define OPAL_QUERY_CPU_STATUS 42 105 #define OPAL_WRITE_OPPANEL 43 /* unimplemented */ 106 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44 107 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 108 /* 46 is unused */ 109 /* 47 is unused */ 110 /* 48 is unused */ 111 #define OPAL_PCI_RESET 49 112 #define OPAL_PCI_GET_HUB_DIAG_DATA 50 113 #define OPAL_PCI_GET_PHB_DIAG_DATA 51 114 #define OPAL_PCI_FENCE_PHB 52 115 #define OPAL_PCI_REINIT 53 116 #define OPAL_PCI_MASK_PE_ERROR 54 117 #define OPAL_SET_SLOT_LED_STATUS 55 118 #define OPAL_GET_EPOW_STATUS 56 119 #define OPAL_SET_SYSTEM_ATTENTION_LED 57 120 #define OPAL_RESERVED1 58 121 #define OPAL_RESERVED2 59 122 #define OPAL_PCI_NEXT_ERROR 60 123 #define OPAL_PCI_EEH_FREEZE_STATUS2 61 124 #define OPAL_PCI_POLL 62 125 #define OPAL_PCI_MSI_EOI 63 126 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64 127 #define OPAL_XSCOM_READ 65 128 #define OPAL_XSCOM_WRITE 66 129 #define OPAL_LPC_READ 67 130 #define OPAL_LPC_WRITE 68 131 #define OPAL_RETURN_CPU 69 132 #define OPAL_REINIT_CPUS 70 133 #define OPAL_ELOG_READ 71 134 #define OPAL_ELOG_WRITE 72 135 #define OPAL_ELOG_ACK 73 136 #define OPAL_ELOG_RESEND 74 137 #define OPAL_ELOG_SIZE 75 138 #define OPAL_FLASH_VALIDATE 76 139 #define OPAL_FLASH_MANAGE 77 140 #define OPAL_FLASH_UPDATE 78 141 #define OPAL_RESYNC_TIMEBASE 79 142 #define OPAL_CHECK_TOKEN 80 143 #define OPAL_DUMP_INIT 81 144 #define OPAL_DUMP_INFO 82 145 #define OPAL_DUMP_READ 83 146 #define OPAL_DUMP_ACK 84 147 #define OPAL_GET_MSG 85 148 #define OPAL_CHECK_ASYNC_COMPLETION 86 149 #define OPAL_SYNC_HOST_REBOOT 87 150 #define OPAL_SENSOR_READ 88 151 #define OPAL_GET_PARAM 89 152 #define OPAL_SET_PARAM 90 153 #define OPAL_DUMP_RESEND 91 154 #define OPAL_ELOG_SEND 92 /* Deprecated */ 155 #define OPAL_PCI_SET_PHB_CAPI_MODE 93 156 #define OPAL_DUMP_INFO2 94 157 #define OPAL_WRITE_OPPANEL_ASYNC 95 158 #define OPAL_PCI_ERR_INJECT 96 159 #define OPAL_PCI_EEH_FREEZE_SET 97 160 #define OPAL_HANDLE_HMI 98 161 #define OPAL_CONFIG_CPU_IDLE_STATE 99 162 #define OPAL_SLW_SET_REG 100 163 #define OPAL_REGISTER_DUMP_REGION 101 164 #define OPAL_UNREGISTER_DUMP_REGION 102 165 #define OPAL_WRITE_TPO 103 166 #define OPAL_READ_TPO 104 167 #define OPAL_GET_DPO_STATUS 105 168 #define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */ 169 #define OPAL_IPMI_SEND 107 170 #define OPAL_IPMI_RECV 108 171 #define OPAL_I2C_REQUEST 109 172 #define OPAL_FLASH_READ 110 173 #define OPAL_FLASH_WRITE 111 174 #define OPAL_FLASH_ERASE 112 175 #define OPAL_PRD_MSG 113 176 #define OPAL_LEDS_GET_INDICATOR 114 177 #define OPAL_LEDS_SET_INDICATOR 115 178 #define OPAL_CEC_REBOOT2 116 179 #define OPAL_CONSOLE_FLUSH 117 180 #define OPAL_GET_DEVICE_TREE 118 181 #define OPAL_PCI_GET_PRESENCE_STATE 119 182 #define OPAL_PCI_GET_POWER_STATE 120 183 #define OPAL_PCI_SET_POWER_STATE 121 184 #define OPAL_INT_GET_XIRR 122 185 #define OPAL_INT_SET_CPPR 123 186 #define OPAL_INT_EOI 124 187 #define OPAL_INT_SET_MFRR 125 188 #define OPAL_PCI_TCE_KILL 126 189 #define OPAL_NMMU_SET_PTCR 127 190 #define OPAL_XIVE_RESET 128 191 #define OPAL_XIVE_GET_IRQ_INFO 129 192 #define OPAL_XIVE_GET_IRQ_CONFIG 130 193 #define OPAL_XIVE_SET_IRQ_CONFIG 131 194 #define OPAL_XIVE_GET_QUEUE_INFO 132 195 #define OPAL_XIVE_SET_QUEUE_INFO 133 196 #define OPAL_XIVE_DONATE_PAGE 134 197 #define OPAL_XIVE_ALLOCATE_VP_BLOCK 135 198 #define OPAL_XIVE_FREE_VP_BLOCK 136 199 #define OPAL_XIVE_GET_VP_INFO 137 200 #define OPAL_XIVE_SET_VP_INFO 138 201 #define OPAL_XIVE_ALLOCATE_IRQ 139 202 #define OPAL_XIVE_FREE_IRQ 140 203 #define OPAL_XIVE_SYNC 141 204 #define OPAL_XIVE_DUMP 142 205 #define OPAL_XIVE_GET_QUEUE_STATE 143 /* Get END state */ 206 #define OPAL_XIVE_SET_QUEUE_STATE 144 /* Set END state */ 207 #define OPAL_SIGNAL_SYSTEM_RESET 145 208 #define OPAL_NPU_INIT_CONTEXT 146 209 #define OPAL_NPU_DESTROY_CONTEXT 147 210 #define OPAL_NPU_MAP_LPAR 148 211 #define OPAL_IMC_COUNTERS_INIT 149 212 #define OPAL_IMC_COUNTERS_START 150 213 #define OPAL_IMC_COUNTERS_STOP 151 214 #define OPAL_GET_POWERCAP 152 215 #define OPAL_SET_POWERCAP 153 216 #define OPAL_GET_POWER_SHIFT_RATIO 154 217 #define OPAL_SET_POWER_SHIFT_RATIO 155 218 #define OPAL_SENSOR_GROUP_CLEAR 156 219 #define OPAL_PCI_SET_P2P 157 220 #define OPAL_QUIESCE 158 221 #define OPAL_NPU_SPA_SETUP 159 222 #define OPAL_NPU_SPA_CLEAR_CACHE 160 223 #define OPAL_NPU_TL_SET 161 224 #define OPAL_SENSOR_READ_U64 162 225 #define OPAL_SENSOR_GROUP_ENABLE 163 226 #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164 227 #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165 228 #define OPAL_HANDLE_HMI2 166 229 #define OPAL_NX_COPROC_INIT 167 230 #define OPAL_NPU_SET_RELAXED_ORDER 168 231 #define OPAL_NPU_GET_RELAXED_ORDER 169 232 #define OPAL_XIVE_GET_VP_STATE 170 /* Get NVT state */ 233 #define OPAL_NPU_MEM_ALLOC 171 234 #define OPAL_NPU_MEM_RELEASE 172 235 #define OPAL_LAST 172 236 237 #define QUIESCE_HOLD 1 /* Spin all calls at entry */ 238 #define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */ 239 #define QUIESCE_LOCK_BREAK 3 /* Set to ignore locks. */ 240 #define QUIESCE_RESUME 4 /* Un-quiesce */ 241 #define QUIESCE_RESUME_FAST_REBOOT 5 /* Un-quiesce, fast reboot */ 242 243 /* Device tree flags */ 244 245 /* 246 * Flags set in power-mgmt nodes in device tree describing 247 * idle states that are supported in the platform. 248 */ 249 #define OPAL_PM_DEC_STOP 0x00000001 /* Decrementer would stop */ 250 #define OPAL_PM_TIMEBASE_STOP 0x00000002 /* Needs timebase restore */ 251 #define OPAL_PM_LOSE_USER_CONTEXT 0x00001000 /* Restore GPRs like nap */ 252 #define OPAL_PM_LOSE_HYP_CONTEXT 0x00002000 /* Restore hypervisor 253 resource from PACA pointer */ 254 #define OPAL_PM_LOSE_FULL_CONTEXT 0x00004000 255 #define OPAL_PM_NAP_ENABLED 0x00010000 256 #define OPAL_PM_SLEEP_ENABLED 0x00020000 257 #define OPAL_PM_WINKLE_ENABLED 0x00040000 258 #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */ 259 #define OPAL_USE_PMICR 0x00800000 /* Use SPR PMICR instruction */ 260 261 #define OPAL_PM_FASTSLEEP_PMICR 0x0000002000000000UL 262 #define OPAL_PM_DEEPSLEEP_PMICR 0x0000003000000000UL 263 #define OPAL_PM_SLEEP_PMICR_MASK 0x0000003000000000UL 264 265 #define OPAL_PM_FASTWINKLE_PMICR 0x0000000000200000UL 266 #define OPAL_PM_DEEPWINKLE_PMICR 0x0000000000300000UL 267 #define OPAL_PM_WINKLE_PMICR_MASK 0x0000000000300000UL 268 269 #define OPAL_PM_PSSCR_RL_MASK 0x000000000000000FUL 270 #define OPAL_PM_PSSCR_MTL_MASK 0x00000000000000F0UL 271 #define OPAL_PM_PSSCR_TR_MASK 0x0000000000000300UL 272 #define OPAL_PM_PSSCR_ESL PPC_BIT(42) 273 #define OPAL_PM_PSSCR_EC PPC_BIT(43) 274 275 #define OPAL_PM_PSSCR_MASK OPAL_PM_PSSCR_RL_MASK | \ 276 OPAL_PM_PSSCR_MTL_MASK | \ 277 OPAL_PM_PSSCR_TR_MASK | \ 278 OPAL_PM_PSSCR_ESL | \ 279 OPAL_PM_PSSCR_EC 280 281 #define OPAL_PM_PSSCR_RL(l) (l) 282 #define OPAL_PM_PSSCR_MTL(l) ((l) << 4) 283 #define OPAL_PM_PSSCR_TR(l) ((l) << 8) 284 285 /* 286 * Flags for stop states. Use 2 bits to distinguish between 287 * deep and fast states. Deep states result in full context 288 * loss thereby requiring slw to partially restore state 289 * whereas fast state can function without the presence of 290 * slw. 291 */ 292 #define OPAL_PM_STOP_INST_FAST 0x00100000 293 #define OPAL_PM_STOP_INST_DEEP 0x00200000 294 295 #ifndef __ASSEMBLY__ 296 297 #include <stdbool.h> 298 #include <types.h> 299 300 /* Other enums */ 301 enum OpalVendorApiTokens { 302 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999 303 }; 304 305 enum OpalFreezeState { 306 OPAL_EEH_STOPPED_NOT_FROZEN = 0, 307 OPAL_EEH_STOPPED_MMIO_FREEZE = 1, 308 OPAL_EEH_STOPPED_DMA_FREEZE = 2, 309 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3, 310 OPAL_EEH_STOPPED_RESET = 4, 311 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5, 312 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6 313 }; 314 315 enum OpalEehFreezeActionToken { 316 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1, 317 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2, 318 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3, 319 320 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1, 321 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2, 322 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3 323 }; 324 325 enum OpalPciStatusToken { 326 OPAL_EEH_NO_ERROR = 0, 327 OPAL_EEH_IOC_ERROR = 1, 328 OPAL_EEH_PHB_ERROR = 2, 329 OPAL_EEH_PE_ERROR = 3, 330 OPAL_EEH_PE_MMIO_ERROR = 4, 331 OPAL_EEH_PE_DMA_ERROR = 5 332 }; 333 334 enum OpalPciErrorSeverity { 335 OPAL_EEH_SEV_NO_ERROR = 0, 336 OPAL_EEH_SEV_IOC_DEAD = 1, 337 OPAL_EEH_SEV_PHB_DEAD = 2, 338 OPAL_EEH_SEV_PHB_FENCED = 3, 339 OPAL_EEH_SEV_PE_ER = 4, 340 OPAL_EEH_SEV_INF = 5 341 }; 342 343 enum OpalErrinjectType { 344 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0, 345 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1, 346 }; 347 348 enum OpalErrinjectFunc { 349 /* IOA bus specific errors */ 350 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0, 351 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1, 352 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2, 353 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3, 354 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4, 355 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5, 356 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6, 357 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7, 358 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8, 359 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9, 360 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10, 361 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11, 362 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12, 363 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13, 364 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14, 365 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15, 366 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16, 367 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17, 368 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18, 369 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19, 370 }; 371 372 enum OpalShpcAction { 373 OPAL_SHPC_GET_LINK_STATE = 0, 374 OPAL_SHPC_GET_SLOT_STATE = 1 375 }; 376 377 enum OpalShpcLinkState { 378 OPAL_SHPC_LINK_DOWN = 0, 379 OPAL_SHPC_LINK_UP_x1 = 1, 380 OPAL_SHPC_LINK_UP_x2 = 2, 381 OPAL_SHPC_LINK_UP_x4 = 4, 382 OPAL_SHPC_LINK_UP_x8 = 8, 383 OPAL_SHPC_LINK_UP_x16 = 16, 384 OPAL_SHPC_LINK_UP_x32 = 32 385 }; 386 387 enum OpalMmioWindowType { 388 OPAL_M32_WINDOW_TYPE = 1, 389 OPAL_M64_WINDOW_TYPE = 2, 390 OPAL_IO_WINDOW_TYPE = 3 391 }; 392 393 enum OpalShpcSlotState { 394 OPAL_SHPC_DEV_NOT_PRESENT = 0, 395 OPAL_SHPC_DEV_PRESENT = 1 396 }; 397 enum OpalShpcPowerState { 398 OPAL_SHPC_POWER_OFF = 0, 399 OPAL_SHPC_POWER_ON = 1 400 }; 401 402 enum OpalExceptionHandler { 403 OPAL_MACHINE_CHECK_HANDLER = 1, 404 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2, 405 OPAL_SOFTPATCH_HANDLER = 3 406 }; 407 408 enum OpalPendingState { 409 OPAL_EVENT_OPAL_INTERNAL = 0x1, 410 OPAL_EVENT_NVRAM = 0x2, 411 OPAL_EVENT_RTC = 0x4, 412 OPAL_EVENT_CONSOLE_OUTPUT = 0x8, 413 OPAL_EVENT_CONSOLE_INPUT = 0x10, 414 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20, 415 OPAL_EVENT_ERROR_LOG = 0x40, 416 OPAL_EVENT_EPOW = 0x80, 417 OPAL_EVENT_LED_STATUS = 0x100, 418 OPAL_EVENT_PCI_ERROR = 0x200, 419 OPAL_EVENT_DUMP_AVAIL = 0x400, 420 OPAL_EVENT_MSG_PENDING = 0x800, 421 }; 422 423 enum OpalThreadStatus { 424 OPAL_THREAD_INACTIVE = 0x0, 425 OPAL_THREAD_STARTED = 0x1, 426 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */ 427 }; 428 429 enum OpalPciBusCompare { 430 OpalPciBusAny = 0, /* Any bus number match */ 431 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */ 432 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */ 433 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */ 434 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */ 435 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */ 436 OpalPciBusAll = 7, /* Match bus number exactly */ 437 }; 438 439 enum OpalDeviceCompare { 440 OPAL_IGNORE_RID_DEVICE_NUMBER = 0, 441 OPAL_COMPARE_RID_DEVICE_NUMBER = 1 442 }; 443 444 enum OpalFuncCompare { 445 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0, 446 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1 447 }; 448 449 enum OpalPeAction { 450 OPAL_UNMAP_PE = 0, 451 OPAL_MAP_PE = 1 452 }; 453 454 enum OpalPeltvAction { 455 OPAL_REMOVE_PE_FROM_DOMAIN = 0, 456 OPAL_ADD_PE_TO_DOMAIN = 1 457 }; 458 459 enum OpalMveEnableAction { 460 OPAL_DISABLE_MVE = 0, 461 OPAL_ENABLE_MVE = 1 462 }; 463 464 enum OpalM64Action { 465 OPAL_DISABLE_M64 = 0, 466 OPAL_ENABLE_M64_SPLIT = 1, 467 OPAL_ENABLE_M64_NON_SPLIT = 2 468 }; 469 470 enum OpalPciResetScope { 471 OPAL_RESET_PHB_COMPLETE = 1, 472 OPAL_RESET_PCI_LINK = 2, 473 OPAL_RESET_PHB_ERROR = 3, 474 OPAL_RESET_PCI_HOT = 4, 475 OPAL_RESET_PCI_FUNDAMENTAL = 5, 476 OPAL_RESET_PCI_IODA_TABLE = 6 477 }; 478 479 enum OpalPciReinitScope { 480 /* 481 * Note: we chose values that do not overlap 482 * OpalPciResetScope as OPAL v2 used the same 483 * enum for both 484 */ 485 OPAL_REINIT_PCI_DEV = 1000 486 }; 487 488 enum OpalPciResetState { 489 OPAL_DEASSERT_RESET = 0, 490 OPAL_ASSERT_RESET = 1 491 }; 492 493 enum OpalPciMaskAction { 494 OPAL_UNMASK_ERROR_TYPE = 0, 495 OPAL_MASK_ERROR_TYPE = 1 496 }; 497 498 enum OpalPciSlotPresence { 499 OPAL_PCI_SLOT_EMPTY = 0, 500 OPAL_PCI_SLOT_PRESENT = 1 501 }; 502 503 enum OpalPciSlotPower { 504 OPAL_PCI_SLOT_POWER_OFF = 0, 505 OPAL_PCI_SLOT_POWER_ON = 1, 506 OPAL_PCI_SLOT_OFFLINE = 2, 507 OPAL_PCI_SLOT_ONLINE = 3 508 }; 509 510 enum OpalSlotLedType { 511 OPAL_SLOT_LED_TYPE_ID = 0, /* IDENTIFY LED */ 512 OPAL_SLOT_LED_TYPE_FAULT = 1, /* FAULT LED */ 513 OPAL_SLOT_LED_TYPE_ATTN = 2, /* System Attention LED */ 514 OPAL_SLOT_LED_TYPE_MAX = 3 515 }; 516 517 enum OpalSlotLedState { 518 OPAL_SLOT_LED_STATE_OFF = 0, /* LED is OFF */ 519 OPAL_SLOT_LED_STATE_ON = 1 /* LED is ON */ 520 }; 521 522 enum OpalEpowStatus { 523 OPAL_EPOW_NONE = 0, 524 OPAL_EPOW_UPS = 1, 525 OPAL_EPOW_OVER_AMBIENT_TEMP = 2, 526 OPAL_EPOW_OVER_INTERNAL_TEMP = 3 527 }; 528 529 enum OpalCheckTokenStatus { 530 OPAL_TOKEN_ABSENT = 0, 531 OPAL_TOKEN_PRESENT = 1 532 }; 533 534 /* 535 * Address cycle types for LPC accesses. These also correspond 536 * to the content of the first cell of the "reg" property for 537 * device nodes on the LPC bus 538 */ 539 enum OpalLPCAddressType { 540 OPAL_LPC_MEM = 0, 541 OPAL_LPC_IO = 1, 542 OPAL_LPC_FW = 2, 543 }; 544 545 enum opal_msg_type { 546 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc, 547 * additional params function-specific 548 */ 549 OPAL_MSG_MEM_ERR = 1, 550 OPAL_MSG_EPOW = 2, 551 OPAL_MSG_SHUTDOWN = 3, /* params[0] = 1 reboot, 0 shutdown */ 552 OPAL_MSG_HMI_EVT = 4, 553 OPAL_MSG_DPO = 5, 554 OPAL_MSG_PRD = 6, 555 OPAL_MSG_OCC = 7, 556 OPAL_MSG_PRD2 = 8, 557 OPAL_MSG_TYPE_MAX, 558 }; 559 560 struct opal_msg { 561 __be32 msg_type; 562 __be32 size; 563 __be64 params[8]; 564 }; 565 566 /* System parameter permission */ 567 enum OpalSysparamPerm { 568 OPAL_SYSPARAM_READ = 0x1, 569 OPAL_SYSPARAM_WRITE = 0x2, 570 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE), 571 }; 572 573 enum { 574 OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1, 575 }; 576 577 struct opal_ipmi_msg { 578 uint8_t version; 579 uint8_t netfn; 580 uint8_t cmd; 581 uint8_t data[]; 582 }; 583 584 /* 585 * EPOW status sharing (OPAL and the host) 586 * 587 * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX 588 * with individual elements being 16 bits wide to fetch the system 589 * wide EPOW status. Each element in the buffer will contain the 590 * EPOW status in it's bit representation for a particular EPOW sub 591 * class as defined here. So multiple detailed EPOW status bits 592 * specific for any sub class can be represented in a single buffer 593 * element as it's bit representation. 594 */ 595 596 /* System EPOW type */ 597 enum OpalSysEpow { 598 OPAL_SYSEPOW_POWER = 0, /* Power EPOW */ 599 OPAL_SYSEPOW_TEMP = 1, /* Temperature EPOW */ 600 OPAL_SYSEPOW_COOLING = 2, /* Cooling EPOW */ 601 OPAL_SYSEPOW_MAX = 3, /* Max EPOW categories */ 602 }; 603 604 /* Power EPOW */ 605 enum OpalSysPower { 606 OPAL_SYSPOWER_UPS = 0x0001, /* System on UPS power */ 607 OPAL_SYSPOWER_CHNG = 0x0002, /* System power configuration change */ 608 OPAL_SYSPOWER_FAIL = 0x0004, /* System impending power failure */ 609 OPAL_SYSPOWER_INCL = 0x0008, /* System incomplete power */ 610 }; 611 612 /* Temperature EPOW */ 613 enum OpalSysTemp { 614 OPAL_SYSTEMP_AMB = 0x0001, /* System over ambient temperature */ 615 OPAL_SYSTEMP_INT = 0x0002, /* System over internal temperature */ 616 OPAL_SYSTEMP_HMD = 0x0004, /* System over ambient humidity */ 617 }; 618 619 /* Cooling EPOW */ 620 enum OpalSysCooling { 621 OPAL_SYSCOOL_INSF = 0x0001, /* System insufficient cooling */ 622 }; 623 624 /* FSP memory errors handling */ 625 enum OpalMemErr_Version { 626 OpalMemErr_V1 = 1, 627 }; 628 629 enum OpalMemErrType { 630 OPAL_MEM_ERR_TYPE_RESILIENCE = 0, 631 OPAL_MEM_ERR_TYPE_DYN_DALLOC, 632 }; 633 634 /* Memory Reilience error type */ 635 enum OpalMemErr_ResilErrType { 636 OPAL_MEM_RESILIENCE_CE = 0, 637 OPAL_MEM_RESILIENCE_UE, 638 OPAL_MEM_RESILIENCE_UE_SCRUB, 639 }; 640 641 /* Dynamic Memory Deallocation type */ 642 enum OpalMemErr_DynErrType { 643 OPAL_MEM_DYNAMIC_DEALLOC = 0, 644 }; 645 646 /* OpalMemoryErrorData->flags */ 647 #define OPAL_MEM_CORRECTED_ERROR 0x0001 648 #define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002 649 #define OPAL_MEM_ACK_REQUIRED 0x8000 650 651 struct OpalMemoryErrorData { 652 enum OpalMemErr_Version version:8; /* 0x00 */ 653 enum OpalMemErrType type:8; /* 0x01 */ 654 __be16 flags; /* 0x02 */ 655 uint8_t reserved_1[4]; /* 0x04 */ 656 657 union { 658 /* Memory Resilience corrected/uncorrected error info */ 659 struct { 660 enum OpalMemErr_ResilErrType resil_err_type:8; 661 uint8_t reserved_1[7]; 662 __be64 physical_address_start; 663 __be64 physical_address_end; 664 } resilience; 665 /* Dynamic memory deallocation error info */ 666 struct { 667 enum OpalMemErr_DynErrType dyn_err_type:8; 668 uint8_t reserved_1[7]; 669 __be64 physical_address_start; 670 __be64 physical_address_end; 671 } dyn_dealloc; 672 } u; 673 }; 674 675 /* HMI interrupt event */ 676 enum OpalHMI_Version { 677 OpalHMIEvt_V1 = 1, 678 OpalHMIEvt_V2 = 2, 679 }; 680 681 enum OpalHMI_Severity { 682 OpalHMI_SEV_NO_ERROR = 0, 683 OpalHMI_SEV_WARNING = 1, 684 OpalHMI_SEV_ERROR_SYNC = 2, 685 OpalHMI_SEV_FATAL = 3, 686 }; 687 688 enum OpalHMI_Disposition { 689 OpalHMI_DISPOSITION_RECOVERED = 0, 690 OpalHMI_DISPOSITION_NOT_RECOVERED = 1, 691 }; 692 693 enum OpalHMI_ErrType { 694 OpalHMI_ERROR_MALFUNC_ALERT = 0, 695 OpalHMI_ERROR_PROC_RECOV_DONE, 696 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN, 697 OpalHMI_ERROR_PROC_RECOV_MASKED, 698 OpalHMI_ERROR_TFAC, 699 OpalHMI_ERROR_TFMR_PARITY, 700 OpalHMI_ERROR_HA_OVERFLOW_WARN, 701 OpalHMI_ERROR_XSCOM_FAIL, 702 OpalHMI_ERROR_XSCOM_DONE, 703 OpalHMI_ERROR_SCOM_FIR, 704 OpalHMI_ERROR_DEBUG_TRIG_FIR, 705 OpalHMI_ERROR_HYP_RESOURCE, 706 OpalHMI_ERROR_CAPP_RECOVERY, 707 }; 708 709 enum OpalHMI_XstopType { 710 CHECKSTOP_TYPE_UNKNOWN = 0, 711 CHECKSTOP_TYPE_CORE = 1, 712 CHECKSTOP_TYPE_NX = 2, 713 CHECKSTOP_TYPE_NPU = 3 714 }; 715 716 enum OpalHMI_CoreXstopReason { 717 CORE_CHECKSTOP_IFU_REGFILE = 0x00000001, 718 CORE_CHECKSTOP_IFU_LOGIC = 0x00000002, 719 CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004, 720 CORE_CHECKSTOP_ISU_REGFILE = 0x00000008, 721 CORE_CHECKSTOP_ISU_LOGIC = 0x00000010, 722 CORE_CHECKSTOP_FXU_LOGIC = 0x00000020, 723 CORE_CHECKSTOP_VSU_LOGIC = 0x00000040, 724 CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080, 725 CORE_CHECKSTOP_LSU_REGFILE = 0x00000100, 726 CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200, 727 CORE_CHECKSTOP_LSU_LOGIC = 0x00000400, 728 CORE_CHECKSTOP_PC_LOGIC = 0x00000800, 729 CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000, 730 CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000, 731 CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000, 732 CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000, 733 CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000, 734 }; 735 736 enum OpalHMI_NestAccelXstopReason { 737 NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001, 738 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002, 739 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004, 740 NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008, 741 NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010, 742 NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020, 743 NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040, 744 NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080, 745 NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100, 746 NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200, 747 NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400, 748 NX_CHECKSTOP_DMA_CRB_UE = 0x00000800, 749 NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000, 750 NX_CHECKSTOP_PBI_ISN_UE = 0x00002000, 751 }; 752 753 struct OpalHMIEvent { 754 uint8_t version; /* 0x00 */ 755 uint8_t severity; /* 0x01 */ 756 uint8_t type; /* 0x02 */ 757 uint8_t disposition; /* 0x03 */ 758 uint8_t reserved_1[4]; /* 0x04 */ 759 760 __be64 hmer; 761 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */ 762 __be64 tfmr; 763 764 /* version 2 and later */ 765 union { 766 /* 767 * checkstop info (Core/NX). 768 * Valid for OpalHMI_ERROR_MALFUNC_ALERT. 769 */ 770 struct { 771 uint8_t xstop_type; /* enum OpalHMI_XstopType */ 772 uint8_t reserved_1[3]; 773 __be32 xstop_reason; 774 union { 775 __be32 pir; /* for CHECKSTOP_TYPE_CORE */ 776 __be32 chip_id; /* for CHECKSTOP_TYPE_NX */ 777 } u; 778 } xstop_error; 779 } u; 780 }; 781 782 /* OPAL_HANDLE_HMI2 out_flags */ 783 enum { 784 OPAL_HMI_FLAGS_TB_RESYNC = (1ull << 0), /* Timebase has been resynced */ 785 OPAL_HMI_FLAGS_DEC_LOST = (1ull << 1), /* DEC lost, needs to be reprogrammed */ 786 OPAL_HMI_FLAGS_HDEC_LOST = (1ull << 2), /* HDEC lost, needs to be reprogrammed */ 787 OPAL_HMI_FLAGS_TOD_TB_FAIL = (1ull << 3), /* TOD/TB recovery failed. */ 788 OPAL_HMI_FLAGS_NEW_EVENT = (1ull << 63), /* An event has been created */ 789 }; 790 791 /** 792 * This structure defines the overlay which will be used to store PHB error 793 * data upon request. 794 */ 795 enum { 796 OPAL_PHB_ERROR_DATA_VERSION_1 = 1, 797 }; 798 799 enum { 800 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2, 801 OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3 802 }; 803 804 enum { 805 OPAL_PHB3_NUM_PEST_REGS = 256, 806 OPAL_PHB4_NUM_PEST_REGS = 512 807 }; 808 809 struct OpalIoPhbErrorCommon { 810 __be32 version; 811 __be32 ioType; 812 __be32 len; 813 }; 814 815 struct OpalIoPhb3ErrorData { 816 struct OpalIoPhbErrorCommon common; 817 818 __be32 brdgCtl; 819 820 /* PHB3 UTL regs */ 821 __be32 portStatusReg; 822 __be32 rootCmplxStatus; 823 __be32 busAgentStatus; 824 825 /* PHB3 cfg regs */ 826 __be32 deviceStatus; 827 __be32 slotStatus; 828 __be32 linkStatus; 829 __be32 devCmdStatus; 830 __be32 devSecStatus; 831 832 /* cfg AER regs */ 833 __be32 rootErrorStatus; 834 __be32 uncorrErrorStatus; 835 __be32 corrErrorStatus; 836 __be32 tlpHdr1; 837 __be32 tlpHdr2; 838 __be32 tlpHdr3; 839 __be32 tlpHdr4; 840 __be32 sourceId; 841 842 __be32 rsv3; 843 844 /* Record data about the call to allocate a buffer */ 845 __be64 errorClass; 846 __be64 correlator; 847 848 /* PHB3 MMIO Error Regs */ 849 __be64 nFir; /* 000 */ 850 __be64 nFirMask; /* 003 */ 851 __be64 nFirWOF; /* 008 */ 852 __be64 phbPlssr; /* 120 */ 853 __be64 phbCsr; /* 110 */ 854 __be64 lemFir; /* C00 */ 855 __be64 lemErrorMask; /* C18 */ 856 __be64 lemWOF; /* C40 */ 857 __be64 phbErrorStatus; /* C80 */ 858 __be64 phbFirstErrorStatus; /* C88 */ 859 __be64 phbErrorLog0; /* CC0 */ 860 __be64 phbErrorLog1; /* CC8 */ 861 __be64 mmioErrorStatus; /* D00 */ 862 __be64 mmioFirstErrorStatus; /* D08 */ 863 __be64 mmioErrorLog0; /* D40 */ 864 __be64 mmioErrorLog1; /* D48 */ 865 __be64 dma0ErrorStatus; /* D80 */ 866 __be64 dma0FirstErrorStatus; /* D88 */ 867 __be64 dma0ErrorLog0; /* DC0 */ 868 __be64 dma0ErrorLog1; /* DC8 */ 869 __be64 dma1ErrorStatus; /* E00 */ 870 __be64 dma1FirstErrorStatus; /* E08 */ 871 __be64 dma1ErrorLog0; /* E40 */ 872 __be64 dma1ErrorLog1; /* E48 */ 873 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS]; 874 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS]; 875 }; 876 877 struct OpalIoPhb4ErrorData { 878 struct OpalIoPhbErrorCommon common; 879 880 __be32 brdgCtl; 881 882 /* XXX missing UTL registers? */ 883 884 /* PHB4 cfg regs */ 885 __be32 deviceStatus; 886 __be32 slotStatus; 887 __be32 linkStatus; 888 __be32 devCmdStatus; 889 __be32 devSecStatus; 890 891 /* cfg AER regs */ 892 __be32 rootErrorStatus; 893 __be32 uncorrErrorStatus; 894 __be32 corrErrorStatus; 895 __be32 tlpHdr1; 896 __be32 tlpHdr2; 897 __be32 tlpHdr3; 898 __be32 tlpHdr4; 899 __be32 sourceId; 900 901 /* PHB4 ETU Error Regs */ 902 __be64 nFir; /* 000 */ 903 __be64 nFirMask; /* 003 */ 904 __be64 nFirWOF; /* 008 */ 905 __be64 phbPlssr; /* 120 */ 906 __be64 phbCsr; /* 110 */ 907 __be64 lemFir; /* C00 */ 908 __be64 lemErrorMask; /* C18 */ 909 __be64 lemWOF; /* C40 */ 910 __be64 phbErrorStatus; /* C80 */ 911 __be64 phbFirstErrorStatus; /* C88 */ 912 __be64 phbErrorLog0; /* CC0 */ 913 __be64 phbErrorLog1; /* CC8 */ 914 __be64 phbTxeErrorStatus; /* D00 */ 915 __be64 phbTxeFirstErrorStatus; /* D08 */ 916 __be64 phbTxeErrorLog0; /* D40 */ 917 __be64 phbTxeErrorLog1; /* D48 */ 918 __be64 phbRxeArbErrorStatus; /* D80 */ 919 __be64 phbRxeArbFirstErrorStatus; /* D88 */ 920 __be64 phbRxeArbErrorLog0; /* DC0 */ 921 __be64 phbRxeArbErrorLog1; /* DC8 */ 922 __be64 phbRxeMrgErrorStatus; /* E00 */ 923 __be64 phbRxeMrgFirstErrorStatus; /* E08 */ 924 __be64 phbRxeMrgErrorLog0; /* E40 */ 925 __be64 phbRxeMrgErrorLog1; /* E48 */ 926 __be64 phbRxeTceErrorStatus; /* E80 */ 927 __be64 phbRxeTceFirstErrorStatus; /* E88 */ 928 __be64 phbRxeTceErrorLog0; /* EC0 */ 929 __be64 phbRxeTceErrorLog1; /* EC8 */ 930 931 /* PHB4 REGB Error Regs */ 932 __be64 phbPblErrorStatus; /* 1900 */ 933 __be64 phbPblFirstErrorStatus; /* 1908 */ 934 __be64 phbPblErrorLog0; /* 1940 */ 935 __be64 phbPblErrorLog1; /* 1948 */ 936 __be64 phbPcieDlpErrorLog1; /* 1AA0 */ 937 __be64 phbPcieDlpErrorLog2; /* 1AA8 */ 938 __be64 phbPcieDlpErrorStatus; /* 1AB0 */ 939 __be64 phbRegbErrorStatus; /* 1C00 */ 940 __be64 phbRegbFirstErrorStatus; /* 1C08 */ 941 __be64 phbRegbErrorLog0; /* 1C40 */ 942 __be64 phbRegbErrorLog1; /* 1C48 */ 943 944 __be64 pestA[OPAL_PHB4_NUM_PEST_REGS]; 945 __be64 pestB[OPAL_PHB4_NUM_PEST_REGS]; 946 }; 947 948 enum { 949 OPAL_REINIT_CPUS_HILE_BE = (1 << 0), 950 OPAL_REINIT_CPUS_HILE_LE = (1 << 1), 951 952 /* These two define the base MMU mode of the host on P9 953 * 954 * On P9 Nimbus DD2.0 and Cumlus (and later), KVM can still 955 * create hash guests in "radix" mode with care (full core 956 * switch only). 957 */ 958 OPAL_REINIT_CPUS_MMU_HASH = (1 << 2), 959 OPAL_REINIT_CPUS_MMU_RADIX = (1 << 3), 960 961 OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED = (1 << 4), 962 }; 963 964 typedef struct oppanel_line { 965 __be64 line; 966 __be64 line_len; 967 } oppanel_line_t; 968 969 enum opal_prd_msg_type { 970 OPAL_PRD_MSG_TYPE_INIT = 0, /* HBRT --> OPAL */ 971 OPAL_PRD_MSG_TYPE_FINI, /* HBRT/kernel --> OPAL */ 972 OPAL_PRD_MSG_TYPE_ATTN, /* HBRT <-- OPAL */ 973 OPAL_PRD_MSG_TYPE_ATTN_ACK, /* HBRT --> OPAL */ 974 OPAL_PRD_MSG_TYPE_OCC_ERROR, /* HBRT <-- OPAL */ 975 OPAL_PRD_MSG_TYPE_OCC_RESET, /* HBRT <-- OPAL */ 976 OPAL_PRD_MSG_TYPE_OCC_RESET_NOTIFY, /* HBRT --> OPAL */ 977 OPAL_PRD_MSG_TYPE_FIRMWARE_REQUEST, /* HBRT --> OPAL */ 978 OPAL_PRD_MSG_TYPE_FIRMWARE_RESPONSE, /* HBRT <-- OPAL */ 979 OPAL_PRD_MSG_TYPE_FIRMWARE_NOTIFY, /* HBRT <-- OPAL */ 980 OPAL_PRD_MSG_TYPE_SBE_PASSTHROUGH, /* HBRT <-- OPAL */ 981 OPAL_PRD_MSG_TYPE_FSP_OCC_RESET, /* HBRT <-- OPAL */ 982 OPAL_PRD_MSG_TYPE_FSP_OCC_RESET_STATUS, /* HBRT --> OPAL */ 983 OPAL_PRD_MSG_TYPE_CORE_SPECIAL_WAKEUP, /* HBRT --> OPAL */ 984 OPAL_PRD_MSG_TYPE_FSP_OCC_LOAD_START, /* HBRT <-- OPAL */ 985 OPAL_PRD_MSG_TYPE_FSP_OCC_LOAD_START_STATUS, /* HBRT --> OPAL */ 986 }; 987 988 #define OPAL_PRD_MSG_SIZE_MAX (1 << 16) 989 990 struct opal_prd_msg_header { 991 uint8_t type; 992 uint8_t pad[1]; 993 __be16 size; 994 }; 995 996 struct opal_prd_msg { 997 struct opal_prd_msg_header hdr; 998 __be32 token; 999 union { 1000 struct { 1001 __be64 version; 1002 __be64 ipoll; 1003 } init; 1004 struct { 1005 __be64 proc; 1006 __be64 ipoll_status; 1007 __be64 ipoll_mask; 1008 } attn; 1009 struct { 1010 __be64 proc; 1011 __be64 ipoll_ack; 1012 } attn_ack; 1013 struct { 1014 __be64 chip; 1015 } occ_error; 1016 struct { 1017 __be64 chip; 1018 } occ_reset; 1019 struct { 1020 __be64 req_len; 1021 __be64 resp_len; 1022 char data[]; 1023 } fw_req; 1024 struct { 1025 __be64 len; 1026 char data[]; 1027 } fw_resp; 1028 struct { 1029 __be64 len; 1030 char data[]; 1031 } fw_notify; 1032 struct { 1033 __be64 chip; 1034 } sbe_passthrough; 1035 struct { 1036 __be64 chip; 1037 __be64 status; /* 0 SUCCESS */ 1038 } fsp_occ_reset_status; 1039 struct { 1040 __be32 core; 1041 __be32 mode; 1042 } spl_wakeup; 1043 }; 1044 }; 1045 1046 #define OCC_RESET 0 1047 #define OCC_LOAD 1 1048 #define OCC_THROTTLE 2 1049 #define OCC_MAX_THROTTLE_STATUS 5 1050 /* 1051 * struct opal_occ_msg: 1052 * type: OCC_RESET, OCC_LOAD, OCC_THROTTLE 1053 * chip: chip id 1054 * throttle status: indicates the reason why OCC may have limited 1055 * the max Pstate of the chip. 1056 * 0x00 = No throttle 1057 * 0x01 = Power Cap 1058 * 0x02 = Processor Over Temperature 1059 * 0x03 = Power Supply Failure (currently not used) 1060 * 0x04 = Over current (currently not used) 1061 * 0x05 = OCC Reset (not reliable as some failures will not allow for 1062 * OCC to update throttle status) 1063 */ 1064 struct opal_occ_msg { 1065 __be64 type; 1066 __be64 chip; 1067 __be64 throttle_status; 1068 }; 1069 1070 /* 1071 * SG entries 1072 * 1073 * WARNING: The current implementation requires each entry 1074 * to represent a block that is 4k aligned *and* each block 1075 * size except the last one in the list to be as well. 1076 */ 1077 struct opal_sg_entry { 1078 __be64 data; 1079 __be64 length; 1080 }; 1081 1082 /* 1083 * Candidate image SG list. 1084 * 1085 * length = VER | length 1086 */ 1087 struct opal_sg_list { 1088 __be64 length; 1089 __be64 next; 1090 struct opal_sg_entry entry[]; 1091 }; 1092 1093 /* 1094 * Dump region ID range usable by the OS 1095 */ 1096 #define OPAL_DUMP_REGION_HOST_START 0x80 1097 #define OPAL_DUMP_REGION_LOG_BUF 0x80 1098 #define OPAL_DUMP_REGION_HOST_END 0xFF 1099 1100 /* CAPI modes for PHB */ 1101 enum { 1102 OPAL_PHB_CAPI_MODE_PCIE = 0, 1103 OPAL_PHB_CAPI_MODE_CAPI = 1, 1104 OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2, 1105 OPAL_PHB_CAPI_MODE_SNOOP_ON = 3, 1106 OPAL_PHB_CAPI_MODE_DMA = 4, 1107 OPAL_PHB_CAPI_MODE_DMA_TVT1 = 5, 1108 }; 1109 1110 /* CAPI feature flags (in device-tree) */ 1111 #define OPAL_PHB_CAPI_FLAG_SNOOP_CONTROL 0x00000001 1112 #define OPAL_PHB_CAPI_FLAG_REVERT_TO_PCIE 0x00000002 1113 1114 /* OPAL I2C request */ 1115 struct opal_i2c_request { 1116 uint8_t type; 1117 #define OPAL_I2C_RAW_READ 0 1118 #define OPAL_I2C_RAW_WRITE 1 1119 #define OPAL_I2C_SM_READ 2 1120 #define OPAL_I2C_SM_WRITE 3 1121 uint8_t flags; 1122 #define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */ 1123 uint8_t subaddr_sz; /* Max 4 */ 1124 uint8_t reserved; 1125 __be16 addr; /* 7 or 10 bit address */ 1126 __be16 reserved2; 1127 __be32 subaddr; /* Sub-address if any */ 1128 __be32 size; /* Data size */ 1129 __be64 buffer_ra; /* Buffer real address */ 1130 }; 1131 1132 /* Argument to OPAL_CEC_REBOOT2() */ 1133 enum { 1134 OPAL_REBOOT_NORMAL = 0, 1135 OPAL_REBOOT_PLATFORM_ERROR, 1136 OPAL_REBOOT_FULL_IPL, 1137 }; 1138 1139 /* Argument to OPAL_PCI_TCE_KILL */ 1140 enum { 1141 OPAL_PCI_TCE_KILL_PAGES, 1142 OPAL_PCI_TCE_KILL_PE, 1143 OPAL_PCI_TCE_KILL_ALL, 1144 }; 1145 1146 /* The xive operation mode indicates the active "API" and 1147 * corresponds to the "mode" parameter of the opal_xive_reset() 1148 * call 1149 */ 1150 enum { 1151 OPAL_XIVE_MODE_EMU = 0, 1152 OPAL_XIVE_MODE_EXPL = 1, 1153 }; 1154 1155 /* Flags for OPAL_XIVE_GET_IRQ_INFO */ 1156 enum { 1157 OPAL_XIVE_IRQ_TRIGGER_PAGE = 0x00000001, 1158 OPAL_XIVE_IRQ_STORE_EOI = 0x00000002, 1159 OPAL_XIVE_IRQ_LSI = 0x00000004, 1160 OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, 1161 OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010, 1162 OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020, 1163 }; 1164 1165 /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */ 1166 enum { 1167 OPAL_XIVE_EQ_ENABLED = 0x00000001, 1168 OPAL_XIVE_EQ_ALWAYS_NOTIFY = 0x00000002, 1169 OPAL_XIVE_EQ_ESCALATE = 0x00000004, 1170 }; 1171 1172 /* Flags for OPAL_XIVE_GET/SET_VP_INFO */ 1173 enum { 1174 OPAL_XIVE_VP_ENABLED = 0x00000001, 1175 OPAL_XIVE_VP_SINGLE_ESCALATION = 0x00000002, 1176 }; 1177 1178 /* "Any chip" replacement for chip ID for allocation functions */ 1179 enum { 1180 OPAL_XIVE_ANY_CHIP = 0xffffffff, 1181 }; 1182 1183 /* Xive sync options */ 1184 enum { 1185 /* This bits are cumulative, arg is a girq */ 1186 XIVE_SYNC_EAS = 0x00000001, /* Sync irq source */ 1187 XIVE_SYNC_QUEUE = 0x00000002, /* Sync irq target */ 1188 }; 1189 1190 /* Dump options */ 1191 enum { 1192 XIVE_DUMP_TM_HYP = 0, 1193 XIVE_DUMP_TM_POOL = 1, 1194 XIVE_DUMP_TM_OS = 2, 1195 XIVE_DUMP_TM_USER = 3, 1196 XIVE_DUMP_VP = 4, 1197 XIVE_DUMP_EMU_STATE = 5, 1198 }; 1199 1200 /* "type" argument options for OPAL_IMC_COUNTERS_* calls */ 1201 enum { 1202 OPAL_IMC_COUNTERS_NEST = 1, 1203 OPAL_IMC_COUNTERS_CORE = 2, 1204 OPAL_IMC_COUNTERS_TRACE = 3, 1205 }; 1206 1207 1208 /* PCI p2p descriptor */ 1209 #define OPAL_PCI_P2P_ENABLE 0x1 1210 #define OPAL_PCI_P2P_LOAD 0x2 1211 #define OPAL_PCI_P2P_STORE 0x4 1212 1213 enum { 1214 OPAL_PCI_P2P_INITIATOR = 0, 1215 OPAL_PCI_P2P_TARGET = 1, 1216 }; 1217 1218 #endif /* __ASSEMBLY__ */ 1219 1220 #endif /* __OPAL_API_H */ 1221