1 /*
2 *
3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #ifndef __ASM_ARCH_MX31_REGS_H
25 #define __ASM_ARCH_MX31_REGS_H
26
27 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
28 #include <asm/types.h>
29
30 /* Clock control module registers */
31 struct clock_control_regs {
32 u32 ccmr;
33 u32 pdr0;
34 u32 pdr1;
35 u32 rcsr;
36 u32 mpctl;
37 u32 upctl;
38 u32 spctl;
39 u32 cosr;
40 u32 cgr0;
41 u32 cgr1;
42 u32 cgr2;
43 u32 wimr0;
44 u32 ldc;
45 u32 dcvr0;
46 u32 dcvr1;
47 u32 dcvr2;
48 u32 dcvr3;
49 u32 ltr0;
50 u32 ltr1;
51 u32 ltr2;
52 u32 ltr3;
53 u32 ltbr0;
54 u32 ltbr1;
trim_begin(const Sequence & seq)55 u32 pmcr0;
56 u32 pmcr1;
57 u32 pdr2;
58 };
59
60 /* Bit definitions for RCSR register in CCM */
61 #define CCM_RCSR_NF16B (1 << 31)
62 #define CCM_RCSR_NFMS (1 << 30)
63
64 #endif
65
66 #define __REG(x) (*((volatile u32 *)(x)))
67 #define __REG16(x) (*((volatile u16 *)(x)))
trim_end(const Sequence & seq)68 #define __REG8(x) (*((volatile u8 *)(x)))
69
70 #define CCM_BASE 0x53f80000
71 #define CCM_CCMR (CCM_BASE + 0x00)
72 #define CCM_PDR0 (CCM_BASE + 0x04)
73 #define CCM_PDR1 (CCM_BASE + 0x08)
74 #define CCM_RCSR (CCM_BASE + 0x0c)
75 #define CCM_MPCTL (CCM_BASE + 0x10)
76 #define CCM_UPCTL (CCM_BASE + 0x14)
77 #define CCM_SPCTL (CCM_BASE + 0x18)
78 #define CCM_COSR (CCM_BASE + 0x1C)
79 #define CCM_CGR0 (CCM_BASE + 0x20)
80 #define CCM_CGR1 (CCM_BASE + 0x24)
81 #define CCM_CGR2 (CCM_BASE + 0x28)
82
83 #define CCMR_MDS (1 << 7)
84 #define CCMR_SBYCS (1 << 4)
85 #define CCMR_MPE (1 << 3)
86 #define CCMR_PRCS_MASK (3 << 1)
87 #define CCMR_FPM (1 << 1)
88 #define CCMR_CKIH (2 << 1)
89
90 #define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
91 #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
92 #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
93 #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
94 #define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
95 #define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
96 #define PDR0_MCU_PODF(x) ((x) & 0x7)
97
98 #define PLL_PD(x) (((x) & 0xf) << 26)
99 #define PLL_MFD(x) (((x) & 0x3ff) << 16)
100 #define PLL_MFI(x) (((x) & 0xf) << 10)
101 #define PLL_MFN(x) (((x) & 0x3ff) << 0)
102
103 #define WEIM_ESDCTL0 0xB8001000
104 #define WEIM_ESDCFG0 0xB8001004
105 #define WEIM_ESDCTL1 0xB8001008
106 #define WEIM_ESDCFG1 0xB800100C
107 #define WEIM_ESDMISC 0xB8001010
108
109 #define ESDCTL_SDE (1 << 31)
110 #define ESDCTL_CMD_RW (0 << 28)
111 #define ESDCTL_CMD_PRECHARGE (1 << 28)
112 #define ESDCTL_CMD_AUTOREFRESH (2 << 28)
113 #define ESDCTL_CMD_LOADMODEREG (3 << 28)
114 #define ESDCTL_CMD_MANUALREFRESH (4 << 28)
115 #define ESDCTL_ROW_13 (2 << 24)
116 #define ESDCTL_ROW(x) ((x) << 24)
117 #define ESDCTL_COL_9 (1 << 20)
118 #define ESDCTL_COL(x) ((x) << 20)
119 #define ESDCTL_DSIZ(x) ((x) << 16)
120 #define ESDCTL_SREFR(x) ((x) << 13)
121 #define ESDCTL_PWDT(x) ((x) << 10)
122 #define ESDCTL_FP(x) ((x) << 8)
123 #define ESDCTL_BL(x) ((x) << 7)
124 #define ESDCTL_PRCT(x) ((x) << 0)
125
126 #define WEIM_BASE 0xb8002000
127 #define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
128 #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
129 #define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
130
131 #define IOMUXC_BASE 0x43FAC000
132 #define IOMUXC_GPR (IOMUXC_BASE + 0x8)
133 #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
134 #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
135
136 #define IPU_BASE 0x53fc0000
137 #define IPU_CONF IPU_BASE
138
139 #define IPU_CONF_PXL_ENDIAN (1<<8)
140 #define IPU_CONF_DU_EN (1<<7)
141 #define IPU_CONF_DI_EN (1<<6)
142 #define IPU_CONF_ADC_EN (1<<5)
143 #define IPU_CONF_SDC_EN (1<<4)
144 #define IPU_CONF_PF_EN (1<<3)
145 #define IPU_CONF_ROT_EN (1<<2)
146 #define IPU_CONF_IC_EN (1<<1)
147 #define IPU_CONF_SCI_EN (1<<0)
148
149 #define ARM_PPMRR 0x40000015
150
151 #define WDOG_BASE 0x53FDC000
152
153 /*
154 * GPIO
155 */
156 #define GPIO1_BASE 0x53FCC000
157 #define GPIO2_BASE 0x53FD0000
158 #define GPIO3_BASE 0x53FA4000
159 #define GPIO_DR 0x00000000 /* data register */
160 #define GPIO_GDIR 0x00000004 /* direction register */
161 #define GPIO_PSR 0x00000008 /* pad status register */
162
163 /*
164 * Signal Multiplexing (IOMUX)
165 */
166
167 /* bits in the SW_MUX_CTL registers */
168 #define MUX_CTL_OUT_GPIO_DR (0 << 4)
169 #define MUX_CTL_OUT_FUNC (1 << 4)
170 #define MUX_CTL_OUT_ALT1 (2 << 4)
171 #define MUX_CTL_OUT_ALT2 (3 << 4)
172 #define MUX_CTL_OUT_ALT3 (4 << 4)
173 #define MUX_CTL_OUT_ALT4 (5 << 4)
174 #define MUX_CTL_OUT_ALT5 (6 << 4)
175 #define MUX_CTL_OUT_ALT6 (7 << 4)
176 #define MUX_CTL_IN_NONE (0 << 0)
177 #define MUX_CTL_IN_GPIO (1 << 0)
178 #define MUX_CTL_IN_FUNC (2 << 0)
179 #define MUX_CTL_IN_ALT1 (4 << 0)
180 #define MUX_CTL_IN_ALT2 (8 << 0)
181
182 #define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
183 #define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
184 #define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
185 #define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
186
187 /* Register offsets based on IOMUXC_BASE */
188 /* 0x00 .. 0x7b */
189 #define MUX_CTL_RTS1 0x7c
190 #define MUX_CTL_CTS1 0x7d
191 #define MUX_CTL_DTR_DCE1 0x7e
192 #define MUX_CTL_DSR_DCE1 0x7f
193 #define MUX_CTL_CSPI2_SCLK 0x80
194 #define MUX_CTL_CSPI2_SPI_RDY 0x81
195 #define MUX_CTL_RXD1 0x82
196 #define MUX_CTL_TXD1 0x83
197 #define MUX_CTL_CSPI2_MISO 0x84
198 #define MUX_CTL_CSPI2_SS0 0x85
199 #define MUX_CTL_CSPI2_SS1 0x86
200 #define MUX_CTL_CSPI2_SS2 0x87
201 #define MUX_CTL_CSPI1_SS2 0x88
202 #define MUX_CTL_CSPI1_SCLK 0x89
203 #define MUX_CTL_CSPI1_SPI_RDY 0x8a
204 #define MUX_CTL_CSPI2_MOSI 0x8b
205 #define MUX_CTL_CSPI1_MOSI 0x8c
206 #define MUX_CTL_CSPI1_MISO 0x8d
207 #define MUX_CTL_CSPI1_SS0 0x8e
208 #define MUX_CTL_CSPI1_SS1 0x8f
209
210 #define MUX_CTL_NFC_WP 0xD0
211 #define MUX_CTL_NFC_CE 0xD1
212 #define MUX_CTL_NFC_RB 0xD2
213 #define MUX_CTL_NFC_WE 0xD4
214 #define MUX_CTL_NFC_RE 0xD5
215 #define MUX_CTL_NFC_ALE 0xD6
216 #define MUX_CTL_NFC_CLE 0xD7
217
218
219 /*
220 * Helper macros for the MUX_[contact name]__[pin function] macros
221 */
222 #define IOMUX_MODE_POS 9
223 #define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
224
225 /*
226 * These macros can be used in mx31_gpio_mux() and have the form
227 * MUX_[contact name]__[pin function]
228 */
229 #define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
230 #define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
231 #define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
232 #define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
233
234 #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
235 #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
236 #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
237 #define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
238 #define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
239 #define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
240 IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
241 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
242
243 #define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
244 #define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
245 #define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
246 #define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
247 #define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
248 #define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
249 IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
250 #define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
251
252 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
253 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
254
255 /* PAD control registers for SDR/DDR */
256 #define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
257 #define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)
258 #define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)
259 #define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)
260 #define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)
261 #define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)
262 #define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)
263 #define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288)
264 #define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C)
265 #define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290)
266 #define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294)
267 #define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298)
268 #define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C)
269 #define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0)
270 #define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4)
271 #define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8)
272 #define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC)
273 #define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0)
274 #define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4)
275 #define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8)
276 #define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC)
277 #define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0)
278 #define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4)
279 #define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8)
280 #define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC)
281 #define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0)
282 #define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4)
283 #define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8)
284 #define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC)
285
286 /*
287 * Memory regions and CS
288 */
289 #define IPU_MEM_BASE 0x70000000
290 #define CSD0_BASE 0x80000000
291 #define CSD1_BASE 0x90000000
292 #define CS0_BASE 0xA0000000
293 #define CS1_BASE 0xA8000000
294 #define CS2_BASE 0xB0000000
295 #define CS3_BASE 0xB2000000
296 #define CS4_BASE 0xB4000000
297 #define CS4_PSRAM_BASE 0xB5000000
298 #define CS5_BASE 0xB6000000
299 #define PCMCIA_MEM_BASE 0xC0000000
300
301 /*
302 * NAND controller
303 */
304 #define NFC_BASE_ADDR 0xB8000000
305
306 /*
307 * Internal RAM (16KB)
308 */
309 #define IRAM_BASE_ADDR 0x1FFFC000
310 #define IRAM_SIZE (16 * 1024)
311
312 #endif /* __ASM_ARCH_MX31_REGS_H */
313