1 /*
2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * This source code is dual-licensed. You may use it under the terms of the
26 * GNU General Public License version 2, or under the license below.
27 *
28 * This source code has been made available to you by IBM on an AS-IS
29 * basis. Anyone receiving this source is licensed under IBM
30 * copyrights to use it in any way he or she deems fit, including
31 * copying it, modifying it, compiling it, and redistributing it either
32 * with or without modifications. No license under IBM patents or
33 * patent applications is to be implied by the copyright license.
34 *
35 * Any user of this software should understand that IBM cannot provide
36 * technical support for this software and will not be responsible for
37 * any consequences resulting from the use of this software.
38 *
39 * Any person who transfers this source code or any derivative work
40 * must include the IBM copyright notice, this paragraph, and the
41 * preceding two paragraphs in the transferred software.
42 *
43 * COPYRIGHT I B M CORPORATION 1995
44 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
45 */
46
47 #include <common.h>
48 #include <commproc.h>
49 #include <asm/processor.h>
50 #include <asm/io.h>
51 #include <watchdog.h>
52 #include <ppc4xx.h>
53
54 #ifdef CONFIG_SERIAL_MULTI
55 #include <serial.h>
56 #endif
57
58 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
59 #include <malloc.h>
60 #endif
61
62 DECLARE_GLOBAL_DATA_PTR;
63
64 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
65 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
66 defined(CONFIG_405EX) || defined(CONFIG_440)
67
68 #if defined(CONFIG_440)
69 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
70 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
71 defined(CONFIG_460EX) || defined(CONFIG_460GT)
72 #define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
73 #define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400)
74 #else
75 #define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000200)
76 #define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
77 #endif
78
79 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
80 #define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
81 #endif
82
83 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
84 #define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500)
85 #define UART3_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
86 #endif
87
88 #if defined(CONFIG_440GP)
89 #define CR0_MASK 0x3fff0000
90 #define CR0_EXTCLK_ENA 0x00600000
91 #define CR0_UDIV_POS 16
92 #define UDIV_SUBTRACT 1
93 #define UART0_SDR CPC0_CR0
94 #define MFREG(a, d) d = mfdcr(a)
95 #define MTREG(a, d) mtdcr(a, d)
96 #else /* #if defined(CONFIG_440GP) */
97 /* all other 440 PPC's access clock divider via sdr register */
98 #define CR0_MASK 0xdfffffff
99 #define CR0_EXTCLK_ENA 0x00800000
100 #define CR0_UDIV_POS 0
101 #define UDIV_SUBTRACT 0
102 #define UART0_SDR SDR0_UART0
103 #define UART1_SDR SDR0_UART1
104 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
105 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
106 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
107 defined(CONFIG_460EX) || defined(CONFIG_460GT)
108 #define UART2_SDR SDR0_UART2
109 #endif
110 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
111 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
112 defined(CONFIG_460EX) || defined(CONFIG_460GT)
113 #define UART3_SDR SDR0_UART3
114 #endif
115 #define MFREG(a, d) mfsdr(a, d)
116 #define MTREG(a, d) mtsdr(a, d)
117 #endif /* #if defined(CONFIG_440GP) */
118 #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
119 #define UART0_BASE 0xef600300
120 #define UART1_BASE 0xef600400
121 #define UCR0_MASK 0x0000007f
122 #define UCR1_MASK 0x00007f00
123 #define UCR0_UDIV_POS 0
124 #define UCR1_UDIV_POS 8
125 #define UDIV_MAX 127
126 #elif defined(CONFIG_405EX)
127 #define UART0_BASE 0xef600200
128 #define UART1_BASE 0xef600300
129 #define CR0_MASK 0x000000ff
130 #define CR0_EXTCLK_ENA 0x00800000
131 #define CR0_UDIV_POS 0
132 #define UDIV_SUBTRACT 0
133 #define UART0_SDR SDR0_UART0
134 #define UART1_SDR SDR0_UART1
135 #else /* CONFIG_405GP || CONFIG_405CR */
136 #define UART0_BASE 0xef600300
137 #define UART1_BASE 0xef600400
138 #define CR0_MASK 0x00001fff
139 #define CR0_EXTCLK_ENA 0x000000c0
140 #define CR0_UDIV_POS 1
141 #define UDIV_MAX 32
142 #endif
143
144 /* using serial port 0 or 1 as U-Boot console ? */
145 #if defined(CONFIG_UART1_CONSOLE)
146 #define ACTING_UART0_BASE UART1_BASE
147 #define ACTING_UART1_BASE UART0_BASE
148 #else
149 #define ACTING_UART0_BASE UART0_BASE
150 #define ACTING_UART1_BASE UART1_BASE
151 #endif
152
153 #if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
154 #error "External serial clock not supported on AMCC PPC405EP!"
155 #endif
156
157 #define UART_RBR 0x00
158 #define UART_THR 0x00
159 #define UART_IER 0x01
160 #define UART_IIR 0x02
161 #define UART_FCR 0x02
162 #define UART_LCR 0x03
163 #define UART_MCR 0x04
164 #define UART_LSR 0x05
165 #define UART_MSR 0x06
166 #define UART_SCR 0x07
167 #define UART_DLL 0x00
168 #define UART_DLM 0x01
169
170 /*-----------------------------------------------------------------------------+
171 | Line Status Register.
172 +-----------------------------------------------------------------------------*/
173 #define asyncLSRDataReady1 0x01
174 #define asyncLSROverrunError1 0x02
175 #define asyncLSRParityError1 0x04
176 #define asyncLSRFramingError1 0x08
177 #define asyncLSRBreakInterrupt1 0x10
178 #define asyncLSRTxHoldEmpty1 0x20
179 #define asyncLSRTxShiftEmpty1 0x40
180 #define asyncLSRRxFifoError1 0x80
181
182 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
183 /*-----------------------------------------------------------------------------+
184 | Fifo
185 +-----------------------------------------------------------------------------*/
186 typedef struct {
187 char *rx_buffer;
188 ulong rx_put;
189 ulong rx_get;
190 } serial_buffer_t;
191
192 volatile static serial_buffer_t buf_info;
193 #endif
194
serial_init_common(u32 base,u32 udiv,u16 bdiv)195 static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
196 {
197 PPC4xx_SYS_INFO sys_info;
198 u8 val;
199
200 get_sys_info(&sys_info);
201
202 /* Correct UART frequency in bd-info struct now that
203 * the UART divisor is available
204 */
205 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
206 gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
207 #else
208 gd->uart_clk = sys_info.freqUART / udiv;
209 #endif
210
211 out_8((u8 *)base + UART_LCR, 0x80); /* set DLAB bit */
212 out_8((u8 *)base + UART_DLL, bdiv); /* set baudrate divisor */
213 out_8((u8 *)base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
214 out_8((u8 *)base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
215 out_8((u8 *)base + UART_FCR, 0x00); /* disable FIFO */
216 out_8((u8 *)base + UART_MCR, 0x00); /* no modem control DTR RTS */
217 val = in_8((u8 *)base + UART_LSR); /* clear line status */
218 val = in_8((u8 *)base + UART_RBR); /* read receive buffer */
219 out_8((u8 *)base + UART_SCR, 0x00); /* set scratchpad */
220 out_8((u8 *)base + UART_IER, 0x00); /* set interrupt enable reg */
221 }
222
223 #if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \
224 !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
serial_divs(int baudrate,unsigned long * pudiv,unsigned short * pbdiv)225 static void serial_divs (int baudrate, unsigned long *pudiv,
226 unsigned short *pbdiv)
227 {
228 sys_info_t sysinfo;
229 unsigned long div; /* total divisor udiv * bdiv */
230 unsigned long umin; /* minimum udiv */
231 unsigned short diff; /* smallest diff */
232 unsigned long udiv; /* best udiv */
233 unsigned short idiff; /* current diff */
234 unsigned short ibdiv; /* current bdiv */
235 unsigned long i;
236 unsigned long est; /* current estimate */
237
238 get_sys_info(&sysinfo);
239
240 udiv = 32; /* Assume lowest possible serial clk */
241 div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
242 umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
243 diff = 32; /* highest possible */
244
245 /* i is the test udiv value -- start with the largest
246 * possible (32) to minimize serial clock and constrain
247 * search to umin.
248 */
249 for (i = 32; i > umin; i--) {
250 ibdiv = div / i;
251 est = i * ibdiv;
252 idiff = (est > div) ? (est-div) : (div-est);
253 if (idiff == 0) {
254 udiv = i;
255 break; /* can't do better */
256 } else if (idiff < diff) {
257 udiv = i; /* best so far */
258 diff = idiff; /* update lowest diff*/
259 }
260 }
261
262 *pudiv = udiv;
263 *pbdiv = div / udiv;
264 }
265
266 #elif defined(CONFIG_405EZ)
267
serial_divs(int baudrate,unsigned long * pudiv,unsigned short * pbdiv)268 static void serial_divs (int baudrate, unsigned long *pudiv,
269 unsigned short *pbdiv)
270 {
271 sys_info_t sysinfo;
272 unsigned long div; /* total divisor udiv * bdiv */
273 unsigned long umin; /* minimum udiv */
274 unsigned short diff; /* smallest diff */
275 unsigned long udiv; /* best udiv */
276 unsigned short idiff; /* current diff */
277 unsigned short ibdiv; /* current bdiv */
278 unsigned long i;
279 unsigned long est; /* current estimate */
280 unsigned long plloutb;
281 unsigned long cpr_pllc;
282 u32 reg;
283
284 /* check the pll feedback source */
285 mfcpr(CPR0_PLLC, cpr_pllc);
286
287 get_sys_info(&sysinfo);
288
289 plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
290 sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
291 sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
292 udiv = 256; /* Assume lowest possible serial clk */
293 div = plloutb / (16 * baudrate); /* total divisor */
294 umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
295 diff = 256; /* highest possible */
296
297 /* i is the test udiv value -- start with the largest
298 * possible (256) to minimize serial clock and constrain
299 * search to umin.
300 */
301 for (i = 256; i > umin; i--) {
302 ibdiv = div / i;
303 est = i * ibdiv;
304 idiff = (est > div) ? (est-div) : (div-est);
305 if (idiff == 0) {
306 udiv = i;
307 break; /* can't do better */
308 } else if (idiff < diff) {
309 udiv = i; /* best so far */
310 diff = idiff; /* update lowest diff*/
311 }
312 }
313
314 *pudiv = udiv;
315 mfcpr(CPC0_PERD0, reg);
316 reg &= ~0x0000ffff;
317 reg |= ((udiv - 0) << 8) | (udiv - 0);
318 mtcpr(CPC0_PERD0, reg);
319 *pbdiv = div / udiv;
320 }
321 #endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */
322
323 /*
324 * Minimal serial functions needed to use one of the SMC ports
325 * as serial console interface.
326 */
327
328 #if defined(CONFIG_440)
serial_init_dev(unsigned long base)329 int serial_init_dev(unsigned long base)
330 {
331 unsigned long reg;
332 unsigned long udiv;
333 unsigned short bdiv;
334 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
335 unsigned long tmp;
336 #endif
337
338 MFREG(UART0_SDR, reg);
339 reg &= ~CR0_MASK;
340
341 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
342 reg |= CR0_EXTCLK_ENA;
343 udiv = 1;
344 tmp = gd->baudrate * 16;
345 bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
346 #else
347 /* For 440, the cpu clock is on divider chain A, UART on divider
348 * chain B ... so cpu clock is irrelevant. Get the "optimized"
349 * values that are subject to the 1/2 opb clock constraint
350 */
351 serial_divs (gd->baudrate, &udiv, &bdiv);
352 #endif
353
354 reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
355
356 /*
357 * Configure input clock to baudrate generator for all
358 * available serial ports here
359 */
360 MTREG(UART0_SDR, reg);
361 #if defined(UART1_SDR)
362 MTREG(UART1_SDR, reg);
363 #endif
364 #if defined(UART2_SDR)
365 MTREG(UART2_SDR, reg);
366 #endif
367 #if defined(UART3_SDR)
368 MTREG(UART3_SDR, reg);
369 #endif
370
371 serial_init_common(base, udiv, bdiv);
372
373 return (0);
374 }
375
376 #else /* !defined(CONFIG_440) */
377
serial_init_dev(unsigned long base)378 int serial_init_dev (unsigned long base)
379 {
380 unsigned long reg;
381 unsigned long tmp;
382 unsigned long clk;
383 unsigned long udiv;
384 unsigned short bdiv;
385
386 #ifdef CONFIG_405EX
387 clk = tmp = 0;
388 mfsdr(UART0_SDR, reg);
389 reg &= ~CR0_MASK;
390 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
391 reg |= CR0_EXTCLK_ENA;
392 udiv = 1;
393 tmp = gd->baudrate * 16;
394 bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
395 #else
396 serial_divs(gd->baudrate, &udiv, &bdiv);
397 #endif
398 reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
399
400 /*
401 * Configure input clock to baudrate generator for all
402 * available serial ports here
403 */
404 mtsdr(UART0_SDR, reg);
405
406 #if defined(UART1_SDR)
407 mtsdr(UART1_SDR, reg);
408 #endif
409
410 #elif defined(CONFIG_405EZ)
411 serial_divs(gd->baudrate, &udiv, &bdiv);
412 clk = tmp = reg = 0;
413 #else
414 #ifdef CONFIG_405EP
415 reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
416 clk = gd->cpu_clk;
417 tmp = CONFIG_SYS_BASE_BAUD * 16;
418 udiv = (clk + tmp / 2) / tmp;
419 if (udiv > UDIV_MAX) /* max. n bits for udiv */
420 udiv = UDIV_MAX;
421 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
422 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
423 mtdcr (CPC0_UCR, reg);
424 #else /* CONFIG_405EP */
425 reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
426 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
427 clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
428 udiv = 1;
429 reg |= CR0_EXTCLK_ENA;
430 #else
431 clk = gd->cpu_clk;
432 #ifdef CONFIG_SYS_405_UART_ERRATA_59
433 udiv = 31; /* Errata 59: stuck at 31 */
434 #else
435 tmp = CONFIG_SYS_BASE_BAUD * 16;
436 udiv = (clk + tmp / 2) / tmp;
437 if (udiv > UDIV_MAX) /* max. n bits for udiv */
438 udiv = UDIV_MAX;
439 #endif
440 #endif
441 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
442 mtdcr (CPC0_CR0, reg);
443 #endif /* CONFIG_405EP */
444 tmp = gd->baudrate * udiv * 16;
445 bdiv = (clk + tmp / 2) / tmp;
446 #endif /* CONFIG_405EX */
447
448 serial_init_common(base, udiv, bdiv);
449
450 return (0);
451 }
452
453 #endif /* if defined(CONFIG_440) */
454
serial_setbrg_dev(unsigned long base)455 void serial_setbrg_dev(unsigned long base)
456 {
457 serial_init_dev(base);
458 }
459
serial_putc_dev(unsigned long base,const char c)460 void serial_putc_dev(unsigned long base, const char c)
461 {
462 int i;
463
464 if (c == '\n')
465 serial_putc_dev(base, '\r');
466
467 /* check THRE bit, wait for transmiter available */
468 for (i = 1; i < 3500; i++) {
469 if ((in_8((u8 *)base + UART_LSR) & 0x20) == 0x20)
470 break;
471 udelay (100);
472 }
473
474 out_8((u8 *)base + UART_THR, c); /* put character out */
475 }
476
serial_puts_dev(unsigned long base,const char * s)477 void serial_puts_dev (unsigned long base, const char *s)
478 {
479 while (*s)
480 serial_putc_dev (base, *s++);
481 }
482
serial_getc_dev(unsigned long base)483 int serial_getc_dev (unsigned long base)
484 {
485 unsigned char status = 0;
486
487 while (1) {
488 #if defined(CONFIG_HW_WATCHDOG)
489 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
490 #endif /* CONFIG_HW_WATCHDOG */
491
492 status = in_8((u8 *)base + UART_LSR);
493 if ((status & asyncLSRDataReady1) != 0x0)
494 break;
495
496 if ((status & ( asyncLSRFramingError1 |
497 asyncLSROverrunError1 |
498 asyncLSRParityError1 |
499 asyncLSRBreakInterrupt1 )) != 0) {
500 out_8((u8 *)base + UART_LSR,
501 asyncLSRFramingError1 |
502 asyncLSROverrunError1 |
503 asyncLSRParityError1 |
504 asyncLSRBreakInterrupt1);
505 }
506 }
507
508 return (0x000000ff & (int) in_8((u8 *)base));
509 }
510
serial_tstc_dev(unsigned long base)511 int serial_tstc_dev (unsigned long base)
512 {
513 unsigned char status;
514
515 status = in_8((u8 *)base + UART_LSR);
516 if ((status & asyncLSRDataReady1) != 0x0)
517 return (1);
518
519 if ((status & ( asyncLSRFramingError1 |
520 asyncLSROverrunError1 |
521 asyncLSRParityError1 |
522 asyncLSRBreakInterrupt1 )) != 0) {
523 out_8((u8 *)base + UART_LSR,
524 asyncLSRFramingError1 |
525 asyncLSROverrunError1 |
526 asyncLSRParityError1 |
527 asyncLSRBreakInterrupt1);
528 }
529
530 return 0;
531 }
532
533 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
534
serial_isr(void * arg)535 void serial_isr (void *arg)
536 {
537 int space;
538 int c;
539 const int rx_get = buf_info.rx_get;
540 int rx_put = buf_info.rx_put;
541
542 if (rx_get <= rx_put)
543 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
544 else
545 space = rx_get - rx_put;
546
547 while (serial_tstc_dev (ACTING_UART0_BASE)) {
548 c = serial_getc_dev (ACTING_UART0_BASE);
549 if (space) {
550 buf_info.rx_buffer[rx_put++] = c;
551 space--;
552 }
553 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
554 rx_put = 0;
555 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
556 /* Stop flow by setting RTS inactive */
557 out_8((u8 *)ACTING_UART0_BASE + UART_MCR,
558 in_8((u8 *)ACTING_UART0_BASE + UART_MCR) &
559 (0xFF ^ 0x02));
560 }
561 }
562 buf_info.rx_put = rx_put;
563 }
564
serial_buffered_init(void)565 void serial_buffered_init (void)
566 {
567 serial_puts ("Switching to interrupt driven serial input mode.\n");
568 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
569 buf_info.rx_put = 0;
570 buf_info.rx_get = 0;
571
572 if (in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)
573 serial_puts ("Check CTS signal present on serial port: OK.\n");
574 else
575 serial_puts ("WARNING: CTS signal not present on serial port.\n");
576
577 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
578 serial_isr /*interrupt_handler_t *handler */ ,
579 (void *) &buf_info /*void *arg */ );
580
581 /* Enable "RX Data Available" Interrupt on UART */
582 out_8(ACTING_UART0_BASE + UART_IER, 0x01);
583 /* Set DTR active */
584 out_8(ACTING_UART0_BASE + UART_MCR,
585 in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x01);
586 /* Start flow by setting RTS active */
587 out_8(ACTING_UART0_BASE + UART_MCR,
588 in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
589 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
590 out_8(ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
591 }
592
serial_buffered_putc(const char c)593 void serial_buffered_putc (const char c)
594 {
595 /* Wait for CTS */
596 #if defined(CONFIG_HW_WATCHDOG)
597 while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10))
598 WATCHDOG_RESET ();
599 #else
600 while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10));
601 #endif
602 serial_putc (c);
603 }
604
serial_buffered_puts(const char * s)605 void serial_buffered_puts (const char *s)
606 {
607 serial_puts (s);
608 }
609
serial_buffered_getc(void)610 int serial_buffered_getc (void)
611 {
612 int space;
613 int c;
614 int rx_get = buf_info.rx_get;
615 int rx_put;
616
617 #if defined(CONFIG_HW_WATCHDOG)
618 while (rx_get == buf_info.rx_put)
619 WATCHDOG_RESET ();
620 #else
621 while (rx_get == buf_info.rx_put);
622 #endif
623 c = buf_info.rx_buffer[rx_get++];
624 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
625 rx_get = 0;
626 buf_info.rx_get = rx_get;
627
628 rx_put = buf_info.rx_put;
629 if (rx_get <= rx_put)
630 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
631 else
632 space = rx_get - rx_put;
633
634 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
635 /* Start flow by setting RTS active */
636 out_8(ACTING_UART0_BASE + UART_MCR,
637 in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
638 }
639
640 return c;
641 }
642
serial_buffered_tstc(void)643 int serial_buffered_tstc (void)
644 {
645 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
646 }
647
648 #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
649
650 #if defined(CONFIG_CMD_KGDB)
651 /*
652 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
653 number 0 or number 1
654 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
655 configuration has been already done
656 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
657 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
658 */
659 #if (CONFIG_KGDB_SER_INDEX & 2)
kgdb_serial_init(void)660 void kgdb_serial_init (void)
661 {
662 u8 val;
663 u16 br_reg;
664
665 get_clocks ();
666 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
667 5) / 10;
668 /*
669 * Init onboard 16550 UART
670 */
671 out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
672 out_8((u8 *)ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
673 out_8((u8 *)ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
674 out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
675 out_8((u8 *)ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
676 out_8((u8 *)ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
677 val = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); /* clear line status */
678 val = in_8((u8 *)ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
679 out_8((u8 *)ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
680 out_8((u8 *)ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
681 }
682
putDebugChar(const char c)683 void putDebugChar (const char c)
684 {
685 if (c == '\n')
686 serial_putc ('\r');
687
688 out_8((u8 *)ACTING_UART1_BASE + UART_THR, c); /* put character out */
689
690 /* check THRE bit, wait for transfer done */
691 while ((in_8((u8 *)ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
692 }
693
putDebugStr(const char * s)694 void putDebugStr (const char *s)
695 {
696 while (*s)
697 serial_putc (*s++);
698 }
699
getDebugChar(void)700 int getDebugChar (void)
701 {
702 unsigned char status = 0;
703
704 while (1) {
705 status = in_8((u8 *)ACTING_UART1_BASE + UART_LSR);
706 if ((status & asyncLSRDataReady1) != 0x0)
707 break;
708
709 if ((status & (asyncLSRFramingError1 |
710 asyncLSROverrunError1 |
711 asyncLSRParityError1 |
712 asyncLSRBreakInterrupt1 )) != 0) {
713 out_8((u8 *)ACTING_UART1_BASE + UART_LSR,
714 asyncLSRFramingError1 |
715 asyncLSROverrunError1 |
716 asyncLSRParityError1 |
717 asyncLSRBreakInterrupt1);
718 }
719 }
720
721 return (0x000000ff & (int) in_8((u8 *)ACTING_UART1_BASE));
722 }
723
kgdb_interruptible(int yes)724 void kgdb_interruptible (int yes)
725 {
726 return;
727 }
728
729 #else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
730
kgdb_serial_init(void)731 void kgdb_serial_init (void)
732 {
733 serial_printf ("[on serial] ");
734 }
735
putDebugChar(int c)736 void putDebugChar (int c)
737 {
738 serial_putc (c);
739 }
740
putDebugStr(const char * str)741 void putDebugStr (const char *str)
742 {
743 serial_puts (str);
744 }
745
getDebugChar(void)746 int getDebugChar (void)
747 {
748 return serial_getc ();
749 }
750
kgdb_interruptible(int yes)751 void kgdb_interruptible (int yes)
752 {
753 return;
754 }
755 #endif /* (CONFIG_KGDB_SER_INDEX & 2) */
756 #endif
757
758
759 #if defined(CONFIG_SERIAL_MULTI)
serial0_init(void)760 int serial0_init(void)
761 {
762 return (serial_init_dev(UART0_BASE));
763 }
764
serial1_init(void)765 int serial1_init(void)
766 {
767 return (serial_init_dev(UART1_BASE));
768 }
769
serial0_setbrg(void)770 void serial0_setbrg (void)
771 {
772 serial_setbrg_dev(UART0_BASE);
773 }
774
serial1_setbrg(void)775 void serial1_setbrg (void)
776 {
777 serial_setbrg_dev(UART1_BASE);
778 }
779
serial0_putc(const char c)780 void serial0_putc(const char c)
781 {
782 serial_putc_dev(UART0_BASE,c);
783 }
784
serial1_putc(const char c)785 void serial1_putc(const char c)
786 {
787 serial_putc_dev(UART1_BASE, c);
788 }
789
serial0_puts(const char * s)790 void serial0_puts(const char *s)
791 {
792 serial_puts_dev(UART0_BASE, s);
793 }
794
serial1_puts(const char * s)795 void serial1_puts(const char *s)
796 {
797 serial_puts_dev(UART1_BASE, s);
798 }
799
serial0_getc(void)800 int serial0_getc(void)
801 {
802 return(serial_getc_dev(UART0_BASE));
803 }
804
serial1_getc(void)805 int serial1_getc(void)
806 {
807 return(serial_getc_dev(UART1_BASE));
808 }
809
serial0_tstc(void)810 int serial0_tstc(void)
811 {
812 return (serial_tstc_dev(UART0_BASE));
813 }
814
serial1_tstc(void)815 int serial1_tstc(void)
816 {
817 return (serial_tstc_dev(UART1_BASE));
818 }
819
820 struct serial_device serial0_device =
821 {
822 "serial0",
823 "UART0",
824 serial0_init,
825 NULL,
826 serial0_setbrg,
827 serial0_getc,
828 serial0_tstc,
829 serial0_putc,
830 serial0_puts,
831 };
832
833 struct serial_device serial1_device =
834 {
835 "serial1",
836 "UART1",
837 serial1_init,
838 NULL,
839 serial1_setbrg,
840 serial1_getc,
841 serial1_tstc,
842 serial1_putc,
843 serial1_puts,
844 };
845 #else
846 /*
847 * Wrapper functions
848 */
serial_init(void)849 int serial_init(void)
850 {
851 return serial_init_dev(ACTING_UART0_BASE);
852 }
853
serial_setbrg(void)854 void serial_setbrg(void)
855 {
856 serial_setbrg_dev(ACTING_UART0_BASE);
857 }
858
serial_putc(const char c)859 void serial_putc(const char c)
860 {
861 serial_putc_dev(ACTING_UART0_BASE, c);
862 }
863
serial_puts(const char * s)864 void serial_puts(const char *s)
865 {
866 serial_puts_dev(ACTING_UART0_BASE, s);
867 }
868
serial_getc(void)869 int serial_getc(void)
870 {
871 return serial_getc_dev(ACTING_UART0_BASE);
872 }
873
serial_tstc(void)874 int serial_tstc(void)
875 {
876 return serial_tstc_dev(ACTING_UART0_BASE);
877 }
878 #endif /* CONFIG_SERIAL_MULTI */
879
880 #endif /* CONFIG_405GP || CONFIG_405CR */
881