1 /* 2 * (C) Copyright 2001-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * board/config.h - configuration options, board specific 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ 37 #define CONFIG_CPU87 1 /* ...on a CPU87 board */ 38 #define CONFIG_PCI 39 #define CONFIG_CPM2 1 /* Has a CPM2 */ 40 41 /* 42 * select serial console configuration 43 * 44 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 46 * for SCC). 47 * 48 * if CONFIG_CONS_NONE is defined, then the serial console routines must 49 * defined elsewhere (for example, on the cogent platform, there are serial 50 * ports on the motherboard which are used for the serial console - see 51 * cogent/cma101/serial.[ch]). 52 */ 53 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ 54 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 55 #undef CONFIG_CONS_NONE /* define if console on something else*/ 56 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 57 58 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) 59 #define CONFIG_BAUDRATE 230400 60 #else 61 #define CONFIG_BAUDRATE 9600 62 #endif 63 64 /* 65 * select ethernet configuration 66 * 67 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 68 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 69 * for FCC) 70 * 71 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 72 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 73 */ 74 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 75 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 76 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 77 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ 78 79 #define CONFIG_HAS_ETH1 1 80 #define CONFIG_HAS_ETH2 1 81 82 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) 83 84 /* 85 * - Rx-CLK is CLK11 86 * - Tx-CLK is CLK12 87 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 88 * - Enable Full Duplex in FSMR 89 */ 90 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) 91 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) 92 # define CONFIG_SYS_CPMFCR_RAMTYPE 0 93 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 94 95 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) 96 97 /* 98 * - Rx-CLK is CLK13 99 * - Tx-CLK is CLK14 100 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 101 * - Enable Full Duplex in FSMR 102 */ 103 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) 104 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) 105 # define CONFIG_SYS_CPMFCR_RAMTYPE 0 106 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 107 108 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ 109 110 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ 111 #define CONFIG_8260_CLKIN 100000000 /* in Hz */ 112 113 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 114 115 #define CONFIG_PREBOOT \ 116 "echo; " \ 117 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \ 118 "echo" 119 120 #undef CONFIG_BOOTARGS 121 #define CONFIG_BOOTCOMMAND \ 122 "bootp; " \ 123 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 124 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 125 "bootm" 126 127 /*----------------------------------------------------------------------- 128 * I2C/EEPROM/RTC configuration 129 */ 130 #define CONFIG_SOFT_I2C /* Software I2C support enabled */ 131 132 # define CONFIG_SYS_I2C_SPEED 50000 133 # define CONFIG_SYS_I2C_SLAVE 0xFE 134 /* 135 * Software (bit-bang) I2C driver configuration 136 */ 137 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 138 #define I2C_ACTIVE (iop->pdir |= 0x00010000) 139 #define I2C_TRISTATE (iop->pdir &= ~0x00010000) 140 #define I2C_READ ((iop->pdat & 0x00010000) != 0) 141 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ 142 else iop->pdat &= ~0x00010000 143 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ 144 else iop->pdat &= ~0x00020000 145 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 146 147 #define CONFIG_RTC_PCF8563 148 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 149 150 #undef CONFIG_WATCHDOG /* watchdog disabled */ 151 152 /*----------------------------------------------------------------------- 153 * Disk-On-Chip configuration 154 */ 155 156 #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ 157 158 #define CONFIG_SYS_DOC_SUPPORT_2000 159 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 160 161 /*----------------------------------------------------------------------- 162 * Miscellaneous configuration options 163 */ 164 165 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 166 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 167 168 /* 169 * BOOTP options 170 */ 171 #define CONFIG_BOOTP_SUBNETMASK 172 #define CONFIG_BOOTP_GATEWAY 173 #define CONFIG_BOOTP_HOSTNAME 174 #define CONFIG_BOOTP_BOOTPATH 175 #define CONFIG_BOOTP_BOOTFILESIZE 176 177 178 /* 179 * Command line configuration. 180 */ 181 #include <config_cmd_default.h> 182 183 #define CONFIG_CMD_BEDBUG 184 #define CONFIG_CMD_DATE 185 #define CONFIG_CMD_EEPROM 186 #define CONFIG_CMD_I2C 187 188 #ifdef CONFIG_PCI 189 #define CONFIG_CMD_PCI 190 #endif 191 192 /* 193 * Miscellaneous configurable options 194 */ 195 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 196 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 197 #if defined(CONFIG_CMD_KGDB) 198 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 199 #else 200 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 201 #endif 202 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 203 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 204 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 205 206 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 207 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 208 209 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 210 211 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 212 213 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 214 215 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */ 216 217 #define CONFIG_LOOPW 218 219 /* 220 * For booting Linux, the board info and command line data 221 * have to be in the first 8 MB of memory, since this is 222 * the maximum mapped by the Linux kernel during initialization. 223 */ 224 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 225 226 /*----------------------------------------------------------------------- 227 * Flash configuration 228 */ 229 230 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000 231 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000 232 #define CONFIG_SYS_FLASH_BASE 0xFF000000 233 #define CONFIG_SYS_FLASH_SIZE 0x00800000 234 235 /*----------------------------------------------------------------------- 236 * FLASH organization 237 */ 238 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ 239 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ 240 241 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 242 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 243 244 /*----------------------------------------------------------------------- 245 * Other areas to be mapped 246 */ 247 248 /* CS3: Dual ported SRAM */ 249 #define CONFIG_SYS_DPSRAM_BASE 0x40000000 250 #define CONFIG_SYS_DPSRAM_SIZE 0x00100000 251 252 /* CS4: DiskOnChip */ 253 #define CONFIG_SYS_DOC_BASE 0xF4000000 254 #define CONFIG_SYS_DOC_SIZE 0x00100000 255 256 /* CS5: FDC37C78 controller */ 257 #define CONFIG_SYS_FDC37C78_BASE 0xF1000000 258 #define CONFIG_SYS_FDC37C78_SIZE 0x00100000 259 260 /* CS6: Board configuration registers */ 261 #define CONFIG_SYS_BCRS_BASE 0xF2000000 262 #define CONFIG_SYS_BCRS_SIZE 0x00010000 263 264 /* CS7: VME Extended Access Range */ 265 #define CONFIG_SYS_VMEEAR_BASE 0x60000000 266 #define CONFIG_SYS_VMEEAR_SIZE 0x01000000 267 268 /* CS8: VME Standard Access Range */ 269 #define CONFIG_SYS_VMESAR_BASE 0xFE000000 270 #define CONFIG_SYS_VMESAR_SIZE 0x01000000 271 272 /* CS9: VME Short I/O Access Range */ 273 #define CONFIG_SYS_VMESIOAR_BASE 0xFD000000 274 #define CONFIG_SYS_VMESIOAR_SIZE 0x01000000 275 276 /*----------------------------------------------------------------------- 277 * Hard Reset Configuration Words 278 * 279 * if you change bits in the HRCW, you must also change the CONFIG_SYS_* 280 * defines for the various registers affected by the HRCW e.g. changing 281 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 282 */ 283 #if defined(CONFIG_BOOT_ROM) 284 #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ 285 HRCW_BPS01 | HRCW_CS10PC01) 286 #else 287 #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01) 288 #endif 289 290 /* no slaves so just fill with zeros */ 291 #define CONFIG_SYS_HRCW_SLAVE1 0 292 #define CONFIG_SYS_HRCW_SLAVE2 0 293 #define CONFIG_SYS_HRCW_SLAVE3 0 294 #define CONFIG_SYS_HRCW_SLAVE4 0 295 #define CONFIG_SYS_HRCW_SLAVE5 0 296 #define CONFIG_SYS_HRCW_SLAVE6 0 297 #define CONFIG_SYS_HRCW_SLAVE7 0 298 299 /*----------------------------------------------------------------------- 300 * Internal Memory Mapped Register 301 */ 302 #define CONFIG_SYS_IMMR 0xF0000000 303 304 /*----------------------------------------------------------------------- 305 * Definitions for initial stack pointer and data area (in DPRAM) 306 */ 307 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 308 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ 309 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ 310 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 311 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 312 313 /*----------------------------------------------------------------------- 314 * Start addresses for the final memory configuration 315 * (Set up by the startup code) 316 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 317 * 318 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE. 319 */ 320 #define CONFIG_SYS_SDRAM_BASE 0x00000000 321 #define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ 322 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE 323 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 324 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ 325 326 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 327 # define CONFIG_SYS_RAMBOOT 328 #endif 329 330 #ifdef CONFIG_PCI 331 #define CONFIG_PCI_PNP 332 #define CONFIG_EEPRO100 333 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 334 #endif 335 336 #if 0 337 /* environment is in Flash */ 338 #define CONFIG_ENV_IS_IN_FLASH 1 339 #ifdef CONFIG_BOOT_ROM 340 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x70000) 341 # define CONFIG_ENV_SIZE 0x10000 342 # define CONFIG_ENV_SECT_SIZE 0x10000 343 #endif 344 #else 345 /* environment is in EEPROM */ 346 #define CONFIG_ENV_IS_IN_EEPROM 1 347 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */ 348 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 349 /* mask of address bits that overflow into the "EEPROM chip address" */ 350 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 351 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 352 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 353 #define CONFIG_ENV_OFFSET 512 354 #define CONFIG_ENV_SIZE (2048 - 512) 355 #endif 356 357 /* 358 * Internal Definitions 359 * 360 * Boot Flags 361 */ 362 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ 363 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 364 365 366 /*----------------------------------------------------------------------- 367 * Cache Configuration 368 */ 369 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 370 #if defined(CONFIG_CMD_KGDB) 371 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 372 #endif 373 374 /*----------------------------------------------------------------------- 375 * HIDx - Hardware Implementation-dependent Registers 2-11 376 *----------------------------------------------------------------------- 377 * HID0 also contains cache control - initially enable both caches and 378 * invalidate contents, then the final state leaves only the instruction 379 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 380 * but Soft reset does not. 381 * 382 * HID1 has only read-only information - nothing to set. 383 */ 384 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ 385 HID0_DCI|HID0_IFEM|HID0_ABE) 386 #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) 387 #define CONFIG_SYS_HID2 0 388 389 /*----------------------------------------------------------------------- 390 * RMR - Reset Mode Register 5-5 391 *----------------------------------------------------------------------- 392 * turn on Checkstop Reset Enable 393 */ 394 #define CONFIG_SYS_RMR RMR_CSRE 395 396 /*----------------------------------------------------------------------- 397 * BCR - Bus Configuration 4-25 398 *----------------------------------------------------------------------- 399 */ 400 #define BCR_APD01 0x10000000 401 #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ 402 403 /*----------------------------------------------------------------------- 404 * SIUMCR - SIU Module Configuration 4-31 405 *----------------------------------------------------------------------- 406 */ 407 #define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\ 408 SIUMCR_CS10PC01|SIUMCR_BCTLC10) 409 410 /*----------------------------------------------------------------------- 411 * SYPCR - System Protection Control 4-35 412 * SYPCR can only be written once after reset! 413 *----------------------------------------------------------------------- 414 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 415 */ 416 #if defined(CONFIG_WATCHDOG) 417 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 418 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 419 #else 420 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 421 SYPCR_SWRI|SYPCR_SWP) 422 #endif /* CONFIG_WATCHDOG */ 423 424 /*----------------------------------------------------------------------- 425 * TMCNTSC - Time Counter Status and Control 4-40 426 *----------------------------------------------------------------------- 427 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 428 * and enable Time Counter 429 */ 430 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 431 432 /*----------------------------------------------------------------------- 433 * PISCR - Periodic Interrupt Status and Control 4-42 434 *----------------------------------------------------------------------- 435 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 436 * Periodic timer 437 */ 438 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 439 440 /*----------------------------------------------------------------------- 441 * SCCR - System Clock Control 9-8 442 *----------------------------------------------------------------------- 443 * Ensure DFBRG is Divide by 16 444 */ 445 #define CONFIG_SYS_SCCR SCCR_DFBRG01 446 447 /*----------------------------------------------------------------------- 448 * RCCR - RISC Controller Configuration 13-7 449 *----------------------------------------------------------------------- 450 */ 451 #define CONFIG_SYS_RCCR 0 452 453 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000 454 455 /* 456 * we use the same values for 32 MB, 128 MB and 256 MB SDRAM 457 * refresh rate = 7.68 uS (100 MHz Bus Clock) 458 */ 459 460 /*----------------------------------------------------------------------- 461 * MPTPR - Memory Refresh Timer Prescaler Register 10-18 462 *----------------------------------------------------------------------- 463 */ 464 #define CONFIG_SYS_MPTPR 0x2000 465 466 /*----------------------------------------------------------------------- 467 * PSRT - Refresh Timer Register 10-16 468 *----------------------------------------------------------------------- 469 */ 470 #define CONFIG_SYS_PSRT 0x16 471 472 /*----------------------------------------------------------------------- 473 * PSRT - SDRAM Mode Register 10-10 474 *----------------------------------------------------------------------- 475 */ 476 477 /* SDRAM initialization values for 8-column chips 478 */ 479 #define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ 480 ORxS_BPD_4 |\ 481 ORxS_ROWST_PBI0_A9 |\ 482 ORxS_NUMR_12) 483 484 #define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ 485 PSDMR_BSMA_A14_A16 |\ 486 PSDMR_SDA10_PBI0_A10 |\ 487 PSDMR_RFRC_7_CLK |\ 488 PSDMR_PRETOACT_2W |\ 489 PSDMR_ACTTORW_2W |\ 490 PSDMR_LDOTOPRE_1C |\ 491 PSDMR_WRC_1C |\ 492 PSDMR_CL_2) 493 494 /* SDRAM initialization values for 9-column chips 495 */ 496 #define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ 497 ORxS_BPD_4 |\ 498 ORxS_ROWST_PBI0_A7 |\ 499 ORxS_NUMR_13) 500 501 #define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ 502 PSDMR_BSMA_A13_A15 |\ 503 PSDMR_SDA10_PBI0_A9 |\ 504 PSDMR_RFRC_7_CLK |\ 505 PSDMR_PRETOACT_2W |\ 506 PSDMR_ACTTORW_2W |\ 507 PSDMR_LDOTOPRE_1C |\ 508 PSDMR_WRC_1C |\ 509 PSDMR_CL_2) 510 511 /* SDRAM initialization values for 10-column chips 512 */ 513 #define CONFIG_SYS_OR2_10COL (CONFIG_SYS_MIN_AM_MASK |\ 514 ORxS_BPD_4 |\ 515 ORxS_ROWST_PBI1_A4 |\ 516 ORxS_NUMR_13) 517 518 #define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\ 519 PSDMR_SDAM_A17_IS_A5 |\ 520 PSDMR_BSMA_A13_A15 |\ 521 PSDMR_SDA10_PBI1_A6 |\ 522 PSDMR_RFRC_7_CLK |\ 523 PSDMR_PRETOACT_2W |\ 524 PSDMR_ACTTORW_2W |\ 525 PSDMR_LDOTOPRE_1C |\ 526 PSDMR_WRC_1C |\ 527 PSDMR_CL_2) 528 529 /* 530 * Init Memory Controller: 531 * 532 * Bank Bus Machine PortSz Device 533 * ---- --- ------- ------ ------ 534 * 0 60x GPCM 8 bit Boot ROM 535 * 1 60x GPCM 64 bit FLASH 536 * 2 60x SDRAM 64 bit SDRAM 537 * 538 */ 539 540 #define CONFIG_SYS_MRS_OFFS 0x00000000 541 542 #ifdef CONFIG_BOOT_ROM 543 /* Bank 0 - Boot ROM 544 */ 545 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ 546 BRx_PS_8 |\ 547 BRx_MS_GPCM_P |\ 548 BRx_V) 549 550 #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ 551 ORxG_CSNT |\ 552 ORxG_ACS_DIV1 |\ 553 ORxG_SCY_5_CLK |\ 554 ORxU_EHTR_8IDLE) 555 556 /* Bank 1 - FLASH 557 */ 558 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 559 BRx_PS_64 |\ 560 BRx_MS_GPCM_P |\ 561 BRx_V) 562 563 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 564 ORxG_CSNT |\ 565 ORxG_ACS_DIV1 |\ 566 ORxG_SCY_5_CLK |\ 567 ORxU_EHTR_8IDLE) 568 569 #else /* CONFIG_BOOT_ROM */ 570 /* Bank 0 - FLASH 571 */ 572 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 573 BRx_PS_64 |\ 574 BRx_MS_GPCM_P |\ 575 BRx_V) 576 577 #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 578 ORxG_CSNT |\ 579 ORxG_ACS_DIV1 |\ 580 ORxG_SCY_5_CLK |\ 581 ORxU_EHTR_8IDLE) 582 583 /* Bank 1 - Boot ROM 584 */ 585 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ 586 BRx_PS_8 |\ 587 BRx_MS_GPCM_P |\ 588 BRx_V) 589 590 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ 591 ORxG_CSNT |\ 592 ORxG_ACS_DIV1 |\ 593 ORxG_SCY_5_CLK |\ 594 ORxU_EHTR_8IDLE) 595 596 #endif /* CONFIG_BOOT_ROM */ 597 598 599 /* Bank 2 - 60x bus SDRAM 600 */ 601 #ifndef CONFIG_SYS_RAMBOOT 602 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ 603 BRx_PS_64 |\ 604 BRx_MS_SDRAM_P |\ 605 BRx_V) 606 607 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL 608 609 #define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL 610 #endif /* CONFIG_SYS_RAMBOOT */ 611 612 /* Bank 3 - Dual Ported SRAM 613 */ 614 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\ 615 BRx_PS_16 |\ 616 BRx_MS_GPCM_P |\ 617 BRx_V) 618 619 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE) |\ 620 ORxG_CSNT |\ 621 ORxG_ACS_DIV1 |\ 622 ORxG_SCY_7_CLK |\ 623 ORxG_SETA) 624 625 /* Bank 4 - DiskOnChip 626 */ 627 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ 628 BRx_PS_8 |\ 629 BRx_MS_GPCM_P |\ 630 BRx_V) 631 632 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ 633 ORxG_CSNT |\ 634 ORxG_ACS_DIV2 |\ 635 ORxG_SCY_9_CLK |\ 636 ORxU_EHTR_8IDLE) 637 638 /* Bank 5 - FDC37C78 controller 639 */ 640 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\ 641 BRx_PS_8 |\ 642 BRx_MS_GPCM_P |\ 643 BRx_V) 644 645 #define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE) |\ 646 ORxG_ACS_DIV2 |\ 647 ORxG_SCY_10_CLK |\ 648 ORxU_EHTR_8IDLE) 649 650 /* Bank 6 - Board control registers 651 */ 652 #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK) |\ 653 BRx_PS_8 |\ 654 BRx_MS_GPCM_P |\ 655 BRx_V) 656 657 #define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE) |\ 658 ORxG_CSNT |\ 659 ORxG_SCY_7_CLK) 660 661 /* Bank 7 - VME Extended Access Range 662 */ 663 #define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\ 664 BRx_PS_32 |\ 665 BRx_MS_GPCM_P |\ 666 BRx_V) 667 668 #define CONFIG_SYS_OR7_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE) |\ 669 ORxG_CSNT |\ 670 ORxG_ACS_DIV1 |\ 671 ORxG_SCY_7_CLK |\ 672 ORxG_SETA) 673 674 /* Bank 8 - VME Standard Access Range 675 */ 676 #define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\ 677 BRx_PS_16 |\ 678 BRx_MS_GPCM_P |\ 679 BRx_V) 680 681 #define CONFIG_SYS_OR8_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE) |\ 682 ORxG_CSNT |\ 683 ORxG_ACS_DIV1 |\ 684 ORxG_SCY_7_CLK |\ 685 ORxG_SETA) 686 687 /* Bank 9 - VME Short I/O Access Range 688 */ 689 #define CONFIG_SYS_BR9_PRELIM ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\ 690 BRx_PS_16 |\ 691 BRx_MS_GPCM_P |\ 692 BRx_V) 693 694 #define CONFIG_SYS_OR9_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE) |\ 695 ORxG_CSNT |\ 696 ORxG_ACS_DIV1 |\ 697 ORxG_SCY_7_CLK |\ 698 ORxG_SETA) 699 700 #endif /* __CONFIG_H */ 701