1 /* 2 * (C) Copyright 2008 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 /************************************************************************ 22 * canyonlands.h - configuration for Canyonlands (460EX) 23 ***********************************************************************/ 24 #ifndef __CONFIG_H 25 #define __CONFIG_H 26 27 /*----------------------------------------------------------------------- 28 * High Level Configuration Options 29 *----------------------------------------------------------------------*/ 30 #define CONFIG_CANYONLANDS 31 #define CONFIG_SAM4XX 1 /* board is Sam4xx family */ 32 #define CONFIG_SAM460EX 33 34 #define CONFIG_460EX 1 /* Specific PPC460EX */ 35 #define CONFIG_HOSTNAME Sam460ex 36 37 #define CONFIG_440 1 38 #define CONFIG_4xx 1 /* ... PPC4xx family */ 39 40 #define CONFIG_SYS_CLK_FREQ 50000000 /* external freq to pll */ 41 42 #define CONFIG_BOARD_RESET 1 43 44 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ 45 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of U-Boot */ 46 #define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1) 47 #define CONFIG_SYS_MALLOC_LEN (32 << 20) /* Reserved for malloc */ 48 49 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 50 #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ 51 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ 52 #define CONFIG_BOARD_TYPES 1 /* support board types */ 53 #define CONFIG_LAST_STAGE_INIT 1 54 #define CONFIG_VERY_BIG_RAM 1 55 #define CONFIG_MAX_MEM_MAPPED 256*1024*1024 56 57 /*----------------------------------------------------------------------- 58 * Base addresses -- Note these are effective addresses where the 59 * actual resources get mapped (not physical addresses) 60 *----------------------------------------------------------------------*/ 61 #define CONFIG_SYS_PCI_64BIT 1 62 63 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory region1 */ 64 #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ 65 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE 66 #define CONFIG_SYS_PCI_MEMSIZE 0x20000000 67 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE + 0x10000000 68 69 #define CONFIG_SYS_PCIE_MEMBASE 0xA0000000 /* mapped PCIe memory */ 70 #define CONFIG_SYS_PCIE_MEMSIZE 0x10000000 /* smallest incr for PCIe port */ 71 #define CONFIG_SYS_PCIE_BASE 0xE4000000 /* PCIe UTL regs */ 72 73 #define CONFIG_SYS_PCIE0_CFGBASE 0xE0000000 74 #define CONFIG_SYS_PCIE1_CFGBASE 0xE1000000 75 #define CONFIG_SYS_PCIE0_XCFGBASE 0xE3000000 76 #define CONFIG_SYS_PCIE1_XCFGBASE 0xE3001000 77 78 #define CONFIG_SYS_PCIE_IOBASE 0x0 79 #define CONFIG_SYS_PCIE_IOSIZE 0x10000 80 81 #define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */ 82 83 /* base address of inbound PCIe window */ 84 #define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */ 85 86 /* EBC stuff */ 87 #define CONFIG_SYS_FPGA_BASE 0xFF000000 88 #define CONFIG_SYS_FLASH_BASE 0xFFF00000 /* later mapped to this addr */ 89 #define CONFIG_SYS_FLASH_SIZE (1 << 20) 90 #define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 91 #define CONFIG_SYS_FLASH_BASE_PHYS_L CONFIG_SYS_FLASH_BASE 92 93 #define CONFIG_SYS_BOOT_BASE_ADDR 0xF0000000 /* EBC Boot Space: 0xFF000000 */ 94 95 #define CONFIG_SYS_OCM_BASE 0xE5000000 /* OCM: 64k */ 96 #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ 97 #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 98 99 #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */ 100 101 #define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals */ 102 103 /*----------------------------------------------------------------------- 104 * Initial RAM & stack pointer (placed in OCM) 105 *----------------------------------------------------------------------*/ 106 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ 107 #define CONFIG_SYS_INIT_RAM_END (4 << 10) 108 #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ 109 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 110 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 111 112 /*----------------------------------------------------------------------- 113 * Serial Port 114 *----------------------------------------------------------------------*/ 115 #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ 116 #undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ 117 #define CONFIG_BAUDRATE 115200 118 #define CONFIG_SERIAL_MULTI 119 #define CONFIG_SYS_BAUDRATE_TABLE \ 120 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} 121 #undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ 122 123 /*----------------------------------------------------------------------- 124 * Environment 125 *----------------------------------------------------------------------*/ 126 /* 127 * Define here the location of the environment variables (FLASH). 128 */ 129 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 130 131 /* 132 * IPL (Initial Program Loader, integrated inside CPU) 133 * Will load first 4k from NAND (SPL) into cache and execute it from there. 134 * 135 * SPL (Secondary Program Loader) 136 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL 137 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM 138 * controller and the NAND controller so that the special U-Boot image can be 139 * loaded from NAND to SDRAM. 140 * 141 * NUB (NAND U-Boot) 142 * This NAND U-Boot (NUB) is a special U-Boot version which can be started 143 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. 144 * 145 * On 440EPx the SPL is copied to SDRAM before the NAND controller is 146 * set up. While still running from cache, I experienced problems accessing 147 * the NAND controller. sr - 2006-08-25 148 * 149 * This is the first official implementation of booting from 2k page sized 150 * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8) 151 */ 152 153 /* 154 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) 155 */ 156 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) /* Offset to RAM U-Boot image */ 157 #define CONFIG_SYS_NAND_U_BOOT_SIZE (1 << 20) /* Size of RAM U-Boot image */ 158 159 /* 160 * Now the NAND chip has to be defined (no autodetection used!) 161 */ 162 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) /* NAND chip page size */ 163 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ 164 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE) 165 /* NAND chip page count */ 166 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 /* Location of bad block marker*/ 167 #define CONFIG_SYS_NAND_5_ADDR_CYCLE /* Fifth addr used (<=128MB) */ 168 169 #define CONFIG_SYS_NAND_ECCSIZE 256 170 #define CONFIG_SYS_NAND_ECCBYTES 3 171 #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) 172 #define CONFIG_SYS_NAND_OOBSIZE 64 173 #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS) 174 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \ 175 48, 49, 50, 51, 52, 53, 54, 55, \ 176 56, 57, 58, 59, 60, 61, 62, 63} 177 178 #ifdef CONFIG_ENV_IS_IN_NAND 179 /* 180 * For NAND booting the environment is embedded in the U-Boot image. Please take 181 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details. 182 */ 183 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 184 #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) 185 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 186 #endif 187 188 /*----------------------------------------------------------------------- 189 * FLASH related 190 *----------------------------------------------------------------------*/ 191 #define CONFIG_SYS_NO_FLASH 1 192 193 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 194 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ 195 196 #define CONFIG_SYS_FLASH_ERASE_TOUT 150000 /* Timeout for Flash Erase (in ms) */ 197 #define CONFIG_SYS_FLASH_WRITE_TOUT 800 /* Timeout for Flash Write (in ms) */ 198 199 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 200 201 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char 202 #define CONFIG_SYS_FLASH_ADDR0 0x555 203 #define CONFIG_SYS_FLASH_ADDR1 0x2aa 204 /*----------------------------------------------------------------------- 205 * NAND-FLASH related 206 *----------------------------------------------------------------------*/ 207 #define CONFIG_SYS_MAX_NAND_DEVICE 1 208 #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */ 209 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) 210 211 /*------------------------------------------------------------------------------ 212 * DDR SDRAM 213 *----------------------------------------------------------------------------*/ 214 #if !defined(CONFIG_NAND_U_BOOT) 215 /* 216 * NAND booting U-Boot version uses a fixed initialization, since the whole 217 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot 218 * code. 219 */ 220 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ 221 #define SPD_EEPROM_ADDRESS {0x50} /* SPD i2c spd addresses*/ 222 #undef CONFIG_DDR_ECC 223 #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ 224 #endif 225 226 /*----------------------------------------------------------------------- 227 * I2C 228 *----------------------------------------------------------------------*/ 229 #define CONFIG_HARD_I2C /* I2C with hardware support */ 230 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ 231 #define CONFIG_SYS_I2C_SLAVE 0x7F 232 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ 233 234 #define CONFIG_SYS_I2C_MULTI_EEPROMS 235 #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) 236 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 238 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 239 240 /* I2C bootstrap EEPROM */ 241 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 242 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 243 #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 244 245 /* RTC configuration */ 246 #define CONFIG_RTC_M41T62 1 247 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 248 249 #ifdef CONFIG_ENV_IS_IN_EEPROM 250 #define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars */ 251 #define CONFIG_ENV_OFFSET 0x0 252 #define CONFIG_ENV_OVERWRITE 253 #endif /* CFG_ENV_IS_IN_EEPROM */ 254 255 /*----------------------------------------------------------------------- 256 * Ethernet 257 *----------------------------------------------------------------------*/ 258 #define CONFIG_PPC4xx_EMAC 259 #define CONFIG_MII /* MII PHY management */ 260 #define CONFIG_NET_MULTI 261 #undef CONFIG_NETCONSOLE /* include NetConsole support */ 262 #define CONFIG_SYS_RX_ETH_BUFFER 4 /* number of eth rx buffers */ 263 264 #define CONFIG_IBM_EMAC4_V4 1 265 #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ 266 #define CONFIG_PHY1_ADDR 1 267 #define CONFIG_HAS_ETH0 268 #define CONFIG_HAS_ETH1 269 270 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ 271 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 272 #define CONFIG_PHY_DYNAMIC_ANEG 1 273 274 /*----------------------------------------------------------------------- 275 * USB-OHCI 276 *----------------------------------------------------------------------*/ 277 /* Only Canyonlands (460EX) has USB */ 278 #ifdef CONFIG_460EX 279 #define CONFIG_USB_OHCI_NEW 280 #define CONFIG_USB_STORAGE 281 #define CONFIG_USB_KEYBOARD 282 #define CONFIG_SYS_USB_EVENT_POLL 283 #undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */ 284 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */ 285 #undef CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */ 286 #define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000) 287 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" 288 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 289 #endif 290 291 /* 292 * Default environment variables 293 */ 294 #define CONFIG_EXTRA_ENV_SETTINGS \ 295 "stdout=vga\0" \ 296 "stdin=usbkbd\0" \ 297 "hush=0\0" \ 298 "ide_doreset=on\0" \ 299 "ide_reset_timeout=15\0" \ 300 "ide_cd_timeout=20\0" \ 301 "pcie_mode=RP:RP\0" \ 302 "pciconfighost=1\0" \ 303 "ipaddr=192.168.2.50\0" \ 304 "serverip=192.168.2.222\0" \ 305 "ethaddr=00:50:C2:80:D5:00\0" \ 306 "video_activate=pci\0" \ 307 "menuboot_delay=2\0" \ 308 "boota_timeout=2\0" \ 309 "bootcmd=menu; run menuboot_cmd\0" \ 310 "menucmd=menu\0" \ 311 "menuboot_cmd=boota\0" \ 312 "boot_method=boota\0" \ 313 "boot1=ssiicdrom\0" \ 314 "boot2=ssii\0" \ 315 "boot3=usb\0" \ 316 "os4_commandline=debuglevel=0\0" \ 317 "bootargs=root=/dev/sda3 console=tty0\0"\ 318 "serdes=sata2\0" \ 319 "usb_enable_4x0=1\0" \ 320 "usb_retry=1\0" \ 321 "usb_ohci_power_down_before_reset=1\0" \ 322 "scan_usb_storage=1\0" 323 324 /* 325 * Commands 326 */ 327 328 #define CONFIG_CMD_BDI /* bdinfo */ 329 #ifndef CONFIG_SYS_NO_FLASH 330 #define CONFIG_CMD_FLASH /* flinfo, erase, protect */ 331 #endif 332 #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ 333 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 334 #define CONFIG_CMD_RUN /* run command in env variable */ 335 #define CONFIG_CMD_SAVEENV /* saveenv */ 336 337 #if defined(CONFIG_440) 338 #undef CONFIG_CMD_CACHE 339 #endif 340 341 #define CONFIG_CMD_EEPROM 342 #define CONFIG_CMD_ELF 343 #define CONFIG_CMD_I2C 344 #define CONFIG_CMD_MII 345 #define CONFIG_CMD_NET 346 347 #if defined(CONFIG_SYS_RAMBOOT) 348 /* 349 * Disable NOR FLASH commands on RAM-booting version. One main reason for this 350 * RAM-booting version is boards with NAND and without NOR. This image can 351 * be used for initial NAND programming. 352 */ 353 #define CONFIG_SYS_NO_FLASH 354 #undef CONFIG_CMD_FLASH 355 #undef CONFIG_CMD_IMLS 356 #endif 357 358 #define CONFIG_CMD_DATE 359 /* #define CONFIG_CMD_NAND */ 360 #define CONFIG_CMD_PCI 361 #ifdef CONFIG_460EX 362 #define CONFIG_CMD_EXT2 363 #define CONFIG_CMD_USB 364 #endif 365 366 /* Partitions */ 367 #define CONFIG_DOS_PARTITION 368 #define CONFIG_ISO_PARTITION 369 #define CONFIG_AMIGA_PARTITION 370 371 /*----------------------------------------------------------------------- 372 * PCI stuff 373 *----------------------------------------------------------------------*/ 374 /* General PCI */ 375 #define CONFIG_PCI /* include pci support */ 376 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 377 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 378 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 379 #define CFG_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI_BASE | 0x08000000) /* PCIX0_IOBASE */ 380 381 /* Board-specific PCI */ 382 #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ 383 #define CONFIG_SYS_PCI_MASTER_INIT 384 385 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ 386 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ 387 388 #define CONFIG_SYS_SCSI_SCAN_BUS_REVERSE /* Don't touch */ 389 390 /* 391 * SATA driver setup 392 */ 393 #define CONFIG_SATA_DWC 394 #define CONFIG_LIBATA 395 #define SATA_BASE_ADDR 0xe20d1000 /* PPC460EX SATA Base Address */ 396 #define SATA_DMA_REG_ADDR 0xe20d0800 /* PPC460EX SATA Base Address */ 397 #define CONFIG_SYS_SATA_MAX_DEVICE 1 /* SATA MAX DEVICE */ 398 /* Convert sectorsize to wordsize */ 399 #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2) 400 401 /*----------------------------------------------------------------------- 402 * Video stuff 403 *----------------------------------------------------------------------*/ 404 #define CONFIG_VIDEO_SM502 405 #define CONFIG_VIDEO_SM501_8BPP 406 407 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 408 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 409 410 /*----------------------------------------------------------------------- 411 * IDE ATAPI Configuration 412 *----------------------------------------------------------------------*/ 413 #define CONFIG_LBA48 1 414 #define CONFIG_ATAPI 1 415 #define CONFIG_SYS_IDE_MAXBUS 2 416 #define CONFIG_SYS_IDE_MAXDEVICE 4 417 418 #define CONFIG_SYS_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS 419 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x1F0 420 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 421 #define CONFIG_SYS_ATA_REG_OFFSET 0 422 #define CONFIG_SYS_ATA_DATA_OFFSET 0 423 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 424 425 /* 426 #define CONFIG_CMD_SCSI 427 #define SCSI_VEND_ID 0x197b 428 #define SCSI_DEV_ID 0x2363 429 #define CONFIG_SCSI_AHCI 430 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 431 #define CONFIG_SYS_SCSI_MAX_LUN 1 432 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 433 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 434 */ 435 /*----------------------------------------------------------------------- 436 * External Bus Controller (EBC) Setup 437 *----------------------------------------------------------------------*/ 438 439 /* Memory Bank 0 (NOR-FLASH) initialization */ 440 #define CONFIG_SYS_EBC_PB0AP 0x06057240 441 #define CONFIG_SYS_EBC_PB0CR 0xfff18000 //(CONFIG_SYS_BOOT_BASE_ADDR | 0x18000) 442 443 /* Memory Bank 2 (FPGA) initialization */ 444 #define CONFIG_SYS_EBC_PB2AP 0x7f8ffe80 445 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/ 446 447 /* Memory Bank 3 (NAND-FLASH) initialization */ 448 /* #define CONFIG_SYS_EBC_PB3AP 0x018003c0 */ 449 /* #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) *//* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/ 450 451 #define CONFIG_SYS_EBC_CFG 0xB8400000 /* EBC0_CFG */ 452 453 /*----------------------------------------------------------------------- 454 * Miscellaneous configurable options 455 *----------------------------------------------------------------------*/ 456 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 457 #define CONFIG_SYS_PROMPT "] " /* Monitor Command Prompt */ 458 #if defined(CONFIG_CMD_KGDB) 459 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 460 #else 461 #define CONFIG_SYS_CBSIZE 100 /* Console I/O Buffer Size */ 462 #endif 463 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 464 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 465 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 466 467 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 468 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 469 470 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 471 #define CONFIG_SYS_EXTBDINFO /* To use extended board_into (bd_t) */ 472 473 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 474 475 #undef CONFIG_CMDLINE_EDITING /* add command line history */ 476 #undef CONFIG_AUTO_COMPLETE /* add autocompletion support */ 477 #undef CONFIG_LOOPW /* enable loopw command */ 478 #undef CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ 479 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 480 #define CONFIG_VERSION_VARIABLE /* include version env variable */ 481 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ 482 #define CONFIG_SILENT_CONSOLE 483 484 #undef CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 485 #ifdef CONFIG_SYS_HUSH_PARSER 486 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 487 #endif 488 489 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 490 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 491 492 /* 493 * For booting Linux, the board info and command line data 494 * have to be in the first 16 MB of memory, since this is 495 * the maximum mapped by the 40x Linux kernel during initialization. 496 */ 497 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ 498 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 499 500 /* 501 * Internal Definitions 502 */ 503 #if defined(CONFIG_CMD_KGDB) 504 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ 505 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 506 #endif 507 508 /* 509 * Pass open firmware flat tree 510 */ 511 #define CONFIG_OF_LIBFDT 512 #define CONFIG_OF_BOARD_SETUP 513 514 /* 515 * Only very few boards have default console not on ttyS0 (like Taishan) 516 */ 517 #if !defined(CONFIG_USE_TTY) 518 #define CONFIG_USE_TTY ttyS0 519 #endif 520 521 /* 522 * Only very few boards have default netdev not set to eth0 (like Arches) 523 */ 524 #if !defined(CONFIG_USE_NETDEV) 525 #define CONFIG_USE_NETDEV eth0 526 #endif 527 528 #define xstr(s) str(s) 529 #define str(s) #s 530 531 /* 532 * PPC4xx GPIO Configuration 533 */ 534 535 /* 460EX: Use USB configuration */ 536 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ 537 { \ 538 /* GPIO Core 0 */ \ 539 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \ 540 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \ 541 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \ 542 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \ 543 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \ 544 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \ 545 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \ 546 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \ 547 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \ 548 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \ 549 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \ 550 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \ 551 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \ 552 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \ 553 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \ 554 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \ 555 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \ 556 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \ 557 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \ 558 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \ 559 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \ 560 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \ 561 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \ 562 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \ 563 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \ 564 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \ 565 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \ 566 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \ 567 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \ 568 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \ 569 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO30 USER TP5 */ \ 570 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 USER TP6 */ \ 571 }, \ 572 { \ 573 /* GPIO Core 1 */ \ 574 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USER TP8 */ \ 575 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USER TP10 */ \ 576 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ 577 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ 578 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \ 579 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \ 580 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ 581 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ 582 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \ 583 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO41 CS(1) */ \ 584 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \ 585 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \ 586 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \ 587 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \ 588 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \ 589 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \ 590 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \ 591 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ 592 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ 593 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ 594 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52 HD LED */ \ 595 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ 596 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ 597 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \ 598 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ 599 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ 600 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ 601 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ 602 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ 603 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ 604 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ 605 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ 606 } \ 607 } 608 609 #endif /* __CONFIG_H */ 610