1 /******************************************************************** 2 * 3 * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms 4 * 5 * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/include/configs/barco.h,v $ 6 * $Revision: 1.2 $ 7 * $Author: mleeman $ 8 * $Date: 2005/02/21 12:48:58 $ 9 * 10 * Last ChangeLog Entry 11 * $Log: barco.h,v $ 12 * Revision 1.2 2005/02/21 12:48:58 mleeman 13 * update of copyright years (feedback wd) 14 * 15 * Revision 1.1 2005/02/14 09:29:25 mleeman 16 * moved barcohydra.h to barco.h 17 * 18 * Revision 1.4 2005/02/09 12:56:23 mleeman 19 * add generic header to track changes in sources 20 * 21 * 22 *******************************************************************/ 23 24 /* 25 * (C) Copyright 2001, 2002 26 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 27 * 28 * See file CREDITS for list of people who contributed to this 29 * project. 30 * 31 * This program is free software; you can redistribute it and/or 32 * modify it under the terms of the GNU General Public License as 33 * published by the Free Software Foundation; either version 2 of 34 * the License, or (at your option) any later version. 35 * 36 * This program is distributed in the hope that it will be useful, 37 * but WITHOUT ANY WARRANTY; without even the implied warranty of 38 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 39 * GNU General Public License for more details. 40 * 41 * You should have received a copy of the GNU General Public License 42 * along with this program; if not, write to the Free Software 43 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 44 * MA 02111-1307 USA 45 */ 46 47 /* ------------------------------------------------------------------------- */ 48 49 /* 50 * board/config.h - configuration options, board specific 51 */ 52 53 #ifndef __CONFIG_H 54 #define __CONFIG_H 55 56 /* 57 * High Level Configuration Options 58 * (easy to change) 59 */ 60 61 #define CONFIG_MPC824X 1 62 #define CONFIG_MPC8245 1 63 #define CONFIG_BARCOBCD_STREAMING 1 64 65 #undef USE_DINK32 66 67 #define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ 68 #define CONFIG_BAUDRATE 9600 69 #define CONFIG_DRAM_SPEED 100 /* MHz */ 70 71 #define CONFIG_BOOTARGS "mem=32M" 72 73 74 /* 75 * BOOTP options 76 */ 77 #define CONFIG_BOOTP_SUBNETMASK 78 #define CONFIG_BOOTP_GATEWAY 79 #define CONFIG_BOOTP_HOSTNAME 80 #define CONFIG_BOOTP_BOOTPATH 81 #define CONFIG_BOOTP_BOOTFILESIZE 82 #define CONFIG_BOOTP_DNS 83 84 85 /* 86 * Command line configuration. 87 */ 88 #include <config_cmd_default.h> 89 90 #define CONFIG_CMD_ELF 91 #define CONFIG_CMD_I2C 92 #define CONFIG_CMD_EEPROM 93 #define CONFIG_CMD_PCI 94 95 #undef CONFIG_CMD_NET 96 97 98 #define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */ 99 #define CONFIG_BOOTDELAY 1 100 #define CONFIG_BOOTCOMMAND "boot_default" 101 102 /* 103 * Miscellaneous configurable options 104 */ 105 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ 106 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 107 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 108 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 109 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 110 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 111 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ 112 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 113 114 115 /*----------------------------------------------------------------------- 116 * PCI stuff 117 *----------------------------------------------------------------------- 118 */ 119 #define CONFIG_PCI /* include pci support */ 120 #undef CONFIG_PCI_PNP 121 122 #define PCI_ENET0_IOADDR 0x80000000 123 #define PCI_ENET0_MEMADDR 0x80000000 124 #define PCI_ENET1_IOADDR 0x81000000 125 #define PCI_ENET1_MEMADDR 0x81000000 126 127 128 /*----------------------------------------------------------------------- 129 * Start addresses for the final memory configuration 130 * (Set up by the startup code) 131 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 132 */ 133 #define CONFIG_SYS_SDRAM_BASE 0x00000000 134 #define CONFIG_SYS_MAX_RAM_SIZE 0x02000000 135 136 #define CONFIG_LOGBUFFER 137 #ifdef CONFIG_LOGBUFFER 138 #define CONFIG_SYS_STDOUT_ADDR 0x1FFC000 139 #else 140 #define CONFIG_SYS_STDOUT_ADDR 0x2B9000 141 #endif 142 143 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 144 145 #if defined (USE_DINK32) 146 #define CONFIG_SYS_MONITOR_LEN 0x00030000 147 #define CONFIG_SYS_MONITOR_BASE 0x00090000 148 #define CONFIG_SYS_RAMBOOT 1 149 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 150 #define CONFIG_SYS_INIT_RAM_END 0x10000 151 #define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ 152 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 153 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 154 #else 155 #undef CONFIG_SYS_RAMBOOT 156 #define CONFIG_SYS_MONITOR_LEN 0x00030000 157 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE 158 159 #define CONFIG_SYS_GBL_DATA_SIZE 128 160 161 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 162 #define CONFIG_SYS_INIT_RAM_END 0x1000 163 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 164 165 #endif 166 167 #define CONFIG_SYS_FLASH_BASE 0xFFF00000 168 #define CONFIG_SYS_FLASH_SIZE (8 * 1024 * 1024) /* Unity has onboard 1MByte flash */ 169 #define CONFIG_ENV_IS_IN_FLASH 1 170 #define CONFIG_ENV_OFFSET 0x000047A4 /* Offset of Environment Sector */ 171 #define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ 172 /* #define ENV_CRC 0x8BF6F24B XXX - FIXME: gets defined automatically */ 173 174 #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ 175 176 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 177 #define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ 178 179 #define CONFIG_SYS_EUMB_ADDR 0xFDF00000 180 181 #define CONFIG_SYS_FLASH_RANGE_BASE 0xFFC00000 /* flash memory address range */ 182 #define CONFIG_SYS_FLASH_RANGE_SIZE 0x00400000 183 #define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ 184 #define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ 185 186 /* 187 * select i2c support configuration 188 * 189 * Supported configurations are {none, software, hardware} drivers. 190 * If the software driver is chosen, there are some additional 191 * configuration items that the driver uses to drive the port pins. 192 */ 193 #define CONFIG_HARD_I2C 1 /* To enable I2C support */ 194 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 195 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 196 #define CONFIG_SYS_I2C_SLAVE 0x7F 197 198 #ifdef CONFIG_SOFT_I2C 199 #error "Soft I2C is not configured properly. Please review!" 200 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 201 #define I2C_ACTIVE (iop->pdir |= 0x00010000) 202 #define I2C_TRISTATE (iop->pdir &= ~0x00010000) 203 #define I2C_READ ((iop->pdat & 0x00010000) != 0) 204 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ 205 else iop->pdat &= ~0x00010000 206 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ 207 else iop->pdat &= ~0x00020000 208 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 209 #endif /* CONFIG_SOFT_I2C */ 210 211 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ 212 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 213 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 215 216 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 217 #define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } 218 #define CONFIG_SYS_DBUS_SIZE2 1 219 220 /*----------------------------------------------------------------------- 221 * Definitions for initial stack pointer and data area (in DPRAM) 222 */ 223 224 225 /* 226 * NS16550 Configuration (internal DUART) 227 */ 228 /* 229 * Low Level Configuration Settings 230 * (address mappings, register initial values, etc.) 231 * You should know what you are doing if you make changes here. 232 */ 233 234 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ 235 236 #define CONFIG_SYS_ROMNAL 0x0F /*rom/flash next access time */ 237 #define CONFIG_SYS_ROMFAL 0x1E /*rom/flash access time */ 238 239 #define CONFIG_SYS_REFINT 0x8F /* no of clock cycles between CBR refresh cycles */ 240 241 /* the following are for SDRAM only*/ 242 #define CONFIG_SYS_BSTOPRE 0x25C /* Burst To Precharge, sets open page interval */ 243 #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ 244 #define CONFIG_SYS_RDLAT 4 /* data latency from read command */ 245 #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ 246 #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ 247 #define CONFIG_SYS_ACTORW 2 /* Activate to R/W */ 248 #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ 249 #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ 250 251 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 252 #define CONFIG_SYS_EXTROM 0 253 #define CONFIG_SYS_REGDIMM 0 254 255 256 /* memory bank settings*/ 257 /* 258 * only bits 20-29 are actually used from these vales to set the 259 * start/end address the upper two bits will be 0, and the lower 20 260 * bits will be set to 0x00000 for a start address, or 0xfffff for an 261 * end address 262 */ 263 #define CONFIG_SYS_BANK0_START 0x00000000 264 #define CONFIG_SYS_BANK0_END 0x01FFFFFF 265 #define CONFIG_SYS_BANK0_ENABLE 1 266 #define CONFIG_SYS_BANK1_START 0x02000000 267 #define CONFIG_SYS_BANK1_END 0x02ffffff 268 #define CONFIG_SYS_BANK1_ENABLE 0 269 #define CONFIG_SYS_BANK2_START 0x03f00000 270 #define CONFIG_SYS_BANK2_END 0x03ffffff 271 #define CONFIG_SYS_BANK2_ENABLE 0 272 #define CONFIG_SYS_BANK3_START 0x04000000 273 #define CONFIG_SYS_BANK3_END 0x04ffffff 274 #define CONFIG_SYS_BANK3_ENABLE 0 275 #define CONFIG_SYS_BANK4_START 0x05000000 276 #define CONFIG_SYS_BANK4_END 0x05FFFFFF 277 #define CONFIG_SYS_BANK4_ENABLE 0 278 #define CONFIG_SYS_BANK5_START 0x06000000 279 #define CONFIG_SYS_BANK5_END 0x06FFFFFF 280 #define CONFIG_SYS_BANK5_ENABLE 0 281 #define CONFIG_SYS_BANK6_START 0x07000000 282 #define CONFIG_SYS_BANK6_END 0x07FFFFFF 283 #define CONFIG_SYS_BANK6_ENABLE 0 284 #define CONFIG_SYS_BANK7_START 0x08000000 285 #define CONFIG_SYS_BANK7_END 0x08FFFFFF 286 #define CONFIG_SYS_BANK7_ENABLE 0 287 /* 288 * Memory bank enable bitmask, specifying which of the banks defined above 289 are actually present. MSB is for bank #7, LSB is for bank #0. 290 */ 291 #define CONFIG_SYS_BANK_ENABLE 0x01 292 293 #define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ 294 /* see 8240 book for bit definitions */ 295 #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ 296 /* currently accessed page in memory */ 297 /* see 8240 book for details */ 298 299 /* SDRAM 0 - 256MB */ 300 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 301 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 302 303 /* stack in DCACHE @ 1GB (no backing mem) */ 304 #if defined(USE_DINK32) 305 #define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) 306 #define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) 307 #else 308 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 309 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 310 #endif 311 312 /* PCI memory */ 313 #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 314 #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) 315 316 /* Flash, config addrs, etc */ 317 #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 318 #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 319 320 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 321 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 322 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 323 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 324 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 325 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 326 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 327 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 328 329 /* 330 * For booting Linux, the board info and command line data 331 * have to be in the first 8 MB of memory, since this is 332 * the maximum mapped by the Linux kernel during initialization. 333 */ 334 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 335 /*----------------------------------------------------------------------- 336 * FLASH organization 337 */ 338 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 339 #define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ 340 341 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 342 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 343 344 #define CONFIG_SYS_FLASH_CHECKSUM 345 346 /*----------------------------------------------------------------------- 347 * Cache Configuration 348 */ 349 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ 350 #if defined(CONFIG_CMD_KGDB) 351 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 352 #endif 353 354 355 /* 356 * Internal Definitions 357 * 358 * Boot Flags 359 */ 360 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 361 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 362 363 /* values according to the manual */ 364 365 #define CONFIG_DRAM_50MHZ 1 366 #define CONFIG_SDRAM_50MHZ 367 368 #define CONFIG_DISK_SPINUP_TIME 1000000 369 370 371 #endif /* __CONFIG_H */ 372