1 /* 2 * U-boot - Configuration file for BF548 STAMP board 3 */ 4 5 #ifndef __CONFIG_BF548_EZKIT_H__ 6 #define __CONFIG_BF548_EZKIT_H__ 7 8 #include <asm/config-pre.h> 9 10 11 /* 12 * Processor Settings 13 */ 14 #define CONFIG_BFIN_CPU bf548-0.0 15 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA 16 17 18 /* 19 * Clock Settings 20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV 21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV 22 */ 23 /* CONFIG_CLKIN_HZ is any value in Hz */ 24 #define CONFIG_CLKIN_HZ 25000000 25 /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ 26 /* 1 = CLKIN / 2 */ 27 #define CONFIG_CLKIN_HALF 0 28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ 29 /* 1 = bypass PLL */ 30 #define CONFIG_PLL_BYPASS 0 31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ 32 /* Values can range from 0-63 (where 0 means 64) */ 33 #define CONFIG_VCO_MULT 21 34 /* CCLK_DIV controls the core clock divider */ 35 /* Values can be 1, 2, 4, or 8 ONLY */ 36 #define CONFIG_CCLK_DIV 1 37 /* SCLK_DIV controls the system clock divider */ 38 /* Values can range from 1-15 */ 39 #define CONFIG_SCLK_DIV 4 40 41 42 /* 43 * Memory Settings 44 */ 45 #define CONFIG_MEM_ADD_WDTH 10 46 #define CONFIG_MEM_SIZE 64 47 48 #define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE 49 #define CONFIG_EBIU_DDRCTL1_VAL 0x20022222 50 #define CONFIG_EBIU_DDRCTL2_VAL 0x00000021 51 52 /* Default EZ-Kit bank mapping: 53 * Async Bank 0 - 32MB Burst Flash 54 * Async Bank 1 - Ethernet 55 * Async Bank 2 - Nothing 56 * Async Bank 3 - Nothing 57 */ 58 #define CONFIG_EBIU_AMGCTL_VAL 0xFF 59 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 60 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 61 #define CONFIG_EBIU_FCTL_VAL (BCLK_4) 62 #define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) 63 64 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) 65 #define CONFIG_SYS_MALLOC_LEN (768 * 1024) 66 67 68 /* 69 * Network Settings 70 */ 71 #define ADI_CMDS_NETWORK 1 72 #define CONFIG_NET_MULTI 73 #define CONFIG_SMC911X 1 74 #define CONFIG_SMC911X_BASE 0x24000000 75 #define CONFIG_SMC911X_16_BIT 76 #define CONFIG_HOSTNAME bf548-ezkit 77 /* Uncomment next line to use fixed MAC address */ 78 /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ 79 80 81 /* 82 * Flash Settings 83 */ 84 #define CONFIG_FLASH_CFI_DRIVER 85 #define CONFIG_SYS_FLASH_BASE 0x20000000 86 #define CONFIG_SYS_FLASH_CFI 87 #define CONFIG_SYS_FLASH_PROTECTION 88 #define CONFIG_SYS_MAX_FLASH_BANKS 1 89 #define CONFIG_SYS_MAX_FLASH_SECT 259 90 91 92 /* 93 * SPI Settings 94 */ 95 #define CONFIG_BFIN_SPI 96 #define CONFIG_ENV_SPI_MAX_HZ 30000000 97 #define CONFIG_SF_DEFAULT_SPEED 30000000 98 #define CONFIG_SPI_FLASH 99 #define CONFIG_SPI_FLASH_STMICRO 100 101 102 /* 103 * Env Storage Settings 104 */ 105 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) 106 #define CONFIG_ENV_IS_IN_SPI_FLASH 107 #define CONFIG_ENV_OFFSET 0x10000 108 #define CONFIG_ENV_SIZE 0x2000 109 #define CONFIG_ENV_SECT_SIZE 0x10000 110 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR 111 #elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) 112 #define CONFIG_ENV_IS_IN_NAND 113 #define CONFIG_ENV_OFFSET 0x40000 114 #define CONFIG_ENV_SIZE 0x20000 115 #else 116 #define CONFIG_ENV_IS_IN_FLASH 1 117 #define CONFIG_ENV_ADDR 0x20002000 118 #define CONFIG_ENV_OFFSET 0x2000 119 #define CONFIG_ENV_SIZE 0x2000 120 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 121 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR 122 #endif 123 124 125 /* 126 * NAND Settings 127 */ 128 #define CONFIG_BFIN_NFC_CTL_VAL 0x0033 129 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) 130 # define CONFIG_BFIN_NFC_BOOTROM_ECC 131 #endif 132 #define CONFIG_DRIVER_NAND_BFIN 133 #define CONFIG_SYS_NAND_BASE 0 /* not actually used */ 134 #define CONFIG_SYS_MAX_NAND_DEVICE 1 135 #define NAND_MAX_CHIPS 1 136 137 138 /* 139 * I2C Settings 140 */ 141 #define CONFIG_BFIN_TWI_I2C 1 142 #define CONFIG_HARD_I2C 1 143 #define CONFIG_SYS_I2C_SPEED 50000 144 #define CONFIG_SYS_I2C_SLAVE 0 145 146 147 /* 148 * SATA 149 */ 150 #if !defined(__ADSPBF544__) 151 #define CONFIG_LIBATA 152 #define CONFIG_SYS_SATA_MAX_DEVICE 1 153 #define CONFIG_LBA48 154 #define CONFIG_PATA_BFIN 155 #define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800 156 #define CONFIG_BFIN_ATA_MODE XFER_PIO_4 157 #endif 158 159 160 /* 161 * SDH Settings 162 */ 163 #if !defined(__ADSPBF544__) 164 #define CONFIG_GENERIC_MMC 165 #define CONFIG_MMC 166 #define CONFIG_BFIN_SDH 167 #endif 168 169 170 /* 171 * USB Settings 172 */ 173 #if !defined(__ADSPBF544__) 174 #define CONFIG_USB 175 #define CONFIG_MUSB_HCD 176 #define CONFIG_USB_BLACKFIN 177 #define CONFIG_USB_STORAGE 178 #define CONFIG_MUSB_TIMEOUT 100000 179 #endif 180 181 182 /* 183 * Misc Settings 184 */ 185 #define CONFIG_BOARD_EARLY_INIT_F 186 #define CONFIG_RTC_BFIN 187 #define CONFIG_UART_CONSOLE 1 188 189 #ifndef __ADSPBF542__ 190 /* Don't waste time transferring a logo over the UART */ 191 # if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) 192 # define CONFIG_VIDEO 193 # endif 194 # define CONFIG_DEB_DMA_URGENT 195 #endif 196 197 /* Define if want to do post memory test */ 198 #undef CONFIG_POST 199 #ifdef CONFIG_POST 200 #define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ 201 #define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ 202 #endif 203 204 205 /* 206 * Pull in common ADI header for remaining command/environment setup 207 */ 208 #include <configs/bfin_adi_common.h> 209 210 #endif 211