1 /* 2 * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de> 3 * Anders Larsen <alarsen@rea.de> 4 * 5 * Configuation settings for the Cogent CSB637 board. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #define CONFIG_AT91_LEGACY 30 31 /* ARM asynchronous clock */ 32 #define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */ 33 #define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */ 34 35 #define AT91_SLOW_CLOCK 32768 /* slow clock */ 36 37 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ 38 #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ 39 #define CONFIG_CSB637 1 /* on a CSB637 board */ 40 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 41 #define USE_920T_MMU 1 42 43 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 44 #define CONFIG_SETUP_MEMORY_TAGS 1 45 #define CONFIG_INITRD_TAG 1 46 47 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 48 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 49 /* flash */ 50 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 51 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ 52 53 /* clocks */ 54 #define CONFIG_SYS_PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ 55 #define CONFIG_SYS_PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */ 56 #define CONFIG_SYS_MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */ 57 58 /* sdram */ 59 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ 60 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 61 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 62 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ 63 #define CONFIG_SYS_SDRC_CR_VAL 0x21914159 /* set up the CONFIG_SYS_SDRAM */ 64 #define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ 65 #define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ 66 #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ 67 #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ 68 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ 69 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ 70 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ 71 #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ 72 #else 73 #define CONFIG_SKIP_RELOCATE_UBOOT 74 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 75 /* 76 * Size of malloc() pool 77 */ 78 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 79 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 80 81 #define CONFIG_BAUDRATE 115200 82 83 #define CONFIG_SYS_AT91C_BRGR_DIVISOR 75 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */ 84 85 /* 86 * Hardware drivers 87 */ 88 89 /* define one of these to choose the DBGU, USART0 or USART1 as console */ 90 #define CONFIG_AT91RM9200_USART 91 #define CONFIG_DBGU 92 #undef CONFIG_USART0 93 #undef CONFIG_USART1 94 95 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ 96 97 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ 98 99 #define CONFIG_BOOTDELAY 3 100 /* #define CONFIG_ENV_OVERWRITE 1 */ 101 102 103 /* 104 * BOOTP options 105 */ 106 #define CONFIG_BOOTP_BOOTFILESIZE 107 #define CONFIG_BOOTP_BOOTPATH 108 #define CONFIG_BOOTP_GATEWAY 109 #define CONFIG_BOOTP_HOSTNAME 110 111 112 /* 113 * Command line configuration. 114 */ 115 #include <config_cmd_default.h> 116 117 #define CONFIG_CMD_DHCP 118 #define CONFIG_CMD_JFFS2 119 #define CONFIG_CMD_PING 120 121 122 #define CONFIG_NR_DRAM_BANKS 1 123 #define PHYS_SDRAM 0x20000000 124 #define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */ 125 126 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 127 #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4 128 #define CONFIG_SYS_ALT_MEMTEST 1 129 #define CONFIG_SYS_MEMTEST_SCRATCH CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 4 130 131 #define CONFIG_NET_MULTI 1 132 #ifdef CONFIG_NET_MULTI 133 #define CONFIG_DRIVER_AT91EMAC 1 134 #define CONFIG_SYS_RX_ETH_BUFFER 8 135 #else 136 #define CONFIG_DRIVER_ETHER 1 137 #endif 138 #define CONFIG_NET_RETRY_COUNT 20 139 #undef CONFIG_AT91C_USE_RMII 140 141 #undef CONFIG_HAS_DATAFLASH 142 #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) 143 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 0 144 #define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 145 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ 146 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ 147 148 /* 149 * FLASH Device configuration 150 */ 151 #define PHYS_FLASH_1 0x10000000 152 #define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ 153 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 154 #define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */ 155 #define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ 156 #define CONFIG_SYS_FLASH_EMPTY_INFO 157 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ 158 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ 159 #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ 160 #define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ 161 #define CONFIG_SYS_MAX_FLASH_SECT 64 162 163 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 164 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 3 165 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 166 167 #undef CONFIG_ENV_IS_IN_DATAFLASH 168 169 #ifdef CONFIG_ENV_IS_IN_DATAFLASH 170 #define CONFIG_ENV_OFFSET 0x20000 171 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 172 #define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */ 173 #else 174 #define CONFIG_ENV_IS_IN_FLASH 1 175 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */ 176 #define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */ 177 #endif /* CONFIG_ENV_IS_IN_DATAFLASH */ 178 179 180 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ 181 182 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } 183 184 #define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */ 185 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 186 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 187 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 188 189 #define CONFIG_SYS_HZ 1000 190 #define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ 191 /* AT91C_TC_TIMER_DIV1_CLOCK */ 192 193 #define CONFIG_STACKSIZE (32*1024) /* regular stack */ 194 195 #ifdef CONFIG_USE_IRQ 196 #error CONFIG_USE_IRQ not supported 197 #endif 198 199 #endif 200