1 /* 2 * Configuration settings for the Gumstix Overo board. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* 24 * High Level Configuration Options 25 */ 26 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 27 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 28 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 29 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 30 #define CONFIG_OMAP3_OVERO 1 /* working with overo */ 31 32 #define CONFIG_SDRC /* The chip has SDRC controller */ 33 34 #include <asm/arch/cpu.h> /* get chip and board defs */ 35 #include <asm/arch/omap3.h> 36 37 /* 38 * Display CPU and Board information 39 */ 40 #define CONFIG_DISPLAY_CPUINFO 1 41 #define CONFIG_DISPLAY_BOARDINFO 1 42 43 /* Clock Defines */ 44 #define V_OSCK 26000000 /* Clock output from T2 */ 45 #define V_SCLK (V_OSCK >> 1) 46 47 #undef CONFIG_USE_IRQ /* no support for IRQs */ 48 #define CONFIG_MISC_INIT_R 49 50 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 51 #define CONFIG_SETUP_MEMORY_TAGS 1 52 #define CONFIG_INITRD_TAG 1 53 #define CONFIG_REVISION_TAG 1 54 55 /* 56 * Size of malloc() pool 57 */ 58 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 59 /* Sector */ 60 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 61 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 62 /* initial data */ 63 64 /* 65 * Hardware drivers 66 */ 67 68 /* 69 * NS16550 Configuration 70 */ 71 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 72 73 #define CONFIG_SYS_NS16550 74 #define CONFIG_SYS_NS16550_SERIAL 75 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 76 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 77 78 /* 79 * select serial console configuration 80 */ 81 #define CONFIG_CONS_INDEX 3 82 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 83 #define CONFIG_SERIAL3 3 84 85 /* allow to overwrite serial and ethaddr */ 86 #define CONFIG_ENV_OVERWRITE 87 #define CONFIG_BAUDRATE 115200 88 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 89 115200} 90 #define CONFIG_MMC 1 91 #define CONFIG_OMAP3_MMC 1 92 #define CONFIG_DOS_PARTITION 1 93 94 /* DDR - I use Micron DDR */ 95 #define CONFIG_OMAP3_MICRON_DDR 1 96 97 /* commands to include */ 98 #include <config_cmd_default.h> 99 100 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 101 #define CONFIG_CMD_FAT /* FAT support */ 102 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 103 104 #define CONFIG_CMD_I2C /* I2C serial bus support */ 105 #define CONFIG_CMD_MMC /* MMC support */ 106 #define CONFIG_CMD_NAND /* NAND support */ 107 108 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 109 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 110 #undef CONFIG_CMD_IMI /* iminfo */ 111 #undef CONFIG_CMD_IMLS /* List all found images */ 112 #undef CONFIG_CMD_NFS /* NFS support */ 113 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 114 115 #define CONFIG_SYS_NO_FLASH 116 #define CONFIG_HARD_I2C 1 117 #define CONFIG_SYS_I2C_SPEED 100000 118 #define CONFIG_SYS_I2C_SLAVE 1 119 #define CONFIG_SYS_I2C_BUS 0 120 #define CONFIG_SYS_I2C_BUS_SELECT 1 121 #define CONFIG_DRIVER_OMAP34XX_I2C 1 122 123 /* 124 * TWL4030 125 */ 126 #define CONFIG_TWL4030_POWER 1 127 #define CONFIG_TWL4030_LED 1 128 129 /* 130 * Board NAND Info. 131 */ 132 #define CONFIG_NAND_OMAP_GPMC 133 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 134 /* to access nand */ 135 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 136 /* to access nand */ 137 /* at CS0 */ 138 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 139 140 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 141 /* devices */ 142 #define CONFIG_JFFS2_NAND 143 /* nand device jffs2 lives on */ 144 #define CONFIG_JFFS2_DEV "nand0" 145 /* start of jffs2 partition */ 146 #define CONFIG_JFFS2_PART_OFFSET 0x680000 147 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 148 /* partition */ 149 150 /* Environment information */ 151 #define CONFIG_BOOTDELAY 5 152 153 #define CONFIG_EXTRA_ENV_SETTINGS \ 154 "loadaddr=0x82000000\0" \ 155 "console=ttyS2,115200n8\0" \ 156 "vram=12M\0" \ 157 "dvimode=1024x768MR-16@60\0" \ 158 "defaultdisplay=dvi\0" \ 159 "mmcroot=/dev/mmcblk0p2 rw\0" \ 160 "mmcrootfstype=ext3 rootwait\0" \ 161 "nandroot=/dev/mtdblock4 rw\0" \ 162 "nandrootfstype=jffs2\0" \ 163 "mmcargs=setenv bootargs console=${console} " \ 164 "vram=${vram} " \ 165 "omapfb.mode=dvi:${dvimode} " \ 166 "omapfb.debug=y " \ 167 "omapdss.def_disp=${defaultdisplay} " \ 168 "root=${mmcroot} " \ 169 "rootfstype=${mmcrootfstype}\0" \ 170 "nandargs=setenv bootargs console=${console} " \ 171 "vram=${vram} " \ 172 "omapfb.mode=dvi:${dvimode} " \ 173 "omapfb.debug=y " \ 174 "omapdss.def_disp=${defaultdisplay} " \ 175 "root=${nandroot} " \ 176 "rootfstype=${nandrootfstype}\0" \ 177 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 178 "bootscript=echo Running bootscript from mmc ...; " \ 179 "source ${loadaddr}\0" \ 180 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 181 "mmcboot=echo Booting from mmc ...; " \ 182 "run mmcargs; " \ 183 "bootm ${loadaddr}\0" \ 184 "nandboot=echo Booting from nand ...; " \ 185 "run nandargs; " \ 186 "nand read ${loadaddr} 280000 400000; " \ 187 "bootm ${loadaddr}\0" \ 188 189 #define CONFIG_BOOTCOMMAND \ 190 "if mmc init; then " \ 191 "if run loadbootscript; then " \ 192 "run bootscript; " \ 193 "else " \ 194 "if run loaduimage; then " \ 195 "run mmcboot; " \ 196 "else run nandboot; " \ 197 "fi; " \ 198 "fi; " \ 199 "else run nandboot; fi" 200 201 #define CONFIG_AUTO_COMPLETE 1 202 /* 203 * Miscellaneous configurable options 204 */ 205 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 206 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 207 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 208 #define CONFIG_SYS_PROMPT "Overo # " 209 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 210 /* Print Buffer Size */ 211 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 212 sizeof(CONFIG_SYS_PROMPT) + 16) 213 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 214 /* args */ 215 /* Boot Argument Buffer Size */ 216 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 217 /* memtest works on */ 218 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 219 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 220 0x01F00000) /* 31MB */ 221 222 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 223 /* address */ 224 /* 225 * OMAP3 has 12 GP timers, they can be driven by the system clock 226 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 227 * This rate is divided by a local divisor. 228 */ 229 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 230 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 231 #define CONFIG_SYS_HZ 1000 232 233 /*----------------------------------------------------------------------- 234 * Stack sizes 235 * 236 * The stack sizes are set up in start.S using the settings below 237 */ 238 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 239 #ifdef CONFIG_USE_IRQ 240 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 241 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 242 #endif 243 244 /*----------------------------------------------------------------------- 245 * Physical Memory Map 246 */ 247 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 248 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 249 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 250 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 251 252 /* SDRAM Bank Allocation method */ 253 #define SDRC_R_B_C 1 254 255 /*----------------------------------------------------------------------- 256 * FLASH and environment organization 257 */ 258 259 /* **** PISMO SUPPORT *** */ 260 261 /* Configure the PISMO */ 262 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 263 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 264 265 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 266 /* one chip */ 267 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 268 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 269 270 #define CONFIG_SYS_FLASH_BASE boot_flash_base 271 272 /* Monitor at start of flash */ 273 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 274 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 275 276 #define CONFIG_ENV_IS_IN_NAND 1 277 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ 278 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ 279 280 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 281 #define CONFIG_ENV_OFFSET boot_flash_off 282 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 283 284 /*----------------------------------------------------------------------- 285 * CFI FLASH driver setup 286 */ 287 /* timeout values are in ticks */ 288 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 289 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 290 291 /* Flash banks JFFS2 should use */ 292 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 293 CONFIG_SYS_MAX_NAND_DEVICE) 294 #define CONFIG_SYS_JFFS2_MEM_NAND 295 /* use flash_info[2] */ 296 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 297 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 298 299 #ifndef __ASSEMBLY__ 300 extern unsigned int boot_flash_base; 301 extern volatile unsigned int boot_flash_env_addr; 302 extern unsigned int boot_flash_off; 303 extern unsigned int boot_flash_sec; 304 extern unsigned int boot_flash_type; 305 #endif 306 307 #if defined(CONFIG_CMD_NET) 308 /*---------------------------------------------------------------------------- 309 * SMSC9211 Ethernet from SMSC9118 family 310 *---------------------------------------------------------------------------- 311 */ 312 313 #define CONFIG_NET_MULTI 314 #define CONFIG_SMC911X 1 315 #define CONFIG_SMC911X_32_BIT 316 #define CONFIG_SMC911X_BASE 0x2C000000 317 318 #endif /* (CONFIG_CMD_NET) */ 319 320 #endif /* __CONFIG_H */ 321