1 /* 2 * (C) Copyright 2006-2009 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * Nishanth Menon <nm@ti.com> 7 * Tom Rix <Tom.Rix@windriver.com> 8 * 9 * Configuration settings for the TI OMAP3430 Zoom II board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 #ifndef __CONFIG_H 31 #define __CONFIG_H 32 33 /* 34 * High Level Configuration Options 35 */ 36 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 37 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 38 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 39 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 40 #define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */ 41 42 #define CONFIG_SDRC /* The chip has SDRC controller */ 43 44 #include <asm/arch/cpu.h> /* get chip and board defs */ 45 #include <asm/arch/omap3.h> 46 47 /* 48 * Display CPU and Board information 49 */ 50 #define CONFIG_DISPLAY_CPUINFO 1 51 #define CONFIG_DISPLAY_BOARDINFO 1 52 53 /* Clock Defines */ 54 #define V_OSCK 26000000 /* Clock output from T2 */ 55 #define V_SCLK (V_OSCK >> 1) 56 57 #undef CONFIG_USE_IRQ /* no support for IRQs */ 58 #define CONFIG_MISC_INIT_R 59 60 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 61 #define CONFIG_SETUP_MEMORY_TAGS 1 62 #define CONFIG_INITRD_TAG 1 63 #define CONFIG_REVISION_TAG 1 64 65 /* 66 * Size of malloc() pool 67 */ 68 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 69 /* Sector */ 70 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 71 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 72 /* initial data */ 73 /* 74 * Hardware drivers 75 */ 76 77 /* 78 * NS16550 Configuration 79 * Zoom2 uses the TL16CP754C on the debug board 80 */ 81 #define CONFIG_SERIAL_MULTI 1 82 /* 83 * 0 - 1 : first USB with respect to the left edge of the debug board 84 * 2 - 3 : second USB with respect to the left edge of the debug board 85 */ 86 #define ZOOM2_DEFAULT_SERIAL_DEVICE (&zoom2_serial_device0) 87 88 #define V_NS16550_CLK (1843200) /* 1.8432 Mhz */ 89 90 #define CONFIG_SYS_NS16550 91 #define CONFIG_SYS_NS16550_REG_SIZE (-2) 92 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 93 #define CONFIG_BAUDRATE 115200 94 #define CONFIG_SYS_BAUDRATE_TABLE {115200} 95 96 /* allow to overwrite serial and ethaddr */ 97 #define CONFIG_ENV_OVERWRITE 98 99 #define CONFIG_MMC 1 100 #define CONFIG_OMAP3_MMC 1 101 #define CONFIG_DOS_PARTITION 1 102 103 /* DDR - I use Micron DDR */ 104 #define CONFIG_OMAP3_MICRON_DDR 1 105 106 /* Status LED */ 107 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 108 #define CONFIG_BOARD_SPECIFIC_LED 1 109 #define STATUS_LED_BLUE 0 110 #define STATUS_LED_RED 1 111 /* Blue */ 112 #define STATUS_LED_BIT STATUS_LED_BLUE 113 #define STATUS_LED_STATE STATUS_LED_ON 114 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 115 /* Red */ 116 #define STATUS_LED_BIT1 STATUS_LED_RED 117 #define STATUS_LED_STATE1 STATUS_LED_OFF 118 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) 119 /* Optional value */ 120 #define STATUS_LED_BOOT STATUS_LED_BIT 121 122 /* GPIO banks */ 123 #ifdef CONFIG_STATUS_LED 124 #define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */ 125 #define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */ 126 #endif 127 #define CONFIG_OMAP3_GPIO_3 /* board revision */ 128 #define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */ 129 130 /* USB */ 131 #define CONFIG_MUSB_UDC 1 132 #define CONFIG_USB_OMAP3 1 133 #define CONFIG_TWL4030_USB 1 134 135 /* USB device configuration */ 136 #define CONFIG_USB_DEVICE 1 137 #define CONFIG_USB_TTY 1 138 /* Change these to suit your needs */ 139 #define CONFIG_USBD_VENDORID 0x0451 140 #define CONFIG_USBD_PRODUCTID 0x5678 141 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 142 #define CONFIG_USBD_PRODUCT_NAME "Zoom2" 143 144 /* commands to include */ 145 #include <config_cmd_default.h> 146 147 #define CONFIG_CMD_FAT /* FAT support */ 148 #define CONFIG_CMD_I2C /* I2C serial bus support */ 149 #define CONFIG_CMD_MMC /* MMC support */ 150 #define CONFIG_CMD_NAND /* NAND support */ 151 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ 152 153 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 154 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 155 #undef CONFIG_CMD_IMI /* iminfo */ 156 #undef CONFIG_CMD_IMLS /* List all found images */ 157 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 158 #undef CONFIG_CMD_NFS /* NFS support */ 159 160 #define CONFIG_SYS_NO_FLASH 161 #define CONFIG_HARD_I2C 1 162 #define CONFIG_SYS_I2C_SPEED 100000 163 #define CONFIG_SYS_I2C_SLAVE 1 164 #define CONFIG_SYS_I2C_BUS 0 165 #define CONFIG_SYS_I2C_BUS_SELECT 1 166 #define CONFIG_DRIVER_OMAP34XX_I2C 1 167 168 /* 169 * TWL4030 170 */ 171 #define CONFIG_TWL4030_POWER 1 172 #define CONFIG_TWL4030_LED 1 173 174 /* 175 * Board NAND Info. 176 */ 177 #define CONFIG_NAND_OMAP_GPMC 178 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 179 /* to access nand */ 180 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 181 /* to access nand at */ 182 /* CS0 */ 183 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 184 #define CONFIG_SYS_MAX_NAND_DEVICE 1 185 186 /* Environment information */ 187 #define CONFIG_BOOTDELAY 10 188 189 #define CONFIG_EXTRA_ENV_SETTINGS \ 190 "usbtty=cdc_acm\0" \ 191 192 /* 193 * Miscellaneous configurable options 194 */ 195 196 #define CONFIG_SYS_PROMPT "OMAP3 Zoom2 # " 197 #define CONFIG_SYS_LONGHELP 198 #define CONFIG_SYS_CBSIZE 256 199 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 200 sizeof(CONFIG_SYS_PROMPT) + 16) 201 #define CONFIG_SYS_MAXARGS 16 202 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 203 /* Memtest from start of memory to 31MB */ 204 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 205 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000) 206 /* The default load address is the start of memory */ 207 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) 208 /* everything, incl board info, in Hz */ 209 #undef CONFIG_SYS_CLKS_IN_HZ 210 /* 211 * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by 212 * 32KHz clk, or from external sig. This rate is divided by a local divisor. 213 */ 214 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 215 #define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ 216 #define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) 217 218 /*----------------------------------------------------------------------- 219 * Stack sizes 220 * 221 * The stack sizes are set up in start.S using these settings 222 */ 223 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 224 #ifdef CONFIG_USE_IRQ 225 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 226 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 227 #endif 228 229 /*----------------------------------------------------------------------- 230 * Physical Memory Map 231 */ 232 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 233 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 234 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 235 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 236 237 /* SDRAM Bank Allocation method */ 238 #define SDRC_R_B_C 1 239 240 /*----------------------------------------------------------------------- 241 * FLASH and environment organization 242 */ 243 244 /* **** PISMO SUPPORT *** */ 245 246 /* Configure the PISMO */ 247 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 248 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 249 250 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 251 /* one chip */ 252 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 253 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 254 255 #define CONFIG_SYS_FLASH_BASE boot_flash_base 256 257 /* Monitor at start of flash */ 258 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 259 260 #define CONFIG_ENV_IS_IN_NAND 1 261 #define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */ 262 263 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 264 #define CONFIG_ENV_OFFSET boot_flash_off 265 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 266 267 /*----------------------------------------------------------------------- 268 * CFI FLASH driver setup 269 */ 270 /* timeout values are in ticks */ 271 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 272 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 273 274 #ifndef __ASSEMBLY__ 275 extern unsigned int boot_flash_base; 276 extern volatile unsigned int boot_flash_env_addr; 277 extern unsigned int boot_flash_off; 278 extern unsigned int boot_flash_sec; 279 extern unsigned int boot_flash_type; 280 #endif 281 282 #endif /* __CONFIG_H */ 283