1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2016 Carlo Caione <carlo@caione.org> 4 */ 5 6 #ifndef __SD_EMMC_H__ 7 #define __SD_EMMC_H__ 8 9 #include <mmc.h> 10 11 #define SDIO_PORT_A 0 12 #define SDIO_PORT_B 1 13 #define SDIO_PORT_C 2 14 15 #define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */ 16 #define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */ 17 18 #define MESON_SD_EMMC_CLOCK 0x00 19 #define CLK_MAX_DIV 63 20 #define CLK_SRC_24M (0 << 6) 21 #define CLK_SRC_DIV2 (1 << 6) 22 #define CLK_CO_PHASE_000 (0 << 8) 23 #define CLK_CO_PHASE_090 (1 << 8) 24 #define CLK_CO_PHASE_180 (2 << 8) 25 #define CLK_CO_PHASE_270 (3 << 8) 26 #define CLK_TX_PHASE_000 (0 << 10) 27 #define CLK_TX_PHASE_090 (1 << 10) 28 #define CLK_TX_PHASE_180 (2 << 10) 29 #define CLK_TX_PHASE_270 (3 << 10) 30 #define CLK_ALWAYS_ON BIT(24) 31 32 #define MESON_SD_EMMC_CFG 0x44 33 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 34 #define CFG_BUS_WIDTH_1 0 35 #define CFG_BUS_WIDTH_4 1 36 #define CFG_BUS_WIDTH_8 2 37 #define CFG_BL_LEN_MASK GENMASK(7, 4) 38 #define CFG_BL_LEN_SHIFT 4 39 #define CFG_BL_LEN_512 (9 << 4) 40 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 41 #define CFG_RESP_TIMEOUT_256 (8 << 8) 42 #define CFG_RC_CC_MASK GENMASK(15, 12) 43 #define CFG_RC_CC_16 (4 << 12) 44 #define CFG_SDCLK_ALWAYS_ON BIT(18) 45 #define CFG_AUTO_CLK BIT(23) 46 47 #define MESON_SD_EMMC_STATUS 0x48 48 #define STATUS_MASK GENMASK(15, 0) 49 #define STATUS_ERR_MASK GENMASK(12, 0) 50 #define STATUS_RXD_ERR_MASK GENMASK(7, 0) 51 #define STATUS_TXD_ERR BIT(8) 52 #define STATUS_DESC_ERR BIT(9) 53 #define STATUS_RESP_ERR BIT(10) 54 #define STATUS_RESP_TIMEOUT BIT(11) 55 #define STATUS_DESC_TIMEOUT BIT(12) 56 #define STATUS_END_OF_CHAIN BIT(13) 57 58 #define MESON_SD_EMMC_IRQ_EN 0x4c 59 60 #define MESON_SD_EMMC_CMD_CFG 0x50 61 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 62 #define CMD_CFG_BLOCK_MODE BIT(9) 63 #define CMD_CFG_R1B BIT(10) 64 #define CMD_CFG_END_OF_CHAIN BIT(11) 65 #define CMD_CFG_TIMEOUT_4S (12 << 12) 66 #define CMD_CFG_NO_RESP BIT(16) 67 #define CMD_CFG_DATA_IO BIT(18) 68 #define CMD_CFG_DATA_WR BIT(19) 69 #define CMD_CFG_RESP_NOCRC BIT(20) 70 #define CMD_CFG_RESP_128 BIT(21) 71 #define CMD_CFG_CMD_INDEX_SHIFT 24 72 #define CMD_CFG_OWNER BIT(31) 73 74 #define MESON_SD_EMMC_CMD_ARG 0x54 75 #define MESON_SD_EMMC_CMD_DAT 0x58 76 #define MESON_SD_EMMC_CMD_RSP 0x5c 77 #define MESON_SD_EMMC_CMD_RSP1 0x60 78 #define MESON_SD_EMMC_CMD_RSP2 0x64 79 #define MESON_SD_EMMC_CMD_RSP3 0x68 80 81 struct meson_mmc_platdata { 82 struct mmc_config cfg; 83 struct mmc mmc; 84 void *regbase; 85 void *w_buf; 86 }; 87 88 #endif 89