1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
4 *
5 */
6
7 #include <common.h>
8 #include <watchdog.h>
9 #include <asm/immap.h>
10 #include <asm/io.h>
11
12 #if defined(CONFIG_M5307)
13 /*
14 * Simple mcf5307 chip select module init.
15 *
16 * Note: this chip has an issue reported in the device "errata":
17 * MCF5307ER Rev 4.2 reports @ section 35:
18 * Corrupted Return PC in Exception Stack Frame
19 * When processing an autovectored interrupt an error can occur that
20 * causes 0xFFFFFFFF to be written as the return PC value in the
21 * exception stack frame. The problem is caused by a conflict between
22 * an internal autovector access and a chip select mapped to the IACK
23 * address space (0xFFFFXXXX).
24 * Workaround:
25 * Set the C/I bit in the chip select mask register (CSMR) for the
26 * chip select that is mapped to 0xFFFFXXXX.
27 * This will prevent the chip select from asserting for IACK accesses.
28 */
29
30 #define MCF5307_SP_ERR_FIX(cs_base, mask) \
31 do { \
32 if (((cs_base<<16)+(in_be32(&mask)&0xffff0000)) >= \
33 0xffff0000) \
34 setbits_be32(&mask, CSMR_CI); \
35 } while (0)
36
init_csm(void)37 void init_csm(void)
38 {
39 csm_t *csm = (csm_t *)(MMAP_CSM);
40
41 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
42 defined(CONFIG_SYS_CS0_CTRL))
43 out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
44 out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
45 out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
46 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
47 #else
48 #warning "Chip Select 0 are not initialized/used"
49 #endif
50 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
51 defined(CONFIG_SYS_CS1_CTRL))
52 out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
53 out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
54 out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
55 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
56 #endif
57 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
58 defined(CONFIG_SYS_CS2_CTRL))
59 out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
60 out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
61 out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
62 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
63 #endif
64 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
65 defined(CONFIG_SYS_CS3_CTRL))
66 out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
67 out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
68 out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
69 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
70 #endif
71 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
72 defined(CONFIG_SYS_CS4_CTRL))
73 out_be16(&csm->csar4, CONFIG_SYS_CS4_BASE);
74 out_be32(&csm->csmr4, CONFIG_SYS_CS4_MASK);
75 out_be16(&csm->cscr4, CONFIG_SYS_CS4_CTRL);
76 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE, csm->csmr4);
77 #endif
78 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && \
79 defined(CONFIG_SYS_CS5_CTRL))
80 out_be16(&csm->csar5, CONFIG_SYS_CS5_BASE);
81 out_be32(&csm->csmr5, CONFIG_SYS_CS5_MASK);
82 out_be16(&csm->cscr5, CONFIG_SYS_CS5_CTRL);
83 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE, csm->csmr5);
84 #endif
85 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && \
86 defined(CONFIG_SYS_CS6_CTRL))
87 out_be16(&csm->csar6, CONFIG_SYS_CS6_BASE);
88 out_be32(&csm->csmr6, CONFIG_SYS_CS6_MASK);
89 out_be16(&csm->cscr6, CONFIG_SYS_CS6_CTRL);
90 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE, csm->csmr6);
91 #endif
92 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && \
93 defined(CONFIG_SYS_CS7_CTRL))
94 out_be16(&csm->csar7, CONFIG_SYS_CS7_BASE);
95 out_be32(&csm->csmr7, CONFIG_SYS_CS7_MASK);
96 out_be16(&csm->cscr7, CONFIG_SYS_CS7_CTRL);
97 MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE, csm->csmr7);
98 #endif
99 }
100
101 /*
102 * Set up the memory map and initialize registers
103 */
cpu_init_f(void)104 void cpu_init_f(void)
105 {
106 sim_t *sim = (sim_t *)(MMAP_SIM);
107
108 out_8(&sim->sypcr, 0x00);
109 out_8(&sim->swivr, 0x0f);
110 out_8(&sim->swsr, 0x00);
111 out_8(&sim->mpark, 0x00);
112
113 intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
114
115 /* timer 2 not masked */
116 out_be32(&icr->imr, 0xfffffbff);
117
118 out_8(&icr->icr0, 0x00); /* sw watchdog */
119 out_8(&icr->icr1, 0x00); /* timer 1 */
120 out_8(&icr->icr2, 0x88); /* timer 2 */
121 out_8(&icr->icr3, 0x00); /* i2c */
122 out_8(&icr->icr4, 0x00); /* uart 0 */
123 out_8(&icr->icr5, 0x00); /* uart 1 */
124 out_8(&icr->icr6, 0x00); /* dma 0 */
125 out_8(&icr->icr7, 0x00); /* dma 1 */
126 out_8(&icr->icr8, 0x00); /* dma 2 */
127 out_8(&icr->icr9, 0x00); /* dma 3 */
128
129 /* Chipselect Init */
130 init_csm();
131
132 /* enable data/instruction cache now */
133 icache_enable();
134 }
135
136 /*
137 * initialize higher level parts of CPU like timers
138 */
cpu_init_r(void)139 int cpu_init_r(void)
140 {
141 return 0;
142 }
143
uart_port_conf(int port)144 void uart_port_conf(int port)
145 {
146 }
147
arch_preboot_os(void)148 void arch_preboot_os(void)
149 {
150 /*
151 * OS can change interrupt offsets and are about to boot the OS so
152 * we need to make sure we disable all async interrupts.
153 */
154 intctrl_t *icr = (intctrl_t *)(MMAP_INTC);
155
156 out_8(&icr->icr1, 0x00); /* timer 1 */
157 out_8(&icr->icr2, 0x00); /* timer 2 */
158 }
159 #endif
160