1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * sh_eth.h - Driver for Renesas SuperH ethernet controller.
4 *
5 * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
6 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
7 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8 */
9
10 #include <netdev.h>
11 #include <asm/types.h>
12
13 #define SHETHER_NAME "sh_eth"
14
15 #if defined(CONFIG_SH)
16 /* Malloc returns addresses in the P1 area (cacheable). However we need to
17 use area P2 (non-cacheable) */
18 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
19
20 /* The ethernet controller needs to use physical addresses */
21 #if defined(CONFIG_SH_32BIT)
22 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
23 #else
24 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
25 #endif
26 #elif defined(CONFIG_ARM)
27 #ifndef inl
28 #define inl readl
29 #define outl writel
30 #endif
31 #define ADDR_TO_PHY(addr) ((int)(addr))
32 #define ADDR_TO_P2(addr) (addr)
33 #endif /* defined(CONFIG_SH) */
34
35 /* base padding size is 16 */
36 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
37 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16
38 #endif
39
40 /* Number of supported ports */
41 #define MAX_PORT_NUM 2
42
43 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
44 buffers must be a multiple of 32 bytes */
45 #define MAX_BUF_SIZE (48 * 32)
46
47 /* The number of tx descriptors must be large enough to point to 5 or more
48 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
49 We use one descriptor per frame */
50 #define NUM_TX_DESC 8
51
52 /* The size of the tx descriptor is determined by how much padding is used.
53 4, 20, or 52 bytes of padding can be used */
54 #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
55
56 /* Tx descriptor. We always use 3 bytes of padding */
57 struct tx_desc_s {
58 volatile u32 td0;
59 u32 td1;
60 u32 td2; /* Buffer start */
61 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
62 };
63
64 /* There is no limitation in the number of rx descriptors */
65 #define NUM_RX_DESC 8
66
67 /* The size of the rx descriptor is determined by how much padding is used.
68 4, 20, or 52 bytes of padding can be used */
69 #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
70 /* aligned cache line size */
71 #define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
72
73 /* Rx descriptor. We always use 4 bytes of padding */
74 struct rx_desc_s {
75 volatile u32 rd0;
76 volatile u32 rd1;
77 u32 rd2; /* Buffer start */
78 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
79 };
80
81 struct sh_eth_info {
82 struct tx_desc_s *tx_desc_alloc;
83 struct tx_desc_s *tx_desc_base;
84 struct tx_desc_s *tx_desc_cur;
85 struct rx_desc_s *rx_desc_alloc;
86 struct rx_desc_s *rx_desc_base;
87 struct rx_desc_s *rx_desc_cur;
88 u8 *rx_buf_alloc;
89 u8 *rx_buf_base;
90 u8 mac_addr[6];
91 u8 phy_addr;
92 struct eth_device *dev;
93 struct phy_device *phydev;
94 void __iomem *iobase;
95 };
96
97 struct sh_eth_dev {
98 int port;
99 struct sh_eth_info port_info[MAX_PORT_NUM];
100 };
101
102 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */
103 enum {
104 /* E-DMAC registers */
105 EDSR = 0,
106 EDMR,
107 EDTRR,
108 EDRRR,
109 EESR,
110 EESIPR,
111 TDLAR,
112 TDFAR,
113 TDFXR,
114 TDFFR,
115 RDLAR,
116 RDFAR,
117 RDFXR,
118 RDFFR,
119 TRSCER,
120 RMFCR,
121 TFTR,
122 FDR,
123 RMCR,
124 EDOCR,
125 TFUCR,
126 RFOCR,
127 FCFTR,
128 RPADIR,
129 TRIMD,
130 RBWAR,
131 TBRAR,
132
133 /* Ether registers */
134 ECMR,
135 ECSR,
136 ECSIPR,
137 PIR,
138 PSR,
139 RDMLR,
140 PIPR,
141 RFLR,
142 IPGR,
143 APR,
144 MPR,
145 PFTCR,
146 PFRCR,
147 RFCR,
148 RFCF,
149 TPAUSER,
150 TPAUSECR,
151 BCFR,
152 BCFRR,
153 GECMR,
154 BCULR,
155 MAHR,
156 MALR,
157 TROCR,
158 CDCR,
159 LCCR,
160 CNDCR,
161 CEFCR,
162 FRECR,
163 TSFRCR,
164 TLFRCR,
165 CERCR,
166 CEECR,
167 RMIIMR, /* R8A7790 */
168 MAFCR,
169 RTRATE,
170 CSMR,
171 RMII_MII,
172
173 /* This value must be written at last. */
174 SH_ETH_MAX_REGISTER_OFFSET,
175 };
176
177 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
178 [EDSR] = 0x0000,
179 [EDMR] = 0x0400,
180 [EDTRR] = 0x0408,
181 [EDRRR] = 0x0410,
182 [EESR] = 0x0428,
183 [EESIPR] = 0x0430,
184 [TDLAR] = 0x0010,
185 [TDFAR] = 0x0014,
186 [TDFXR] = 0x0018,
187 [TDFFR] = 0x001c,
188 [RDLAR] = 0x0030,
189 [RDFAR] = 0x0034,
190 [RDFXR] = 0x0038,
191 [RDFFR] = 0x003c,
192 [TRSCER] = 0x0438,
193 [RMFCR] = 0x0440,
194 [TFTR] = 0x0448,
195 [FDR] = 0x0450,
196 [RMCR] = 0x0458,
197 [RPADIR] = 0x0460,
198 [FCFTR] = 0x0468,
199 [CSMR] = 0x04E4,
200
201 [ECMR] = 0x0500,
202 [ECSR] = 0x0510,
203 [ECSIPR] = 0x0518,
204 [PIR] = 0x0520,
205 [PSR] = 0x0528,
206 [PIPR] = 0x052c,
207 [RFLR] = 0x0508,
208 [APR] = 0x0554,
209 [MPR] = 0x0558,
210 [PFTCR] = 0x055c,
211 [PFRCR] = 0x0560,
212 [TPAUSER] = 0x0564,
213 [GECMR] = 0x05b0,
214 [BCULR] = 0x05b4,
215 [MAHR] = 0x05c0,
216 [MALR] = 0x05c8,
217 [TROCR] = 0x0700,
218 [CDCR] = 0x0708,
219 [LCCR] = 0x0710,
220 [CEFCR] = 0x0740,
221 [FRECR] = 0x0748,
222 [TSFRCR] = 0x0750,
223 [TLFRCR] = 0x0758,
224 [RFCR] = 0x0760,
225 [CERCR] = 0x0768,
226 [CEECR] = 0x0770,
227 [MAFCR] = 0x0778,
228 [RMII_MII] = 0x0790,
229 };
230
231 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
232 [ECMR] = 0x0100,
233 [RFLR] = 0x0108,
234 [ECSR] = 0x0110,
235 [ECSIPR] = 0x0118,
236 [PIR] = 0x0120,
237 [PSR] = 0x0128,
238 [RDMLR] = 0x0140,
239 [IPGR] = 0x0150,
240 [APR] = 0x0154,
241 [MPR] = 0x0158,
242 [TPAUSER] = 0x0164,
243 [RFCF] = 0x0160,
244 [TPAUSECR] = 0x0168,
245 [BCFRR] = 0x016c,
246 [MAHR] = 0x01c0,
247 [MALR] = 0x01c8,
248 [TROCR] = 0x01d0,
249 [CDCR] = 0x01d4,
250 [LCCR] = 0x01d8,
251 [CNDCR] = 0x01dc,
252 [CEFCR] = 0x01e4,
253 [FRECR] = 0x01e8,
254 [TSFRCR] = 0x01ec,
255 [TLFRCR] = 0x01f0,
256 [RFCR] = 0x01f4,
257 [MAFCR] = 0x01f8,
258 [RTRATE] = 0x01fc,
259
260 [EDMR] = 0x0000,
261 [EDTRR] = 0x0008,
262 [EDRRR] = 0x0010,
263 [TDLAR] = 0x0018,
264 [RDLAR] = 0x0020,
265 [EESR] = 0x0028,
266 [EESIPR] = 0x0030,
267 [TRSCER] = 0x0038,
268 [RMFCR] = 0x0040,
269 [TFTR] = 0x0048,
270 [FDR] = 0x0050,
271 [RMCR] = 0x0058,
272 [TFUCR] = 0x0064,
273 [RFOCR] = 0x0068,
274 [RMIIMR] = 0x006C,
275 [FCFTR] = 0x0070,
276 [RPADIR] = 0x0078,
277 [TRIMD] = 0x007c,
278 [RBWAR] = 0x00c8,
279 [RDFAR] = 0x00cc,
280 [TBRAR] = 0x00d4,
281 [TDFAR] = 0x00d8,
282 };
283
284 /* Register Address */
285 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
286 #define SH_ETH_TYPE_GETHER
287 #define BASE_IO_ADDR 0xfee00000
288 #elif defined(CONFIG_CPU_SH7757) || \
289 defined(CONFIG_CPU_SH7752) || \
290 defined(CONFIG_CPU_SH7753)
291 #if defined(CONFIG_SH_ETHER_USE_GETHER)
292 #define SH_ETH_TYPE_GETHER
293 #define BASE_IO_ADDR 0xfee00000
294 #else
295 #define SH_ETH_TYPE_ETHER
296 #define BASE_IO_ADDR 0xfef00000
297 #endif
298 #elif defined(CONFIG_CPU_SH7724)
299 #define SH_ETH_TYPE_ETHER
300 #define BASE_IO_ADDR 0xA4600000
301 #elif defined(CONFIG_R8A7740)
302 #define SH_ETH_TYPE_GETHER
303 #define BASE_IO_ADDR 0xE9A00000
304 #elif defined(CONFIG_RCAR_GEN2)
305 #define SH_ETH_TYPE_ETHER
306 #define BASE_IO_ADDR 0xEE700200
307 #elif defined(CONFIG_R7S72100)
308 #define SH_ETH_TYPE_RZ
309 #define BASE_IO_ADDR 0xE8203000
310 #endif
311
312 /*
313 * Register's bits
314 * Copy from Linux driver source code
315 */
316 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
317 /* EDSR */
318 enum EDSR_BIT {
319 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
320 };
321 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
322 #endif
323
324 /* EDMR */
325 enum DMAC_M_BIT {
326 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
327 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
328 EDMR_SRST = 0x03, /* Receive/Send reset */
329 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
330 EDMR_EL = 0x40, /* Litte endian */
331 #elif defined(SH_ETH_TYPE_ETHER)
332 EDMR_SRST = 0x01,
333 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
334 EDMR_EL = 0x40, /* Litte endian */
335 #else
336 EDMR_SRST = 0x01,
337 #endif
338 };
339
340 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
341 # define EMDR_DESC EDMR_DL1
342 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
343 # define EMDR_DESC EDMR_DL0
344 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
345 # define EMDR_DESC 0
346 #endif
347
348 /* RFLR */
349 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
350
351 /* EDTRR */
352 enum DMAC_T_BIT {
353 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
354 EDTRR_TRNS = 0x03,
355 #else
356 EDTRR_TRNS = 0x01,
357 #endif
358 };
359
360 /* GECMR */
361 enum GECMR_BIT {
362 #if defined(CONFIG_CPU_SH7757) || \
363 defined(CONFIG_CPU_SH7752) || \
364 defined(CONFIG_CPU_SH7753)
365 GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
366 #else
367 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
368 #endif
369 };
370
371 /* EDRRR*/
372 enum EDRRR_R_BIT {
373 EDRRR_R = 0x01,
374 };
375
376 /* TPAUSER */
377 enum TPAUSER_BIT {
378 TPAUSER_TPAUSE = 0x0000ffff,
379 TPAUSER_UNLIMITED = 0,
380 };
381
382 /* BCFR */
383 enum BCFR_BIT {
384 BCFR_RPAUSE = 0x0000ffff,
385 BCFR_UNLIMITED = 0,
386 };
387
388 /* PIR */
389 enum PIR_BIT {
390 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
391 };
392
393 /* PSR */
394 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
395
396 /* EESR */
397 enum EESR_BIT {
398 #if defined(SH_ETH_TYPE_ETHER)
399 EESR_TWB = 0x40000000,
400 #else
401 EESR_TWB = 0xC0000000,
402 EESR_TC1 = 0x20000000,
403 EESR_TUC = 0x10000000,
404 EESR_ROC = 0x80000000,
405 #endif
406 EESR_TABT = 0x04000000,
407 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
408 #if defined(SH_ETH_TYPE_ETHER)
409 EESR_ADE = 0x00800000,
410 #endif
411 EESR_ECI = 0x00400000,
412 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
413 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
414 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
415 #if defined(SH_ETH_TYPE_ETHER)
416 EESR_CND = 0x00000800,
417 #endif
418 EESR_DLC = 0x00000400,
419 EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
420 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
421 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
422 EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
423 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
424 };
425
426
427 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
428 # define TX_CHECK (EESR_TC1 | EESR_FTC)
429 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
430 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
431 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
432
433 #else
434 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
435 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
436 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
437 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
438 #endif
439
440 /* EESIPR */
441 enum DMAC_IM_BIT {
442 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
443 DMAC_M_RABT = 0x02000000,
444 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
445 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
446 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
447 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
448 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
449 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
450 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
451 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
452 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
453 DMAC_M_RINT1 = 0x00000001,
454 };
455
456 /* Receive descriptor bit */
457 enum RD_STS_BIT {
458 RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
459 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
460 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
461 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
462 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
463 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
464 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
465 RD_RFS1 = 0x00000001,
466 };
467 #define RDF1ST RD_RFP1
468 #define RDFEND RD_RFP0
469 #define RD_RFP (RD_RFP1|RD_RFP0)
470
471 /* RDFFR*/
472 enum RDFFR_BIT {
473 RDFFR_RDLF = 0x01,
474 };
475
476 /* FCFTR */
477 enum FCFTR_BIT {
478 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
479 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
480 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
481 };
482 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
483 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
484
485 /* Transfer descriptor bit */
486 enum TD_STS_BIT {
487 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
488 defined(SH_ETH_TYPE_RZ)
489 TD_TACT = 0x80000000,
490 #else
491 TD_TACT = 0x7fffffff,
492 #endif
493 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
494 TD_TFP0 = 0x10000000,
495 };
496 #define TDF1ST TD_TFP1
497 #define TDFEND TD_TFP0
498 #define TD_TFP (TD_TFP1|TD_TFP0)
499
500 /* RMCR */
501 enum RECV_RST_BIT { RMCR_RST = 0x01, };
502 /* ECMR */
503 enum FELIC_MODE_BIT {
504 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
505 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
506 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
507 #endif
508 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
509 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
510 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
511 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
512 ECMR_PRM = 0x00000001,
513 #ifdef CONFIG_CPU_SH7724
514 ECMR_RTM = 0x00000010,
515 #elif defined(CONFIG_RCAR_GEN2)
516 ECMR_RTM = 0x00000004,
517 #endif
518
519 };
520
521 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
522 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
523 ECMR_RXF | ECMR_TXF | ECMR_MCT)
524 #elif defined(SH_ETH_TYPE_ETHER)
525 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
526 #else
527 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
528 #endif
529
530 /* ECSR */
531 enum ECSR_STATUS_BIT {
532 #if defined(SH_ETH_TYPE_ETHER)
533 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
534 #endif
535 ECSR_LCHNG = 0x04,
536 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
537 };
538
539 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
540 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
541 #else
542 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
543 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
544 #endif
545
546 /* ECSIPR */
547 enum ECSIPR_STATUS_MASK_BIT {
548 #if defined(SH_ETH_TYPE_ETHER)
549 ECSIPR_BRCRXIP = 0x20,
550 ECSIPR_PSRTOIP = 0x10,
551 #elif defined(SH_ETY_TYPE_GETHER)
552 ECSIPR_PSRTOIP = 0x10,
553 ECSIPR_PHYIP = 0x08,
554 #endif
555 ECSIPR_LCHNGIP = 0x04,
556 ECSIPR_MPDIP = 0x02,
557 ECSIPR_ICDIP = 0x01,
558 };
559
560 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
561 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
562 #else
563 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
564 ECSIPR_ICDIP | ECSIPR_MPDIP)
565 #endif
566
567 /* APR */
568 enum APR_BIT {
569 APR_AP = 0x00000004,
570 };
571
572 /* MPR */
573 enum MPR_BIT {
574 MPR_MP = 0x00000006,
575 };
576
577 /* TRSCER */
578 enum DESC_I_BIT {
579 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
580 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
581 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
582 DESC_I_RINT1 = 0x0001,
583 };
584
585 /* RPADIR */
586 enum RPADIR_BIT {
587 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
588 RPADIR_PADR = 0x0003f,
589 };
590
591 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
592 # define RPADIR_INIT (0x00)
593 #else
594 # define RPADIR_INIT (RPADIR_PADS1)
595 #endif
596
597 /* FDR */
598 enum FIFO_SIZE_BIT {
599 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
600 };
601
sh_eth_reg_addr(struct sh_eth_info * port,int enum_index)602 static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
603 int enum_index)
604 {
605 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
606 const u16 *reg_offset = sh_eth_offset_gigabit;
607 #elif defined(SH_ETH_TYPE_ETHER)
608 const u16 *reg_offset = sh_eth_offset_fast_sh4;
609 #else
610 #error
611 #endif
612 return (unsigned long)port->iobase + reg_offset[enum_index];
613 }
614
sh_eth_write(struct sh_eth_info * port,unsigned long data,int enum_index)615 static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
616 int enum_index)
617 {
618 outl(data, sh_eth_reg_addr(port, enum_index));
619 }
620
sh_eth_read(struct sh_eth_info * port,int enum_index)621 static inline unsigned long sh_eth_read(struct sh_eth_info *port,
622 int enum_index)
623 {
624 return inl(sh_eth_reg_addr(port, enum_index));
625 }
626