1 /* SRMMU page table defines and code,
2 * taken from the SPARC port of Linux
3 *
4 * Copyright (C) 2007 Daniel Hellstrom (daniel@gaisler.com)
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24 #ifndef __SPARC_SRMMU_H__
25 #define __SPARC_SRMMU_H__
26
27 #include <asm/asi.h>
28 #include <asm/page.h>
29
30 /* Number of contexts is implementation-dependent; 64k is the most we support */
31 #define SRMMU_MAX_CONTEXTS 65536
32
33 /* PMD_SHIFT determines the size of the area a second-level page table entry can map */
34 #define SRMMU_REAL_PMD_SHIFT 18
35 #define SRMMU_REAL_PMD_SIZE (1UL << SRMMU_REAL_PMD_SHIFT)
36 #define SRMMU_REAL_PMD_MASK (~(SRMMU_REAL_PMD_SIZE-1))
37 #define SRMMU_REAL_PMD_ALIGN(__addr) (((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK)
38
39 /* PGDIR_SHIFT determines what a third-level page table entry can map */
40 #define SRMMU_PGDIR_SHIFT 24
41 #define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT)
42 #define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1))
43 #define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
44
45 #define SRMMU_REAL_PTRS_PER_PTE 64
46 #define SRMMU_REAL_PTRS_PER_PMD 64
47 #define SRMMU_PTRS_PER_PGD 256
48
49 #define SRMMU_REAL_PTE_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PTE*4)
50 #define SRMMU_PMD_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PMD*4)
51 #define SRMMU_PGD_TABLE_SIZE (SRMMU_PTRS_PER_PGD*4)
52
53 /*
54 * To support pagetables in highmem, Linux introduces APIs which
55 * return struct page* and generally manipulate page tables when
56 * they are not mapped into kernel space. Our hardware page tables
57 * are smaller than pages. We lump hardware tabes into big, page sized
58 * software tables.
59 *
60 * PMD_SHIFT determines the size of the area a second-level page table entry
61 * can map, and our pmd_t is 16 times larger than normal. The values which
62 * were once defined here are now generic for 4c and srmmu, so they're
63 * found in pgtable.h.
64 */
65 #define SRMMU_PTRS_PER_PMD 4
66
67 /* Definition of the values in the ET field of PTD's and PTE's */
68 #define SRMMU_ET_MASK 0x3
69 #define SRMMU_ET_INVALID 0x0
70 #define SRMMU_ET_PTD 0x1
71 #define SRMMU_ET_PTE 0x2
72 #define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */
73
74 /* Physical page extraction from PTP's and PTE's. */
75 #define SRMMU_CTX_PMASK 0xfffffff0
76 #define SRMMU_PTD_PMASK 0xfffffff0
77 #define SRMMU_PTE_PMASK 0xffffff00
78
79 /* The pte non-page bits. Some notes:
80 * 1) cache, dirty, valid, and ref are frobbable
81 * for both supervisor and user pages.
82 * 2) exec and write will only give the desired effect
83 * on user pages
84 * 3) use priv and priv_readonly for changing the
85 * characteristics of supervisor ptes
86 */
87 #define SRMMU_CACHE 0x80
88 #define SRMMU_DIRTY 0x40
89 #define SRMMU_REF 0x20
90 #define SRMMU_NOREAD 0x10
91 #define SRMMU_EXEC 0x08
92 #define SRMMU_WRITE 0x04
93 #define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */
94 #define SRMMU_PRIV 0x1c
95 #define SRMMU_PRIV_RDONLY 0x18
96
97 #define SRMMU_FILE 0x40 /* Implemented in software */
98
99 #define SRMMU_PTE_FILE_SHIFT 8 /* == 32-PTE_FILE_MAX_BITS */
100
101 #define SRMMU_CHG_MASK (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
102
103 /* SRMMU swap entry encoding
104 *
105 * We use 5 bits for the type and 19 for the offset. This gives us
106 * 32 swapfiles of 4GB each. Encoding looks like:
107 *
108 * oooooooooooooooooootttttRRRRRRRR
109 * fedcba9876543210fedcba9876543210
110 *
111 * The bottom 8 bits are reserved for protection and status bits, especially
112 * FILE and PRESENT.
113 */
114 #define SRMMU_SWP_TYPE_MASK 0x1f
115 #define SRMMU_SWP_TYPE_SHIFT SRMMU_PTE_FILE_SHIFT
116 #define SRMMU_SWP_OFF_MASK 0x7ffff
117 #define SRMMU_SWP_OFF_SHIFT (SRMMU_PTE_FILE_SHIFT + 5)
118
119 /* Some day I will implement true fine grained access bits for
120 * user pages because the SRMMU gives us the capabilities to
121 * enforce all the protection levels that vma's can have.
122 * XXX But for now...
123 */
124 #define SRMMU_PAGE_NONE __pgprot(SRMMU_CACHE | \
125 SRMMU_PRIV | SRMMU_REF)
126 #define SRMMU_PAGE_SHARED __pgprot(SRMMU_VALID | SRMMU_CACHE | \
127 SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
128 #define SRMMU_PAGE_COPY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
129 SRMMU_EXEC | SRMMU_REF)
130 #define SRMMU_PAGE_RDONLY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
131 SRMMU_EXEC | SRMMU_REF)
132 #define SRMMU_PAGE_KERNEL __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
133 SRMMU_DIRTY | SRMMU_REF)
134
135 /* SRMMU Register addresses in ASI 0x4. These are valid for all
136 * current SRMMU implementations that exist.
137 */
138 #define SRMMU_CTRL_REG 0x00000000
139 #define SRMMU_CTXTBL_PTR 0x00000100
140 #define SRMMU_CTX_REG 0x00000200
141 #define SRMMU_FAULT_STATUS 0x00000300
142 #define SRMMU_FAULT_ADDR 0x00000400
143
144 #define WINDOW_FLUSH(tmp1, tmp2) \
145 mov 0, tmp1; \
146 98: ld [%g6 + TI_UWINMASK], tmp2; \
147 orcc %g0, tmp2, %g0; \
148 add tmp1, 1, tmp1; \
149 bne 98b; \
150 save %sp, -64, %sp; \
151 99: subcc tmp1, 1, tmp1; \
152 bne 99b; \
153 restore %g0, %g0, %g0;
154
155 #ifndef __ASSEMBLY__
156
157 /* This makes sense. Honest it does - Anton */
158 /* XXX Yes but it's ugly as sin. FIXME. -KMW */
159 extern void *srmmu_nocache_pool;
160 #define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
161 #define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
162 #define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
163
164 /* Accessing the MMU control register. */
srmmu_get_mmureg(void)165 extern __inline__ unsigned int srmmu_get_mmureg(void)
166 {
167 unsigned int retval;
168 __asm__ __volatile__("lda [%%g0] %1, %0\n\t":
169 "=r"(retval):"i"(ASI_M_MMUREGS));
170 return retval;
171 }
172
srmmu_set_mmureg(unsigned long regval)173 extern __inline__ void srmmu_set_mmureg(unsigned long regval)
174 {
175 __asm__ __volatile__("sta %0, [%%g0] %1\n\t"::"r"(regval),
176 "i"(ASI_M_MMUREGS):"memory");
177
178 }
179
srmmu_set_ctable_ptr(unsigned long paddr)180 extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr)
181 {
182 paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
183 __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(paddr),
184 "r"(SRMMU_CTXTBL_PTR),
185 "i"(ASI_M_MMUREGS):"memory");
186 }
187
srmmu_get_ctable_ptr(void)188 extern __inline__ unsigned long srmmu_get_ctable_ptr(void)
189 {
190 unsigned int retval;
191
192 __asm__ __volatile__("lda [%1] %2, %0\n\t":
193 "=r"(retval):
194 "r"(SRMMU_CTXTBL_PTR), "i"(ASI_M_MMUREGS));
195 return (retval & SRMMU_CTX_PMASK) << 4;
196 }
197
srmmu_set_context(int context)198 extern __inline__ void srmmu_set_context(int context)
199 {
200 __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(context),
201 "r"(SRMMU_CTX_REG), "i"(ASI_M_MMUREGS):"memory");
202 }
203
srmmu_get_context(void)204 extern __inline__ int srmmu_get_context(void)
205 {
206 register int retval;
207 __asm__ __volatile__("lda [%1] %2, %0\n\t":
208 "=r"(retval):
209 "r"(SRMMU_CTX_REG), "i"(ASI_M_MMUREGS));
210 return retval;
211 }
212
srmmu_get_fstatus(void)213 extern __inline__ unsigned int srmmu_get_fstatus(void)
214 {
215 unsigned int retval;
216
217 __asm__ __volatile__("lda [%1] %2, %0\n\t":
218 "=r"(retval):
219 "r"(SRMMU_FAULT_STATUS), "i"(ASI_M_MMUREGS));
220 return retval;
221 }
222
srmmu_get_faddr(void)223 extern __inline__ unsigned int srmmu_get_faddr(void)
224 {
225 unsigned int retval;
226
227 __asm__ __volatile__("lda [%1] %2, %0\n\t":
228 "=r"(retval):
229 "r"(SRMMU_FAULT_ADDR), "i"(ASI_M_MMUREGS));
230 return retval;
231 }
232
233 /* This is guaranteed on all SRMMU's. */
srmmu_flush_whole_tlb(void)234 extern __inline__ void srmmu_flush_whole_tlb(void)
235 {
236 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x400), /* Flush entire TLB!! */
237 "i"(ASI_M_FLUSH_PROBE):"memory");
238
239 }
240
241 /* These flush types are not available on all chips... */
srmmu_flush_tlb_ctx(void)242 extern __inline__ void srmmu_flush_tlb_ctx(void)
243 {
244 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x300), /* Flush TLB ctx.. */
245 "i"(ASI_M_FLUSH_PROBE):"memory");
246
247 }
248
srmmu_flush_tlb_region(unsigned long addr)249 extern __inline__ void srmmu_flush_tlb_region(unsigned long addr)
250 {
251 addr &= SRMMU_PGDIR_MASK;
252 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x200), /* Flush TLB region.. */
253 "i"(ASI_M_FLUSH_PROBE):"memory");
254
255 }
256
srmmu_flush_tlb_segment(unsigned long addr)257 extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr)
258 {
259 addr &= SRMMU_REAL_PMD_MASK;
260 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x100), /* Flush TLB segment.. */
261 "i"(ASI_M_FLUSH_PROBE):"memory");
262
263 }
264
srmmu_flush_tlb_page(unsigned long page)265 extern __inline__ void srmmu_flush_tlb_page(unsigned long page)
266 {
267 page &= PAGE_MASK;
268 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(page), /* Flush TLB page.. */
269 "i"(ASI_M_FLUSH_PROBE):"memory");
270
271 }
272
srmmu_hwprobe(unsigned long vaddr)273 extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr)
274 {
275 unsigned long retval;
276
277 vaddr &= PAGE_MASK;
278 __asm__ __volatile__("lda [%1] %2, %0\n\t":
279 "=r"(retval):
280 "r"(vaddr | 0x400), "i"(ASI_M_FLUSH_PROBE));
281
282 return retval;
283 }
284
srmmu_get_pte(unsigned long addr)285 extern __inline__ int srmmu_get_pte(unsigned long addr)
286 {
287 register unsigned long entry;
288
289 __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t":
290 "=r"(entry):
291 "r"((addr & 0xfffff000) | 0x400),
292 "i"(ASI_M_FLUSH_PROBE));
293 return entry;
294 }
295
296 extern unsigned long (*srmmu_read_physical) (unsigned long paddr);
297 extern void (*srmmu_write_physical) (unsigned long paddr, unsigned long word);
298
299 #endif /* !(__ASSEMBLY__) */
300
301 #endif /* !(__SPARC_SRMMU_H__) */
302