1 /*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright IBM Corp. 2012, 2018
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * Contributions after 2012-10-29 are licensed under the terms of the
18 * GNU GPL, version 2 or (at your option) any later version.
19 *
20 * You should have received a copy of the GNU (Lesser) General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #ifndef S390X_CPU_H
25 #define S390X_CPU_H
26
27 #include "qemu-common.h"
28 #include "cpu-qom.h"
29 #include "cpu_models.h"
30
31 #define TARGET_LONG_BITS 64
32
33 #define ELF_MACHINE_UNAME "S390X"
34
35 #define CPUArchState struct CPUS390XState
36
37 #include "exec/cpu-defs.h"
38 #define TARGET_PAGE_BITS 12
39
40 #define TARGET_PHYS_ADDR_SPACE_BITS 64
41 #define TARGET_VIRT_ADDR_SPACE_BITS 64
42
43 #include "exec/cpu-all.h"
44
45 #define NB_MMU_MODES 4
46 #define TARGET_INSN_START_EXTRA_WORDS 1
47
48 #define MMU_MODE0_SUFFIX _primary
49 #define MMU_MODE1_SUFFIX _secondary
50 #define MMU_MODE2_SUFFIX _home
51 #define MMU_MODE3_SUFFIX _real
52
53 #define MMU_USER_IDX 0
54
55 #define S390_MAX_CPUS 248
56
57 typedef struct PSW {
58 uint64_t mask;
59 uint64_t addr;
60 } PSW;
61
62 struct CPUS390XState {
63 uint64_t regs[16]; /* GP registers */
64 /*
65 * The floating point registers are part of the vector registers.
66 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
67 */
68 CPU_DoubleU vregs[32][2]; /* vector registers */
69 uint32_t aregs[16]; /* access registers */
70 uint8_t riccb[64]; /* runtime instrumentation control */
71 uint64_t gscb[4]; /* guarded storage control */
72 uint64_t etoken; /* etoken */
73 uint64_t etoken_extension; /* etoken extension */
74
75 /* Fields up to this point are not cleared by initial CPU reset */
76 struct {} start_initial_reset_fields;
77
78 uint32_t fpc; /* floating-point control register */
79 uint32_t cc_op;
80 bool bpbc; /* branch prediction blocking */
81
82 float_status fpu_status; /* passed to softfloat lib */
83
84 /* The low part of a 128-bit return, or remainder of a divide. */
85 uint64_t retxl;
86
87 PSW psw;
88
89 S390CrashReason crash_reason;
90
91 uint64_t cc_src;
92 uint64_t cc_dst;
93 uint64_t cc_vr;
94
95 uint64_t ex_value;
96
97 uint64_t __excp_addr;
98 uint64_t psa;
99
100 uint32_t int_pgm_code;
101 uint32_t int_pgm_ilen;
102
103 uint32_t int_svc_code;
104 uint32_t int_svc_ilen;
105
106 uint64_t per_address;
107 uint16_t per_perc_atmid;
108
109 uint64_t cregs[16]; /* control registers */
110
111 int pending_int;
112 uint16_t external_call_addr;
113 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
114
115 uint64_t ckc;
116 uint64_t cputm;
117 uint32_t todpr;
118
119 uint64_t pfault_token;
120 uint64_t pfault_compare;
121 uint64_t pfault_select;
122
123 uint64_t gbea;
124 uint64_t pp;
125
126 /* Fields up to this point are cleared by a CPU reset */
127 struct {} end_reset_fields;
128
129 CPU_COMMON
130
131 #if !defined(CONFIG_USER_ONLY)
132 uint32_t core_id; /* PoP "CPU address", same as cpu_index */
133 uint64_t cpuid;
134 #endif
135
136 QEMUTimer *tod_timer;
137
138 QEMUTimer *cpu_timer;
139
140 /*
141 * The cpu state represents the logical state of a cpu. In contrast to other
142 * architectures, there is a difference between a halt and a stop on s390.
143 * If all cpus are either stopped (including check stop) or in the disabled
144 * wait state, the vm can be shut down.
145 * The acceptable cpu_state values are defined in the CpuInfoS390State
146 * enum.
147 */
148 uint8_t cpu_state;
149
150 /* currently processed sigp order */
151 uint8_t sigp_order;
152
153 };
154
get_freg(CPUS390XState * cs,int nr)155 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
156 {
157 return &cs->vregs[nr][0];
158 }
159
160 /**
161 * S390CPU:
162 * @env: #CPUS390XState.
163 *
164 * An S/390 CPU.
165 */
166 struct S390CPU {
167 /*< private >*/
168 CPUState parent_obj;
169 /*< public >*/
170
171 CPUS390XState env;
172 S390CPUModel *model;
173 /* needed for live migration */
174 void *irqstate;
175 uint32_t irqstate_saved_size;
176 };
177
s390_env_get_cpu(CPUS390XState * env)178 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
179 {
180 return container_of(env, S390CPU, env);
181 }
182
183 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
184
185 #define ENV_OFFSET offsetof(S390CPU, env)
186
187 #ifndef CONFIG_USER_ONLY
188 extern const struct VMStateDescription vmstate_s390_cpu;
189 #endif
190
191 /* distinguish between 24 bit and 31 bit addressing */
192 #define HIGH_ORDER_BIT 0x80000000
193
194 /* Interrupt Codes */
195 /* Program Interrupts */
196 #define PGM_OPERATION 0x0001
197 #define PGM_PRIVILEGED 0x0002
198 #define PGM_EXECUTE 0x0003
199 #define PGM_PROTECTION 0x0004
200 #define PGM_ADDRESSING 0x0005
201 #define PGM_SPECIFICATION 0x0006
202 #define PGM_DATA 0x0007
203 #define PGM_FIXPT_OVERFLOW 0x0008
204 #define PGM_FIXPT_DIVIDE 0x0009
205 #define PGM_DEC_OVERFLOW 0x000a
206 #define PGM_DEC_DIVIDE 0x000b
207 #define PGM_HFP_EXP_OVERFLOW 0x000c
208 #define PGM_HFP_EXP_UNDERFLOW 0x000d
209 #define PGM_HFP_SIGNIFICANCE 0x000e
210 #define PGM_HFP_DIVIDE 0x000f
211 #define PGM_SEGMENT_TRANS 0x0010
212 #define PGM_PAGE_TRANS 0x0011
213 #define PGM_TRANS_SPEC 0x0012
214 #define PGM_SPECIAL_OP 0x0013
215 #define PGM_OPERAND 0x0015
216 #define PGM_TRACE_TABLE 0x0016
217 #define PGM_SPACE_SWITCH 0x001c
218 #define PGM_HFP_SQRT 0x001d
219 #define PGM_PC_TRANS_SPEC 0x001f
220 #define PGM_AFX_TRANS 0x0020
221 #define PGM_ASX_TRANS 0x0021
222 #define PGM_LX_TRANS 0x0022
223 #define PGM_EX_TRANS 0x0023
224 #define PGM_PRIM_AUTH 0x0024
225 #define PGM_SEC_AUTH 0x0025
226 #define PGM_ALET_SPEC 0x0028
227 #define PGM_ALEN_SPEC 0x0029
228 #define PGM_ALE_SEQ 0x002a
229 #define PGM_ASTE_VALID 0x002b
230 #define PGM_ASTE_SEQ 0x002c
231 #define PGM_EXT_AUTH 0x002d
232 #define PGM_STACK_FULL 0x0030
233 #define PGM_STACK_EMPTY 0x0031
234 #define PGM_STACK_SPEC 0x0032
235 #define PGM_STACK_TYPE 0x0033
236 #define PGM_STACK_OP 0x0034
237 #define PGM_ASCE_TYPE 0x0038
238 #define PGM_REG_FIRST_TRANS 0x0039
239 #define PGM_REG_SEC_TRANS 0x003a
240 #define PGM_REG_THIRD_TRANS 0x003b
241 #define PGM_MONITOR 0x0040
242 #define PGM_PER 0x0080
243 #define PGM_CRYPTO 0x0119
244
245 /* External Interrupts */
246 #define EXT_INTERRUPT_KEY 0x0040
247 #define EXT_CLOCK_COMP 0x1004
248 #define EXT_CPU_TIMER 0x1005
249 #define EXT_MALFUNCTION 0x1200
250 #define EXT_EMERGENCY 0x1201
251 #define EXT_EXTERNAL_CALL 0x1202
252 #define EXT_ETR 0x1406
253 #define EXT_SERVICE 0x2401
254 #define EXT_VIRTIO 0x2603
255
256 /* PSW defines */
257 #undef PSW_MASK_PER
258 #undef PSW_MASK_UNUSED_2
259 #undef PSW_MASK_DAT
260 #undef PSW_MASK_IO
261 #undef PSW_MASK_EXT
262 #undef PSW_MASK_KEY
263 #undef PSW_SHIFT_KEY
264 #undef PSW_MASK_MCHECK
265 #undef PSW_MASK_WAIT
266 #undef PSW_MASK_PSTATE
267 #undef PSW_MASK_ASC
268 #undef PSW_SHIFT_ASC
269 #undef PSW_MASK_CC
270 #undef PSW_MASK_PM
271 #undef PSW_SHIFT_MASK_PM
272 #undef PSW_MASK_64
273 #undef PSW_MASK_32
274 #undef PSW_MASK_ESA_ADDR
275
276 #define PSW_MASK_PER 0x4000000000000000ULL
277 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL
278 #define PSW_MASK_DAT 0x0400000000000000ULL
279 #define PSW_MASK_IO 0x0200000000000000ULL
280 #define PSW_MASK_EXT 0x0100000000000000ULL
281 #define PSW_MASK_KEY 0x00F0000000000000ULL
282 #define PSW_SHIFT_KEY 52
283 #define PSW_MASK_MCHECK 0x0004000000000000ULL
284 #define PSW_MASK_WAIT 0x0002000000000000ULL
285 #define PSW_MASK_PSTATE 0x0001000000000000ULL
286 #define PSW_MASK_ASC 0x0000C00000000000ULL
287 #define PSW_SHIFT_ASC 46
288 #define PSW_MASK_CC 0x0000300000000000ULL
289 #define PSW_MASK_PM 0x00000F0000000000ULL
290 #define PSW_SHIFT_MASK_PM 40
291 #define PSW_MASK_64 0x0000000100000000ULL
292 #define PSW_MASK_32 0x0000000080000000ULL
293 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
294
295 #undef PSW_ASC_PRIMARY
296 #undef PSW_ASC_ACCREG
297 #undef PSW_ASC_SECONDARY
298 #undef PSW_ASC_HOME
299
300 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
301 #define PSW_ASC_ACCREG 0x0000400000000000ULL
302 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
303 #define PSW_ASC_HOME 0x0000C00000000000ULL
304
305 /* the address space values shifted */
306 #define AS_PRIMARY 0
307 #define AS_ACCREG 1
308 #define AS_SECONDARY 2
309 #define AS_HOME 3
310
311 /* tb flags */
312
313 #define FLAG_MASK_PSW_SHIFT 31
314 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
315 #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT)
316 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
317 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
318 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
319 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
320 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
321 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
322
323 /* we'll use some unused PSW positions to store CR flags in tb flags */
324 #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
325
326 /* Control register 0 bits */
327 #define CR0_LOWPROT 0x0000000010000000ULL
328 #define CR0_SECONDARY 0x0000000004000000ULL
329 #define CR0_EDAT 0x0000000000800000ULL
330 #define CR0_AFP 0x0000000000040000ULL
331 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
332 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
333 #define CR0_CKC_SC 0x0000000000000800ULL
334 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL
335 #define CR0_SERVICE_SC 0x0000000000000200ULL
336
337 /* Control register 14 bits */
338 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL
339
340 /* MMU */
341 #define MMU_PRIMARY_IDX 0
342 #define MMU_SECONDARY_IDX 1
343 #define MMU_HOME_IDX 2
344 #define MMU_REAL_IDX 3
345
cpu_mmu_index(CPUS390XState * env,bool ifetch)346 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
347 {
348 if (!(env->psw.mask & PSW_MASK_DAT)) {
349 return MMU_REAL_IDX;
350 }
351
352 switch (env->psw.mask & PSW_MASK_ASC) {
353 case PSW_ASC_PRIMARY:
354 return MMU_PRIMARY_IDX;
355 case PSW_ASC_SECONDARY:
356 return MMU_SECONDARY_IDX;
357 case PSW_ASC_HOME:
358 return MMU_HOME_IDX;
359 case PSW_ASC_ACCREG:
360 /* Fallthrough: access register mode is not yet supported */
361 default:
362 abort();
363 }
364 }
365
cpu_get_tb_cpu_state(CPUS390XState * env,target_ulong * pc,target_ulong * cs_base,uint32_t * flags)366 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
367 target_ulong *cs_base, uint32_t *flags)
368 {
369 *pc = env->psw.addr;
370 *cs_base = env->ex_value;
371 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
372 if (env->cregs[0] & CR0_AFP) {
373 *flags |= FLAG_MASK_AFP;
374 }
375 }
376
377 /* PER bits from control register 9 */
378 #define PER_CR9_EVENT_BRANCH 0x80000000
379 #define PER_CR9_EVENT_IFETCH 0x40000000
380 #define PER_CR9_EVENT_STORE 0x20000000
381 #define PER_CR9_EVENT_STORE_REAL 0x08000000
382 #define PER_CR9_EVENT_NULLIFICATION 0x01000000
383 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
384 #define PER_CR9_CONTROL_ALTERATION 0x00200000
385
386 /* PER bits from the PER CODE/ATMID/AI in lowcore */
387 #define PER_CODE_EVENT_BRANCH 0x8000
388 #define PER_CODE_EVENT_IFETCH 0x4000
389 #define PER_CODE_EVENT_STORE 0x2000
390 #define PER_CODE_EVENT_STORE_REAL 0x0800
391 #define PER_CODE_EVENT_NULLIFICATION 0x0100
392
393 #define EXCP_EXT 1 /* external interrupt */
394 #define EXCP_SVC 2 /* supervisor call (syscall) */
395 #define EXCP_PGM 3 /* program interruption */
396 #define EXCP_RESTART 4 /* restart interrupt */
397 #define EXCP_STOP 5 /* stop interrupt */
398 #define EXCP_IO 7 /* I/O interrupt */
399 #define EXCP_MCHK 8 /* machine check */
400
401 #define INTERRUPT_EXT_CPU_TIMER (1 << 3)
402 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4)
403 #define INTERRUPT_EXTERNAL_CALL (1 << 5)
404 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6)
405 #define INTERRUPT_RESTART (1 << 7)
406 #define INTERRUPT_STOP (1 << 8)
407
408 /* Program Status Word. */
409 #define S390_PSWM_REGNUM 0
410 #define S390_PSWA_REGNUM 1
411 /* General Purpose Registers. */
412 #define S390_R0_REGNUM 2
413 #define S390_R1_REGNUM 3
414 #define S390_R2_REGNUM 4
415 #define S390_R3_REGNUM 5
416 #define S390_R4_REGNUM 6
417 #define S390_R5_REGNUM 7
418 #define S390_R6_REGNUM 8
419 #define S390_R7_REGNUM 9
420 #define S390_R8_REGNUM 10
421 #define S390_R9_REGNUM 11
422 #define S390_R10_REGNUM 12
423 #define S390_R11_REGNUM 13
424 #define S390_R12_REGNUM 14
425 #define S390_R13_REGNUM 15
426 #define S390_R14_REGNUM 16
427 #define S390_R15_REGNUM 17
428 /* Total Core Registers. */
429 #define S390_NUM_CORE_REGS 18
430
setcc(S390CPU * cpu,uint64_t cc)431 static inline void setcc(S390CPU *cpu, uint64_t cc)
432 {
433 CPUS390XState *env = &cpu->env;
434
435 env->psw.mask &= ~(3ull << 44);
436 env->psw.mask |= (cc & 3) << 44;
437 env->cc_op = cc;
438 }
439
440 /* STSI */
441 #define STSI_R0_FC_MASK 0x00000000f0000000ULL
442 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL
443 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL
444 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL
445 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL
446 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
447 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
448 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
449 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
450
451 /* Basic Machine Configuration */
452 typedef struct SysIB_111 {
453 uint8_t res1[32];
454 uint8_t manuf[16];
455 uint8_t type[4];
456 uint8_t res2[12];
457 uint8_t model[16];
458 uint8_t sequence[16];
459 uint8_t plant[4];
460 uint8_t res3[3996];
461 } SysIB_111;
462 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096);
463
464 /* Basic Machine CPU */
465 typedef struct SysIB_121 {
466 uint8_t res1[80];
467 uint8_t sequence[16];
468 uint8_t plant[4];
469 uint8_t res2[2];
470 uint16_t cpu_addr;
471 uint8_t res3[3992];
472 } SysIB_121;
473 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096);
474
475 /* Basic Machine CPUs */
476 typedef struct SysIB_122 {
477 uint8_t res1[32];
478 uint32_t capability;
479 uint16_t total_cpus;
480 uint16_t conf_cpus;
481 uint16_t standby_cpus;
482 uint16_t reserved_cpus;
483 uint16_t adjustments[2026];
484 } SysIB_122;
485 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096);
486
487 /* LPAR CPU */
488 typedef struct SysIB_221 {
489 uint8_t res1[80];
490 uint8_t sequence[16];
491 uint8_t plant[4];
492 uint16_t cpu_id;
493 uint16_t cpu_addr;
494 uint8_t res3[3992];
495 } SysIB_221;
496 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096);
497
498 /* LPAR CPUs */
499 typedef struct SysIB_222 {
500 uint8_t res1[32];
501 uint16_t lpar_num;
502 uint8_t res2;
503 uint8_t lcpuc;
504 uint16_t total_cpus;
505 uint16_t conf_cpus;
506 uint16_t standby_cpus;
507 uint16_t reserved_cpus;
508 uint8_t name[8];
509 uint32_t caf;
510 uint8_t res3[16];
511 uint16_t dedicated_cpus;
512 uint16_t shared_cpus;
513 uint8_t res4[4020];
514 } SysIB_222;
515 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096);
516
517 /* VM CPUs */
518 typedef struct SysIB_322 {
519 uint8_t res1[31];
520 uint8_t count;
521 struct {
522 uint8_t res2[4];
523 uint16_t total_cpus;
524 uint16_t conf_cpus;
525 uint16_t standby_cpus;
526 uint16_t reserved_cpus;
527 uint8_t name[8];
528 uint32_t caf;
529 uint8_t cpi[16];
530 uint8_t res5[3];
531 uint8_t ext_name_encoding;
532 uint32_t res3;
533 uint8_t uuid[16];
534 } vm[8];
535 uint8_t res4[1504];
536 uint8_t ext_names[8][256];
537 } SysIB_322;
538 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096);
539
540 typedef union SysIB {
541 SysIB_111 sysib_111;
542 SysIB_121 sysib_121;
543 SysIB_122 sysib_122;
544 SysIB_221 sysib_221;
545 SysIB_222 sysib_222;
546 SysIB_322 sysib_322;
547 } SysIB;
548 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
549
550 /* MMU defines */
551 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */
552 #define ASCE_SUBSPACE 0x200 /* subspace group control */
553 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */
554 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */
555 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */
556 #define ASCE_REAL_SPACE 0x20 /* real space control */
557 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */
558 #define ASCE_TYPE_REGION1 0x0c /* region first table type */
559 #define ASCE_TYPE_REGION2 0x08 /* region second table type */
560 #define ASCE_TYPE_REGION3 0x04 /* region third table type */
561 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */
562 #define ASCE_TABLE_LENGTH 0x03 /* region table length */
563
564 #define REGION_ENTRY_ORIGIN (~0xfffULL) /* region/segment table origin */
565 #define REGION_ENTRY_RO 0x200 /* region/segment protection bit */
566 #define REGION_ENTRY_TF 0xc0 /* region/segment table offset */
567 #define REGION_ENTRY_INV 0x20 /* invalid region table entry */
568 #define REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
569 #define REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
570 #define REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
571 #define REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
572 #define REGION_ENTRY_LENGTH 0x03 /* region third length */
573
574 #define SEGMENT_ENTRY_ORIGIN (~0x7ffULL) /* segment table origin */
575 #define SEGMENT_ENTRY_FC 0x400 /* format control */
576 #define SEGMENT_ENTRY_RO 0x200 /* page protection bit */
577 #define SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
578
579 #define VADDR_PX 0xff000 /* page index bits */
580
581 #define PAGE_RO 0x200 /* HW read-only bit */
582 #define PAGE_INVALID 0x400 /* HW invalid bit */
583 #define PAGE_RES0 0x800 /* bit must be zero */
584
585 #define SK_C (0x1 << 1)
586 #define SK_R (0x1 << 2)
587 #define SK_F (0x1 << 3)
588 #define SK_ACC_MASK (0xf << 4)
589
590 /* SIGP order codes */
591 #define SIGP_SENSE 0x01
592 #define SIGP_EXTERNAL_CALL 0x02
593 #define SIGP_EMERGENCY 0x03
594 #define SIGP_START 0x04
595 #define SIGP_STOP 0x05
596 #define SIGP_RESTART 0x06
597 #define SIGP_STOP_STORE_STATUS 0x09
598 #define SIGP_INITIAL_CPU_RESET 0x0b
599 #define SIGP_CPU_RESET 0x0c
600 #define SIGP_SET_PREFIX 0x0d
601 #define SIGP_STORE_STATUS_ADDR 0x0e
602 #define SIGP_SET_ARCH 0x12
603 #define SIGP_COND_EMERGENCY 0x13
604 #define SIGP_SENSE_RUNNING 0x15
605 #define SIGP_STORE_ADTL_STATUS 0x17
606
607 /* SIGP condition codes */
608 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
609 #define SIGP_CC_STATUS_STORED 1
610 #define SIGP_CC_BUSY 2
611 #define SIGP_CC_NOT_OPERATIONAL 3
612
613 /* SIGP status bits */
614 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
615 #define SIGP_STAT_NOT_RUNNING 0x00000400UL
616 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
617 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
618 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
619 #define SIGP_STAT_STOPPED 0x00000040UL
620 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
621 #define SIGP_STAT_CHECK_STOP 0x00000010UL
622 #define SIGP_STAT_INOPERATIVE 0x00000004UL
623 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
624 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
625
626 /* SIGP SET ARCHITECTURE modes */
627 #define SIGP_MODE_ESA_S390 0
628 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
629 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
630
631 /* SIGP order code mask corresponding to bit positions 56-63 */
632 #define SIGP_ORDER_MASK 0x000000ff
633
634 /* machine check interruption code */
635
636 /* subclasses */
637 #define MCIC_SC_SD 0x8000000000000000ULL
638 #define MCIC_SC_PD 0x4000000000000000ULL
639 #define MCIC_SC_SR 0x2000000000000000ULL
640 #define MCIC_SC_CD 0x0800000000000000ULL
641 #define MCIC_SC_ED 0x0400000000000000ULL
642 #define MCIC_SC_DG 0x0100000000000000ULL
643 #define MCIC_SC_W 0x0080000000000000ULL
644 #define MCIC_SC_CP 0x0040000000000000ULL
645 #define MCIC_SC_SP 0x0020000000000000ULL
646 #define MCIC_SC_CK 0x0010000000000000ULL
647
648 /* subclass modifiers */
649 #define MCIC_SCM_B 0x0002000000000000ULL
650 #define MCIC_SCM_DA 0x0000000020000000ULL
651 #define MCIC_SCM_AP 0x0000000000080000ULL
652
653 /* storage errors */
654 #define MCIC_SE_SE 0x0000800000000000ULL
655 #define MCIC_SE_SC 0x0000400000000000ULL
656 #define MCIC_SE_KE 0x0000200000000000ULL
657 #define MCIC_SE_DS 0x0000100000000000ULL
658 #define MCIC_SE_IE 0x0000000080000000ULL
659
660 /* validity bits */
661 #define MCIC_VB_WP 0x0000080000000000ULL
662 #define MCIC_VB_MS 0x0000040000000000ULL
663 #define MCIC_VB_PM 0x0000020000000000ULL
664 #define MCIC_VB_IA 0x0000010000000000ULL
665 #define MCIC_VB_FA 0x0000008000000000ULL
666 #define MCIC_VB_VR 0x0000004000000000ULL
667 #define MCIC_VB_EC 0x0000002000000000ULL
668 #define MCIC_VB_FP 0x0000001000000000ULL
669 #define MCIC_VB_GR 0x0000000800000000ULL
670 #define MCIC_VB_CR 0x0000000400000000ULL
671 #define MCIC_VB_ST 0x0000000100000000ULL
672 #define MCIC_VB_AR 0x0000000040000000ULL
673 #define MCIC_VB_GS 0x0000000008000000ULL
674 #define MCIC_VB_PR 0x0000000000200000ULL
675 #define MCIC_VB_FC 0x0000000000100000ULL
676 #define MCIC_VB_CT 0x0000000000020000ULL
677 #define MCIC_VB_CC 0x0000000000010000ULL
678
s390_build_validity_mcic(void)679 static inline uint64_t s390_build_validity_mcic(void)
680 {
681 uint64_t mcic;
682
683 /*
684 * Indicate all validity bits (no damage) only. Other bits have to be
685 * added by the caller. (storage errors, subclasses and subclass modifiers)
686 */
687 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
688 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
689 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
690 if (s390_has_feat(S390_FEAT_VECTOR)) {
691 mcic |= MCIC_VB_VR;
692 }
693 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
694 mcic |= MCIC_VB_GS;
695 }
696 return mcic;
697 }
698
s390_do_cpu_full_reset(CPUState * cs,run_on_cpu_data arg)699 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
700 {
701 cpu_reset(cs);
702 }
703
s390_do_cpu_reset(CPUState * cs,run_on_cpu_data arg)704 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
705 {
706 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
707
708 scc->cpu_reset(cs);
709 }
710
s390_do_cpu_initial_reset(CPUState * cs,run_on_cpu_data arg)711 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg)
712 {
713 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
714
715 scc->initial_cpu_reset(cs);
716 }
717
s390_do_cpu_load_normal(CPUState * cs,run_on_cpu_data arg)718 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg)
719 {
720 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
721
722 scc->load_normal(cs);
723 }
724
725
726 /* cpu.c */
727 void s390_crypto_reset(void);
728 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
729 void s390_cmma_reset(void);
730 void s390_enable_css_support(S390CPU *cpu);
731 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
732 int vq, bool assign);
733 #ifndef CONFIG_USER_ONLY
734 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
735 #else
s390_cpu_set_state(uint8_t cpu_state,S390CPU * cpu)736 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
737 {
738 return 0;
739 }
740 #endif /* CONFIG_USER_ONLY */
s390_cpu_get_state(S390CPU * cpu)741 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
742 {
743 return cpu->env.cpu_state;
744 }
745
746
747 /* cpu_models.c */
748 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
749 #define cpu_list s390_cpu_list
750 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
751 const S390FeatInit feat_init);
752
753
754 /* helper.c */
755 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
756 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
757 #define CPU_RESOLVING_TYPE TYPE_S390_CPU
758
759 /* you can call this signal handler from your SIGBUS and SIGSEGV
760 signal handlers to inform the virtual CPU of exceptions. non zero
761 is returned if the signal was handled by the virtual CPU. */
762 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc);
763 #define cpu_signal_handler cpu_s390x_signal_handler
764
765
766 /* interrupt.c */
767 void s390_crw_mchk(void);
768 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
769 uint32_t io_int_parm, uint32_t io_int_word);
770 /* automatically detect the instruction length */
771 #define ILEN_AUTO 0xff
772 #define RA_IGNORED 0
773 void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen,
774 uintptr_t ra);
775 /* service interrupts are floating therefore we must not pass an cpustate */
776 void s390_sclp_extint(uint32_t parm);
777
778 /* mmu_helper.c */
779 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
780 int len, bool is_write);
781 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
782 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
783 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
784 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
785 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \
786 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
787 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
788 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
789 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
790
791
792 /* sigp.c */
793 int s390_cpu_restart(S390CPU *cpu);
794 void s390_init_sigp(void);
795
796
797 /* outside of target/s390x/ */
798 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
799
800 #endif
801