1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/visitor.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/hostmem.h"
33 #include "sysemu/numa.h"
34 #include "sysemu/qtest.h"
35 #include "sysemu/reset.h"
36 #include "sysemu/runstate.h"
37 #include "qemu/log.h"
38 #include "hw/fw-path-provider.h"
39 #include "elf.h"
40 #include "net/net.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/cpus.h"
43 #include "sysemu/hw_accel.h"
44 #include "kvm_ppc.h"
45 #include "migration/misc.h"
46 #include "migration/qemu-file-types.h"
47 #include "migration/global_state.h"
48 #include "migration/register.h"
49 #include "mmu-hash64.h"
50 #include "mmu-book3s-v3.h"
51 #include "cpu-models.h"
52 #include "hw/core/cpu.h"
53
54 #include "hw/boards.h"
55 #include "hw/ppc/ppc.h"
56 #include "hw/loader.h"
57
58 #include "hw/ppc/fdt.h"
59 #include "hw/ppc/spapr.h"
60 #include "hw/ppc/spapr_vio.h"
61 #include "hw/qdev-properties.h"
62 #include "hw/pci-host/spapr.h"
63 #include "hw/pci/msi.h"
64
65 #include "hw/pci/pci.h"
66 #include "hw/scsi/scsi.h"
67 #include "hw/virtio/virtio-scsi.h"
68 #include "hw/virtio/vhost-scsi-common.h"
69
70 #include "exec/address-spaces.h"
71 #include "exec/ram_addr.h"
72 #include "hw/usb.h"
73 #include "qemu/config-file.h"
74 #include "qemu/error-report.h"
75 #include "trace.h"
76 #include "hw/nmi.h"
77 #include "hw/intc/intc.h"
78
79 #include "qemu/cutils.h"
80 #include "hw/ppc/spapr_cpu_core.h"
81 #include "hw/mem/memory-device.h"
82 #include "hw/ppc/spapr_tpm_proxy.h"
83
84 #include "monitor/monitor.h"
85
86 #include <libfdt.h>
87
88 /* SLOF memory layout:
89 *
90 * SLOF raw image loaded at 0, copies its romfs right below the flat
91 * device-tree, then position SLOF itself 31M below that
92 *
93 * So we set FW_OVERHEAD to 40MB which should account for all of that
94 * and more
95 *
96 * We load our kernel at 4M, leaving space for SLOF initial image
97 */
98 #define FDT_MAX_SIZE 0x100000
99 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
100 #define FW_MAX_SIZE 0x400000
101 #define FW_FILE_NAME "slof.bin"
102 #define FW_OVERHEAD 0x2800000
103 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
104
105 #define MIN_RMA_SLOF 128UL
106
107 #define PHANDLE_INTC 0x00001111
108
109 /* These two functions implement the VCPU id numbering: one to compute them
110 * all and one to identify thread 0 of a VCORE. Any change to the first one
111 * is likely to have an impact on the second one, so let's keep them close.
112 */
spapr_vcpu_id(SpaprMachineState * spapr,int cpu_index)113 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index)
114 {
115 MachineState *ms = MACHINE(spapr);
116 unsigned int smp_threads = ms->smp.threads;
117
118 assert(spapr->vsmt);
119 return
120 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
121 }
spapr_is_thread0_in_vcore(SpaprMachineState * spapr,PowerPCCPU * cpu)122 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr,
123 PowerPCCPU *cpu)
124 {
125 assert(spapr->vsmt);
126 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
127 }
128
pre_2_10_vmstate_dummy_icp_needed(void * opaque)129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
130 {
131 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
132 * and newer QEMUs don't even have them. In both cases, we don't want
133 * to send anything on the wire.
134 */
135 return false;
136 }
137
138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
139 .name = "icp/server",
140 .version_id = 1,
141 .minimum_version_id = 1,
142 .needed = pre_2_10_vmstate_dummy_icp_needed,
143 .fields = (VMStateField[]) {
144 VMSTATE_UNUSED(4), /* uint32_t xirr */
145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
146 VMSTATE_UNUSED(1), /* uint8_t mfrr */
147 VMSTATE_END_OF_LIST()
148 },
149 };
150
pre_2_10_vmstate_register_dummy_icp(int i)151 static void pre_2_10_vmstate_register_dummy_icp(int i)
152 {
153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
154 (void *)(uintptr_t) i);
155 }
156
pre_2_10_vmstate_unregister_dummy_icp(int i)157 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
158 {
159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
160 (void *)(uintptr_t) i);
161 }
162
spapr_max_server_number(SpaprMachineState * spapr)163 int spapr_max_server_number(SpaprMachineState *spapr)
164 {
165 MachineState *ms = MACHINE(spapr);
166
167 assert(spapr->vsmt);
168 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads);
169 }
170
spapr_fixup_cpu_smt_dt(void * fdt,int offset,PowerPCCPU * cpu,int smt_threads)171 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
172 int smt_threads)
173 {
174 int i, ret = 0;
175 uint32_t servers_prop[smt_threads];
176 uint32_t gservers_prop[smt_threads * 2];
177 int index = spapr_get_vcpu_id(cpu);
178
179 if (cpu->compat_pvr) {
180 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
181 if (ret < 0) {
182 return ret;
183 }
184 }
185
186 /* Build interrupt servers and gservers properties */
187 for (i = 0; i < smt_threads; i++) {
188 servers_prop[i] = cpu_to_be32(index + i);
189 /* Hack, direct the group queues back to cpu 0 */
190 gservers_prop[i*2] = cpu_to_be32(index + i);
191 gservers_prop[i*2 + 1] = 0;
192 }
193 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
194 servers_prop, sizeof(servers_prop));
195 if (ret < 0) {
196 return ret;
197 }
198 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
199 gservers_prop, sizeof(gservers_prop));
200
201 return ret;
202 }
203
spapr_fixup_cpu_numa_dt(void * fdt,int offset,PowerPCCPU * cpu)204 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
205 {
206 int index = spapr_get_vcpu_id(cpu);
207 uint32_t associativity[] = {cpu_to_be32(0x5),
208 cpu_to_be32(0x0),
209 cpu_to_be32(0x0),
210 cpu_to_be32(0x0),
211 cpu_to_be32(cpu->node_id),
212 cpu_to_be32(index)};
213
214 /* Advertise NUMA via ibm,associativity */
215 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
216 sizeof(associativity));
217 }
218
219 /* Populate the "ibm,pa-features" property */
spapr_populate_pa_features(SpaprMachineState * spapr,PowerPCCPU * cpu,void * fdt,int offset)220 static void spapr_populate_pa_features(SpaprMachineState *spapr,
221 PowerPCCPU *cpu,
222 void *fdt, int offset)
223 {
224 uint8_t pa_features_206[] = { 6, 0,
225 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
226 uint8_t pa_features_207[] = { 24, 0,
227 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
228 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
231 uint8_t pa_features_300[] = { 66, 0,
232 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
233 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
234 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
235 /* 6: DS207 */
236 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
237 /* 16: Vector */
238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
239 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
241 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
243 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
244 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
245 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
247 /* 42: PM, 44: PC RA, 46: SC vec'd */
248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
249 /* 48: SIMD, 50: QP BFP, 52: String */
250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
251 /* 54: DecFP, 56: DecI, 58: SHA */
252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
253 /* 60: NM atomic, 62: RNG */
254 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
255 };
256 uint8_t *pa_features = NULL;
257 size_t pa_size;
258
259 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
260 pa_features = pa_features_206;
261 pa_size = sizeof(pa_features_206);
262 }
263 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
264 pa_features = pa_features_207;
265 pa_size = sizeof(pa_features_207);
266 }
267 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
268 pa_features = pa_features_300;
269 pa_size = sizeof(pa_features_300);
270 }
271 if (!pa_features) {
272 return;
273 }
274
275 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
276 /*
277 * Note: we keep CI large pages off by default because a 64K capable
278 * guest provisioned with large pages might otherwise try to map a qemu
279 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
280 * even if that qemu runs on a 4k host.
281 * We dd this bit back here if we are confident this is not an issue
282 */
283 pa_features[3] |= 0x20;
284 }
285 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
286 pa_features[24] |= 0x80; /* Transactional memory support */
287 }
288 if (spapr->cas_pre_isa3_guest && pa_size > 40) {
289 /* Workaround for broken kernels that attempt (guest) radix
290 * mode when they can't handle it, if they see the radix bit set
291 * in pa-features. So hide it from them. */
292 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
293 }
294
295 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
296 }
297
spapr_node0_size(MachineState * machine)298 static hwaddr spapr_node0_size(MachineState *machine)
299 {
300 if (machine->numa_state->num_nodes) {
301 int i;
302 for (i = 0; i < machine->numa_state->num_nodes; ++i) {
303 if (machine->numa_state->nodes[i].node_mem) {
304 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem),
305 machine->ram_size);
306 }
307 }
308 }
309 return machine->ram_size;
310 }
311
add_str(GString * s,const gchar * s1)312 static void add_str(GString *s, const gchar *s1)
313 {
314 g_string_append_len(s, s1, strlen(s1) + 1);
315 }
316
spapr_populate_memory_node(void * fdt,int nodeid,hwaddr start,hwaddr size)317 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
318 hwaddr size)
319 {
320 uint32_t associativity[] = {
321 cpu_to_be32(0x4), /* length */
322 cpu_to_be32(0x0), cpu_to_be32(0x0),
323 cpu_to_be32(0x0), cpu_to_be32(nodeid)
324 };
325 char mem_name[32];
326 uint64_t mem_reg_property[2];
327 int off;
328
329 mem_reg_property[0] = cpu_to_be64(start);
330 mem_reg_property[1] = cpu_to_be64(size);
331
332 sprintf(mem_name, "memory@%" HWADDR_PRIx, start);
333 off = fdt_add_subnode(fdt, 0, mem_name);
334 _FDT(off);
335 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
336 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
337 sizeof(mem_reg_property))));
338 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
339 sizeof(associativity))));
340 return off;
341 }
342
spapr_populate_memory(SpaprMachineState * spapr,void * fdt)343 static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt)
344 {
345 MachineState *machine = MACHINE(spapr);
346 hwaddr mem_start, node_size;
347 int i, nb_nodes = machine->numa_state->num_nodes;
348 NodeInfo *nodes = machine->numa_state->nodes;
349
350 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
351 if (!nodes[i].node_mem) {
352 continue;
353 }
354 if (mem_start >= machine->ram_size) {
355 node_size = 0;
356 } else {
357 node_size = nodes[i].node_mem;
358 if (node_size > machine->ram_size - mem_start) {
359 node_size = machine->ram_size - mem_start;
360 }
361 }
362 if (!mem_start) {
363 /* spapr_machine_init() checks for rma_size <= node0_size
364 * already */
365 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
366 mem_start += spapr->rma_size;
367 node_size -= spapr->rma_size;
368 }
369 for ( ; node_size; ) {
370 hwaddr sizetmp = pow2floor(node_size);
371
372 /* mem_start != 0 here */
373 if (ctzl(mem_start) < ctzl(sizetmp)) {
374 sizetmp = 1ULL << ctzl(mem_start);
375 }
376
377 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
378 node_size -= sizetmp;
379 mem_start += sizetmp;
380 }
381 }
382
383 return 0;
384 }
385
spapr_populate_cpu_dt(CPUState * cs,void * fdt,int offset,SpaprMachineState * spapr)386 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
387 SpaprMachineState *spapr)
388 {
389 MachineState *ms = MACHINE(spapr);
390 PowerPCCPU *cpu = POWERPC_CPU(cs);
391 CPUPPCState *env = &cpu->env;
392 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
393 int index = spapr_get_vcpu_id(cpu);
394 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
395 0xffffffff, 0xffffffff};
396 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
397 : SPAPR_TIMEBASE_FREQ;
398 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
399 uint32_t page_sizes_prop[64];
400 size_t page_sizes_prop_size;
401 unsigned int smp_threads = ms->smp.threads;
402 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores;
403 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
404 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
405 SpaprDrc *drc;
406 int drc_index;
407 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
408 int i;
409
410 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
411 if (drc) {
412 drc_index = spapr_drc_index(drc);
413 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
414 }
415
416 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
417 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
418
419 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
420 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
421 env->dcache_line_size)));
422 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
423 env->dcache_line_size)));
424 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
425 env->icache_line_size)));
426 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
427 env->icache_line_size)));
428
429 if (pcc->l1_dcache_size) {
430 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
431 pcc->l1_dcache_size)));
432 } else {
433 warn_report("Unknown L1 dcache size for cpu");
434 }
435 if (pcc->l1_icache_size) {
436 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
437 pcc->l1_icache_size)));
438 } else {
439 warn_report("Unknown L1 icache size for cpu");
440 }
441
442 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
443 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
444 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
445 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
446 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
447 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
448
449 if (env->spr_cb[SPR_PURR].oea_read) {
450 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1)));
451 }
452 if (env->spr_cb[SPR_SPURR].oea_read) {
453 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1)));
454 }
455
456 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
457 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
458 segs, sizeof(segs))));
459 }
460
461 /* Advertise VSX (vector extensions) if available
462 * 1 == VMX / Altivec available
463 * 2 == VSX available
464 *
465 * Only CPUs for which we create core types in spapr_cpu_core.c
466 * are possible, and all of those have VMX */
467 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
468 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
469 } else {
470 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
471 }
472
473 /* Advertise DFP (Decimal Floating Point) if available
474 * 0 / no property == no DFP
475 * 1 == DFP available */
476 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
477 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
478 }
479
480 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
481 sizeof(page_sizes_prop));
482 if (page_sizes_prop_size) {
483 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
484 page_sizes_prop, page_sizes_prop_size)));
485 }
486
487 spapr_populate_pa_features(spapr, cpu, fdt, offset);
488
489 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
490 cs->cpu_index / vcpus_per_socket)));
491
492 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
493 pft_size_prop, sizeof(pft_size_prop))));
494
495 if (ms->numa_state->num_nodes > 1) {
496 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
497 }
498
499 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
500
501 if (pcc->radix_page_info) {
502 for (i = 0; i < pcc->radix_page_info->count; i++) {
503 radix_AP_encodings[i] =
504 cpu_to_be32(pcc->radix_page_info->entries[i]);
505 }
506 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
507 radix_AP_encodings,
508 pcc->radix_page_info->count *
509 sizeof(radix_AP_encodings[0]))));
510 }
511
512 /*
513 * We set this property to let the guest know that it can use the large
514 * decrementer and its width in bits.
515 */
516 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF)
517 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits",
518 pcc->lrg_decr_bits)));
519 }
520
spapr_populate_cpus_dt_node(void * fdt,SpaprMachineState * spapr)521 static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr)
522 {
523 CPUState **rev;
524 CPUState *cs;
525 int n_cpus;
526 int cpus_offset;
527 char *nodename;
528 int i;
529
530 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
531 _FDT(cpus_offset);
532 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
533 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
534
535 /*
536 * We walk the CPUs in reverse order to ensure that CPU DT nodes
537 * created by fdt_add_subnode() end up in the right order in FDT
538 * for the guest kernel the enumerate the CPUs correctly.
539 *
540 * The CPU list cannot be traversed in reverse order, so we need
541 * to do extra work.
542 */
543 n_cpus = 0;
544 rev = NULL;
545 CPU_FOREACH(cs) {
546 rev = g_renew(CPUState *, rev, n_cpus + 1);
547 rev[n_cpus++] = cs;
548 }
549
550 for (i = n_cpus - 1; i >= 0; i--) {
551 CPUState *cs = rev[i];
552 PowerPCCPU *cpu = POWERPC_CPU(cs);
553 int index = spapr_get_vcpu_id(cpu);
554 DeviceClass *dc = DEVICE_GET_CLASS(cs);
555 int offset;
556
557 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
558 continue;
559 }
560
561 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
562 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
563 g_free(nodename);
564 _FDT(offset);
565 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
566 }
567
568 g_free(rev);
569 }
570
spapr_rng_populate_dt(void * fdt)571 static int spapr_rng_populate_dt(void *fdt)
572 {
573 int node;
574 int ret;
575
576 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
577 if (node <= 0) {
578 return -1;
579 }
580 ret = fdt_setprop_string(fdt, node, "device_type",
581 "ibm,platform-facilities");
582 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
583 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
584
585 node = fdt_add_subnode(fdt, node, "ibm,random-v1");
586 if (node <= 0) {
587 return -1;
588 }
589 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
590
591 return ret ? -1 : 0;
592 }
593
spapr_pc_dimm_node(MemoryDeviceInfoList * list,ram_addr_t addr)594 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
595 {
596 MemoryDeviceInfoList *info;
597
598 for (info = list; info; info = info->next) {
599 MemoryDeviceInfo *value = info->value;
600
601 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
602 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
603
604 if (addr >= pcdimm_info->addr &&
605 addr < (pcdimm_info->addr + pcdimm_info->size)) {
606 return pcdimm_info->node;
607 }
608 }
609 }
610
611 return -1;
612 }
613
614 struct sPAPRDrconfCellV2 {
615 uint32_t seq_lmbs;
616 uint64_t base_addr;
617 uint32_t drc_index;
618 uint32_t aa_index;
619 uint32_t flags;
620 } QEMU_PACKED;
621
622 typedef struct DrconfCellQueue {
623 struct sPAPRDrconfCellV2 cell;
624 QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
625 } DrconfCellQueue;
626
627 static DrconfCellQueue *
spapr_get_drconf_cell(uint32_t seq_lmbs,uint64_t base_addr,uint32_t drc_index,uint32_t aa_index,uint32_t flags)628 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
629 uint32_t drc_index, uint32_t aa_index,
630 uint32_t flags)
631 {
632 DrconfCellQueue *elem;
633
634 elem = g_malloc0(sizeof(*elem));
635 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
636 elem->cell.base_addr = cpu_to_be64(base_addr);
637 elem->cell.drc_index = cpu_to_be32(drc_index);
638 elem->cell.aa_index = cpu_to_be32(aa_index);
639 elem->cell.flags = cpu_to_be32(flags);
640
641 return elem;
642 }
643
644 /* ibm,dynamic-memory-v2 */
spapr_populate_drmem_v2(SpaprMachineState * spapr,void * fdt,int offset,MemoryDeviceInfoList * dimms)645 static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt,
646 int offset, MemoryDeviceInfoList *dimms)
647 {
648 MachineState *machine = MACHINE(spapr);
649 uint8_t *int_buf, *cur_index;
650 int ret;
651 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
652 uint64_t addr, cur_addr, size;
653 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
654 uint64_t mem_end = machine->device_memory->base +
655 memory_region_size(&machine->device_memory->mr);
656 uint32_t node, buf_len, nr_entries = 0;
657 SpaprDrc *drc;
658 DrconfCellQueue *elem, *next;
659 MemoryDeviceInfoList *info;
660 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
661 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
662
663 /* Entry to cover RAM and the gap area */
664 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
665 SPAPR_LMB_FLAGS_RESERVED |
666 SPAPR_LMB_FLAGS_DRC_INVALID);
667 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
668 nr_entries++;
669
670 cur_addr = machine->device_memory->base;
671 for (info = dimms; info; info = info->next) {
672 PCDIMMDeviceInfo *di = info->value->u.dimm.data;
673
674 addr = di->addr;
675 size = di->size;
676 node = di->node;
677
678 /* Entry for hot-pluggable area */
679 if (cur_addr < addr) {
680 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
681 g_assert(drc);
682 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
683 cur_addr, spapr_drc_index(drc), -1, 0);
684 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
685 nr_entries++;
686 }
687
688 /* Entry for DIMM */
689 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
690 g_assert(drc);
691 elem = spapr_get_drconf_cell(size / lmb_size, addr,
692 spapr_drc_index(drc), node,
693 SPAPR_LMB_FLAGS_ASSIGNED);
694 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
695 nr_entries++;
696 cur_addr = addr + size;
697 }
698
699 /* Entry for remaining hotpluggable area */
700 if (cur_addr < mem_end) {
701 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
702 g_assert(drc);
703 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
704 cur_addr, spapr_drc_index(drc), -1, 0);
705 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
706 nr_entries++;
707 }
708
709 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
710 int_buf = cur_index = g_malloc0(buf_len);
711 *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
712 cur_index += sizeof(nr_entries);
713
714 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
715 memcpy(cur_index, &elem->cell, sizeof(elem->cell));
716 cur_index += sizeof(elem->cell);
717 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
718 g_free(elem);
719 }
720
721 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
722 g_free(int_buf);
723 if (ret < 0) {
724 return -1;
725 }
726 return 0;
727 }
728
729 /* ibm,dynamic-memory */
spapr_populate_drmem_v1(SpaprMachineState * spapr,void * fdt,int offset,MemoryDeviceInfoList * dimms)730 static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt,
731 int offset, MemoryDeviceInfoList *dimms)
732 {
733 MachineState *machine = MACHINE(spapr);
734 int i, ret;
735 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
736 uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
737 uint32_t nr_lmbs = (machine->device_memory->base +
738 memory_region_size(&machine->device_memory->mr)) /
739 lmb_size;
740 uint32_t *int_buf, *cur_index, buf_len;
741
742 /*
743 * Allocate enough buffer size to fit in ibm,dynamic-memory
744 */
745 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
746 cur_index = int_buf = g_malloc0(buf_len);
747 int_buf[0] = cpu_to_be32(nr_lmbs);
748 cur_index++;
749 for (i = 0; i < nr_lmbs; i++) {
750 uint64_t addr = i * lmb_size;
751 uint32_t *dynamic_memory = cur_index;
752
753 if (i >= device_lmb_start) {
754 SpaprDrc *drc;
755
756 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
757 g_assert(drc);
758
759 dynamic_memory[0] = cpu_to_be32(addr >> 32);
760 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
761 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
762 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
763 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
764 if (memory_region_present(get_system_memory(), addr)) {
765 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
766 } else {
767 dynamic_memory[5] = cpu_to_be32(0);
768 }
769 } else {
770 /*
771 * LMB information for RMA, boot time RAM and gap b/n RAM and
772 * device memory region -- all these are marked as reserved
773 * and as having no valid DRC.
774 */
775 dynamic_memory[0] = cpu_to_be32(addr >> 32);
776 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
777 dynamic_memory[2] = cpu_to_be32(0);
778 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
779 dynamic_memory[4] = cpu_to_be32(-1);
780 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
781 SPAPR_LMB_FLAGS_DRC_INVALID);
782 }
783
784 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
785 }
786 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
787 g_free(int_buf);
788 if (ret < 0) {
789 return -1;
790 }
791 return 0;
792 }
793
794 /*
795 * Adds ibm,dynamic-reconfiguration-memory node.
796 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
797 * of this device tree node.
798 */
spapr_populate_drconf_memory(SpaprMachineState * spapr,void * fdt)799 static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt)
800 {
801 MachineState *machine = MACHINE(spapr);
802 int nb_numa_nodes = machine->numa_state->num_nodes;
803 int ret, i, offset;
804 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
805 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
806 uint32_t *int_buf, *cur_index, buf_len;
807 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
808 MemoryDeviceInfoList *dimms = NULL;
809
810 /*
811 * Don't create the node if there is no device memory
812 */
813 if (machine->ram_size == machine->maxram_size) {
814 return 0;
815 }
816
817 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
818
819 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
820 sizeof(prop_lmb_size));
821 if (ret < 0) {
822 return ret;
823 }
824
825 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
826 if (ret < 0) {
827 return ret;
828 }
829
830 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
831 if (ret < 0) {
832 return ret;
833 }
834
835 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
836 dimms = qmp_memory_device_list();
837 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
838 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms);
839 } else {
840 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms);
841 }
842 qapi_free_MemoryDeviceInfoList(dimms);
843
844 if (ret < 0) {
845 return ret;
846 }
847
848 /* ibm,associativity-lookup-arrays */
849 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
850 cur_index = int_buf = g_malloc0(buf_len);
851 int_buf[0] = cpu_to_be32(nr_nodes);
852 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
853 cur_index += 2;
854 for (i = 0; i < nr_nodes; i++) {
855 uint32_t associativity[] = {
856 cpu_to_be32(0x0),
857 cpu_to_be32(0x0),
858 cpu_to_be32(0x0),
859 cpu_to_be32(i)
860 };
861 memcpy(cur_index, associativity, sizeof(associativity));
862 cur_index += 4;
863 }
864 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
865 (cur_index - int_buf) * sizeof(uint32_t));
866 g_free(int_buf);
867
868 return ret;
869 }
870
spapr_dt_cas_updates(SpaprMachineState * spapr,void * fdt,SpaprOptionVector * ov5_updates)871 static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt,
872 SpaprOptionVector *ov5_updates)
873 {
874 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
875 int ret = 0, offset;
876
877 /* Generate ibm,dynamic-reconfiguration-memory node if required */
878 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
879 g_assert(smc->dr_lmb_enabled);
880 ret = spapr_populate_drconf_memory(spapr, fdt);
881 if (ret) {
882 goto out;
883 }
884 }
885
886 offset = fdt_path_offset(fdt, "/chosen");
887 if (offset < 0) {
888 offset = fdt_add_subnode(fdt, 0, "chosen");
889 if (offset < 0) {
890 return offset;
891 }
892 }
893 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
894 "ibm,architecture-vec-5");
895
896 out:
897 return ret;
898 }
899
spapr_hotplugged_dev_before_cas(void)900 static bool spapr_hotplugged_dev_before_cas(void)
901 {
902 Object *drc_container, *obj;
903 ObjectProperty *prop;
904 ObjectPropertyIterator iter;
905
906 drc_container = container_get(object_get_root(), "/dr-connector");
907 object_property_iter_init(&iter, drc_container);
908 while ((prop = object_property_iter_next(&iter))) {
909 if (!strstart(prop->type, "link<", NULL)) {
910 continue;
911 }
912 obj = object_property_get_link(drc_container, prop->name, NULL);
913 if (spapr_drc_needed(obj)) {
914 return true;
915 }
916 }
917 return false;
918 }
919
920 static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset);
921
spapr_h_cas_compose_response(SpaprMachineState * spapr,target_ulong addr,target_ulong size,SpaprOptionVector * ov5_updates)922 int spapr_h_cas_compose_response(SpaprMachineState *spapr,
923 target_ulong addr, target_ulong size,
924 SpaprOptionVector *ov5_updates)
925 {
926 void *fdt;
927 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 };
928
929 if (spapr_hotplugged_dev_before_cas()) {
930 return 1;
931 }
932
933 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
934 error_report("SLOF provided an unexpected CAS buffer size "
935 TARGET_FMT_lu " (min: %zu, max: %u)",
936 size, sizeof(hdr), FW_MAX_SIZE);
937 exit(EXIT_FAILURE);
938 }
939
940 size -= sizeof(hdr);
941
942 fdt = spapr_build_fdt(spapr, false);
943 _FDT((fdt_pack(fdt)));
944
945 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
946 g_free(fdt);
947 trace_spapr_cas_failed(size);
948 return -1;
949 }
950
951 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
952 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
953 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
954
955 g_free(spapr->fdt_blob);
956 spapr->fdt_size = fdt_totalsize(fdt);
957 spapr->fdt_initial_size = spapr->fdt_size;
958 spapr->fdt_blob = fdt;
959
960 return 0;
961 }
962
spapr_dt_rtas(SpaprMachineState * spapr,void * fdt)963 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
964 {
965 MachineState *ms = MACHINE(spapr);
966 int rtas;
967 GString *hypertas = g_string_sized_new(256);
968 GString *qemu_hypertas = g_string_sized_new(256);
969 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
970 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
971 memory_region_size(&MACHINE(spapr)->device_memory->mr);
972 uint32_t lrdr_capacity[] = {
973 cpu_to_be32(max_device_addr >> 32),
974 cpu_to_be32(max_device_addr & 0xffffffff),
975 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
976 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads),
977 };
978 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0);
979 uint32_t maxdomains[] = {
980 cpu_to_be32(4),
981 maxdomain,
982 maxdomain,
983 maxdomain,
984 cpu_to_be32(spapr->gpu_numa_id),
985 };
986
987 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
988
989 /* hypertas */
990 add_str(hypertas, "hcall-pft");
991 add_str(hypertas, "hcall-term");
992 add_str(hypertas, "hcall-dabr");
993 add_str(hypertas, "hcall-interrupt");
994 add_str(hypertas, "hcall-tce");
995 add_str(hypertas, "hcall-vio");
996 add_str(hypertas, "hcall-splpar");
997 add_str(hypertas, "hcall-join");
998 add_str(hypertas, "hcall-bulk");
999 add_str(hypertas, "hcall-set-mode");
1000 add_str(hypertas, "hcall-sprg0");
1001 add_str(hypertas, "hcall-copy");
1002 add_str(hypertas, "hcall-debug");
1003 add_str(hypertas, "hcall-vphn");
1004 add_str(qemu_hypertas, "hcall-memop1");
1005
1006 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1007 add_str(hypertas, "hcall-multi-tce");
1008 }
1009
1010 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
1011 add_str(hypertas, "hcall-hpt-resize");
1012 }
1013
1014 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
1015 hypertas->str, hypertas->len));
1016 g_string_free(hypertas, TRUE);
1017 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
1018 qemu_hypertas->str, qemu_hypertas->len));
1019 g_string_free(qemu_hypertas, TRUE);
1020
1021 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
1022 refpoints, sizeof(refpoints)));
1023
1024 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
1025 maxdomains, sizeof(maxdomains)));
1026
1027 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
1028 RTAS_ERROR_LOG_MAX));
1029 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
1030 RTAS_EVENT_SCAN_RATE));
1031
1032 g_assert(msi_nonbroken);
1033 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
1034
1035 /*
1036 * According to PAPR, rtas ibm,os-term does not guarantee a return
1037 * back to the guest cpu.
1038 *
1039 * While an additional ibm,extended-os-term property indicates
1040 * that rtas call return will always occur. Set this property.
1041 */
1042 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
1043
1044 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
1045 lrdr_capacity, sizeof(lrdr_capacity)));
1046
1047 spapr_dt_rtas_tokens(fdt, rtas);
1048 }
1049
1050 /*
1051 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
1052 * and the XIVE features that the guest may request and thus the valid
1053 * values for bytes 23..26 of option vector 5:
1054 */
spapr_dt_ov5_platform_support(SpaprMachineState * spapr,void * fdt,int chosen)1055 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt,
1056 int chosen)
1057 {
1058 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
1059
1060 char val[2 * 4] = {
1061 23, 0x00, /* XICS / XIVE mode */
1062 24, 0x00, /* Hash/Radix, filled in below. */
1063 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1064 26, 0x40, /* Radix options: GTSE == yes. */
1065 };
1066
1067 if (spapr->irq->xics && spapr->irq->xive) {
1068 val[1] = SPAPR_OV5_XIVE_BOTH;
1069 } else if (spapr->irq->xive) {
1070 val[1] = SPAPR_OV5_XIVE_EXPLOIT;
1071 } else {
1072 assert(spapr->irq->xics);
1073 val[1] = SPAPR_OV5_XIVE_LEGACY;
1074 }
1075
1076 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1077 first_ppc_cpu->compat_pvr)) {
1078 /*
1079 * If we're in a pre POWER9 compat mode then the guest should
1080 * do hash and use the legacy interrupt mode
1081 */
1082 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */
1083 val[3] = 0x00; /* Hash */
1084 } else if (kvm_enabled()) {
1085 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1086 val[3] = 0x80; /* OV5_MMU_BOTH */
1087 } else if (kvmppc_has_cap_mmu_radix()) {
1088 val[3] = 0x40; /* OV5_MMU_RADIX_300 */
1089 } else {
1090 val[3] = 0x00; /* Hash */
1091 }
1092 } else {
1093 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1094 val[3] = 0xC0;
1095 }
1096 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1097 val, sizeof(val)));
1098 }
1099
spapr_dt_chosen(SpaprMachineState * spapr,void * fdt)1100 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt)
1101 {
1102 MachineState *machine = MACHINE(spapr);
1103 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1104 int chosen;
1105 const char *boot_device = machine->boot_order;
1106 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1107 size_t cb = 0;
1108 char *bootlist = get_boot_devices_list(&cb);
1109
1110 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1111
1112 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) {
1113 _FDT(fdt_setprop_string(fdt, chosen, "bootargs",
1114 machine->kernel_cmdline));
1115 }
1116 if (spapr->initrd_size) {
1117 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1118 spapr->initrd_base));
1119 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1120 spapr->initrd_base + spapr->initrd_size));
1121 }
1122
1123 if (spapr->kernel_size) {
1124 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1125 cpu_to_be64(spapr->kernel_size) };
1126
1127 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1128 &kprop, sizeof(kprop)));
1129 if (spapr->kernel_le) {
1130 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1131 }
1132 }
1133 if (boot_menu) {
1134 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1135 }
1136 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1137 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1138 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1139
1140 if (cb && bootlist) {
1141 int i;
1142
1143 for (i = 0; i < cb; i++) {
1144 if (bootlist[i] == '\n') {
1145 bootlist[i] = ' ';
1146 }
1147 }
1148 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1149 }
1150
1151 if (boot_device && strlen(boot_device)) {
1152 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1153 }
1154
1155 if (!spapr->has_graphics && stdout_path) {
1156 /*
1157 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1158 * kernel. New platforms should only use the "stdout-path" property. Set
1159 * the new property and continue using older property to remain
1160 * compatible with the existing firmware.
1161 */
1162 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1163 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1164 }
1165
1166 /* We can deal with BAR reallocation just fine, advertise it to the guest */
1167 if (smc->linux_pci_probe) {
1168 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0));
1169 }
1170
1171 spapr_dt_ov5_platform_support(spapr, fdt, chosen);
1172
1173 g_free(stdout_path);
1174 g_free(bootlist);
1175 }
1176
spapr_dt_hypervisor(SpaprMachineState * spapr,void * fdt)1177 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
1178 {
1179 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1180 * KVM to work under pHyp with some guest co-operation */
1181 int hypervisor;
1182 uint8_t hypercall[16];
1183
1184 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1185 /* indicate KVM hypercall interface */
1186 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1187 if (kvmppc_has_cap_fixup_hcalls()) {
1188 /*
1189 * Older KVM versions with older guest kernels were broken
1190 * with the magic page, don't allow the guest to map it.
1191 */
1192 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1193 sizeof(hypercall))) {
1194 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1195 hypercall, sizeof(hypercall)));
1196 }
1197 }
1198 }
1199
spapr_build_fdt(SpaprMachineState * spapr,bool reset)1200 static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset)
1201 {
1202 MachineState *machine = MACHINE(spapr);
1203 MachineClass *mc = MACHINE_GET_CLASS(machine);
1204 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1205 int ret;
1206 void *fdt;
1207 SpaprPhbState *phb;
1208 char *buf;
1209
1210 fdt = g_malloc0(FDT_MAX_SIZE);
1211 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1212
1213 /* Root node */
1214 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1215 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1216 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1217
1218 /* Guest UUID & Name*/
1219 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1220 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1221 if (qemu_uuid_set) {
1222 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1223 }
1224 g_free(buf);
1225
1226 if (qemu_get_vm_name()) {
1227 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1228 qemu_get_vm_name()));
1229 }
1230
1231 /* Host Model & Serial Number */
1232 if (spapr->host_model) {
1233 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model));
1234 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) {
1235 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1236 g_free(buf);
1237 }
1238
1239 if (spapr->host_serial) {
1240 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial));
1241 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) {
1242 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1243 g_free(buf);
1244 }
1245
1246 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1247 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1248
1249 /* /interrupt controller */
1250 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC);
1251
1252 ret = spapr_populate_memory(spapr, fdt);
1253 if (ret < 0) {
1254 error_report("couldn't setup memory nodes in fdt");
1255 exit(1);
1256 }
1257
1258 /* /vdevice */
1259 spapr_dt_vdevice(spapr->vio_bus, fdt);
1260
1261 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1262 ret = spapr_rng_populate_dt(fdt);
1263 if (ret < 0) {
1264 error_report("could not set up rng device in the fdt");
1265 exit(1);
1266 }
1267 }
1268
1269 QLIST_FOREACH(phb, &spapr->phbs, list) {
1270 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL);
1271 if (ret < 0) {
1272 error_report("couldn't setup PCI devices in fdt");
1273 exit(1);
1274 }
1275 }
1276
1277 /* cpus */
1278 spapr_populate_cpus_dt_node(fdt, spapr);
1279
1280 if (smc->dr_lmb_enabled) {
1281 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1282 }
1283
1284 if (mc->has_hotpluggable_cpus) {
1285 int offset = fdt_path_offset(fdt, "/cpus");
1286 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU);
1287 if (ret < 0) {
1288 error_report("Couldn't set up CPU DR device tree properties");
1289 exit(1);
1290 }
1291 }
1292
1293 /* /event-sources */
1294 spapr_dt_events(spapr, fdt);
1295
1296 /* /rtas */
1297 spapr_dt_rtas(spapr, fdt);
1298
1299 /* /chosen */
1300 if (reset) {
1301 spapr_dt_chosen(spapr, fdt);
1302 }
1303
1304 /* /hypervisor */
1305 if (kvm_enabled()) {
1306 spapr_dt_hypervisor(spapr, fdt);
1307 }
1308
1309 /* Build memory reserve map */
1310 if (reset) {
1311 if (spapr->kernel_size) {
1312 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1313 }
1314 if (spapr->initrd_size) {
1315 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base,
1316 spapr->initrd_size)));
1317 }
1318 }
1319
1320 /* ibm,client-architecture-support updates */
1321 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1322 if (ret < 0) {
1323 error_report("couldn't setup CAS properties fdt");
1324 exit(1);
1325 }
1326
1327 if (smc->dr_phb_enabled) {
1328 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB);
1329 if (ret < 0) {
1330 error_report("Couldn't set up PHB DR device tree properties");
1331 exit(1);
1332 }
1333 }
1334
1335 return fdt;
1336 }
1337
translate_kernel_address(void * opaque,uint64_t addr)1338 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1339 {
1340 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1341 }
1342
emulate_spapr_hypercall(PPCVirtualHypervisor * vhyp,PowerPCCPU * cpu)1343 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1344 PowerPCCPU *cpu)
1345 {
1346 CPUPPCState *env = &cpu->env;
1347
1348 /* The TCG path should also be holding the BQL at this point */
1349 g_assert(qemu_mutex_iothread_locked());
1350
1351 if (msr_pr) {
1352 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1353 env->gpr[3] = H_PRIVILEGE;
1354 } else {
1355 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1356 }
1357 }
1358
1359 struct LPCRSyncState {
1360 target_ulong value;
1361 target_ulong mask;
1362 };
1363
do_lpcr_sync(CPUState * cs,run_on_cpu_data arg)1364 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg)
1365 {
1366 struct LPCRSyncState *s = arg.host_ptr;
1367 PowerPCCPU *cpu = POWERPC_CPU(cs);
1368 CPUPPCState *env = &cpu->env;
1369 target_ulong lpcr;
1370
1371 cpu_synchronize_state(cs);
1372 lpcr = env->spr[SPR_LPCR];
1373 lpcr &= ~s->mask;
1374 lpcr |= s->value;
1375 ppc_store_lpcr(cpu, lpcr);
1376 }
1377
spapr_set_all_lpcrs(target_ulong value,target_ulong mask)1378 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask)
1379 {
1380 CPUState *cs;
1381 struct LPCRSyncState s = {
1382 .value = value,
1383 .mask = mask
1384 };
1385 CPU_FOREACH(cs) {
1386 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s));
1387 }
1388 }
1389
spapr_get_pate(PPCVirtualHypervisor * vhyp,ppc_v3_pate_t * entry)1390 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry)
1391 {
1392 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1393
1394 /* Copy PATE1:GR into PATE0:HR */
1395 entry->dw0 = spapr->patb_entry & PATE0_HR;
1396 entry->dw1 = spapr->patb_entry;
1397 }
1398
1399 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1400 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1401 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1402 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1403 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1404
1405 /*
1406 * Get the fd to access the kernel htab, re-opening it if necessary
1407 */
get_htab_fd(SpaprMachineState * spapr)1408 static int get_htab_fd(SpaprMachineState *spapr)
1409 {
1410 Error *local_err = NULL;
1411
1412 if (spapr->htab_fd >= 0) {
1413 return spapr->htab_fd;
1414 }
1415
1416 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1417 if (spapr->htab_fd < 0) {
1418 error_report_err(local_err);
1419 }
1420
1421 return spapr->htab_fd;
1422 }
1423
close_htab_fd(SpaprMachineState * spapr)1424 void close_htab_fd(SpaprMachineState *spapr)
1425 {
1426 if (spapr->htab_fd >= 0) {
1427 close(spapr->htab_fd);
1428 }
1429 spapr->htab_fd = -1;
1430 }
1431
spapr_hpt_mask(PPCVirtualHypervisor * vhyp)1432 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1433 {
1434 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1435
1436 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1437 }
1438
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor * vhyp)1439 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1440 {
1441 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1442
1443 assert(kvm_enabled());
1444
1445 if (!spapr->htab) {
1446 return 0;
1447 }
1448
1449 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1450 }
1451
spapr_map_hptes(PPCVirtualHypervisor * vhyp,hwaddr ptex,int n)1452 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1453 hwaddr ptex, int n)
1454 {
1455 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1456 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1457
1458 if (!spapr->htab) {
1459 /*
1460 * HTAB is controlled by KVM. Fetch into temporary buffer
1461 */
1462 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1463 kvmppc_read_hptes(hptes, ptex, n);
1464 return hptes;
1465 }
1466
1467 /*
1468 * HTAB is controlled by QEMU. Just point to the internally
1469 * accessible PTEG.
1470 */
1471 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1472 }
1473
spapr_unmap_hptes(PPCVirtualHypervisor * vhyp,const ppc_hash_pte64_t * hptes,hwaddr ptex,int n)1474 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1475 const ppc_hash_pte64_t *hptes,
1476 hwaddr ptex, int n)
1477 {
1478 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1479
1480 if (!spapr->htab) {
1481 g_free((void *)hptes);
1482 }
1483
1484 /* Nothing to do for qemu managed HPT */
1485 }
1486
spapr_store_hpte(PowerPCCPU * cpu,hwaddr ptex,uint64_t pte0,uint64_t pte1)1487 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
1488 uint64_t pte0, uint64_t pte1)
1489 {
1490 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp);
1491 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1492
1493 if (!spapr->htab) {
1494 kvmppc_write_hpte(ptex, pte0, pte1);
1495 } else {
1496 if (pte0 & HPTE64_V_VALID) {
1497 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1498 /*
1499 * When setting valid, we write PTE1 first. This ensures
1500 * proper synchronization with the reading code in
1501 * ppc_hash64_pteg_search()
1502 */
1503 smp_wmb();
1504 stq_p(spapr->htab + offset, pte0);
1505 } else {
1506 stq_p(spapr->htab + offset, pte0);
1507 /*
1508 * When clearing it we set PTE0 first. This ensures proper
1509 * synchronization with the reading code in
1510 * ppc_hash64_pteg_search()
1511 */
1512 smp_wmb();
1513 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1514 }
1515 }
1516 }
1517
spapr_hpte_set_c(PPCVirtualHypervisor * vhyp,hwaddr ptex,uint64_t pte1)1518 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1519 uint64_t pte1)
1520 {
1521 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15;
1522 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1523
1524 if (!spapr->htab) {
1525 /* There should always be a hash table when this is called */
1526 error_report("spapr_hpte_set_c called with no hash table !");
1527 return;
1528 }
1529
1530 /* The HW performs a non-atomic byte update */
1531 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80);
1532 }
1533
spapr_hpte_set_r(PPCVirtualHypervisor * vhyp,hwaddr ptex,uint64_t pte1)1534 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1535 uint64_t pte1)
1536 {
1537 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14;
1538 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1539
1540 if (!spapr->htab) {
1541 /* There should always be a hash table when this is called */
1542 error_report("spapr_hpte_set_r called with no hash table !");
1543 return;
1544 }
1545
1546 /* The HW performs a non-atomic byte update */
1547 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01);
1548 }
1549
spapr_hpt_shift_for_ramsize(uint64_t ramsize)1550 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1551 {
1552 int shift;
1553
1554 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1555 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1556 * that's much more than is needed for Linux guests */
1557 shift = ctz64(pow2ceil(ramsize)) - 7;
1558 shift = MAX(shift, 18); /* Minimum architected size */
1559 shift = MIN(shift, 46); /* Maximum architected size */
1560 return shift;
1561 }
1562
spapr_free_hpt(SpaprMachineState * spapr)1563 void spapr_free_hpt(SpaprMachineState *spapr)
1564 {
1565 g_free(spapr->htab);
1566 spapr->htab = NULL;
1567 spapr->htab_shift = 0;
1568 close_htab_fd(spapr);
1569 }
1570
spapr_reallocate_hpt(SpaprMachineState * spapr,int shift,Error ** errp)1571 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
1572 Error **errp)
1573 {
1574 long rc;
1575
1576 /* Clean up any HPT info from a previous boot */
1577 spapr_free_hpt(spapr);
1578
1579 rc = kvmppc_reset_htab(shift);
1580 if (rc < 0) {
1581 /* kernel-side HPT needed, but couldn't allocate one */
1582 error_setg_errno(errp, errno,
1583 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1584 shift);
1585 /* This is almost certainly fatal, but if the caller really
1586 * wants to carry on with shift == 0, it's welcome to try */
1587 } else if (rc > 0) {
1588 /* kernel-side HPT allocated */
1589 if (rc != shift) {
1590 error_setg(errp,
1591 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1592 shift, rc);
1593 }
1594
1595 spapr->htab_shift = shift;
1596 spapr->htab = NULL;
1597 } else {
1598 /* kernel-side HPT not needed, allocate in userspace instead */
1599 size_t size = 1ULL << shift;
1600 int i;
1601
1602 spapr->htab = qemu_memalign(size, size);
1603 if (!spapr->htab) {
1604 error_setg_errno(errp, errno,
1605 "Could not allocate HPT of order %d", shift);
1606 return;
1607 }
1608
1609 memset(spapr->htab, 0, size);
1610 spapr->htab_shift = shift;
1611
1612 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1613 DIRTY_HPTE(HPTE(spapr->htab, i));
1614 }
1615 }
1616 /* We're setting up a hash table, so that means we're not radix */
1617 spapr->patb_entry = 0;
1618 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
1619 }
1620
spapr_setup_hpt_and_vrma(SpaprMachineState * spapr)1621 void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr)
1622 {
1623 int hpt_shift;
1624
1625 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1626 || (spapr->cas_reboot
1627 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1628 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1629 } else {
1630 uint64_t current_ram_size;
1631
1632 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1633 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1634 }
1635 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1636
1637 if (spapr->vrma_adjust) {
1638 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1639 spapr->htab_shift);
1640 }
1641 }
1642
spapr_reset_drcs(Object * child,void * opaque)1643 static int spapr_reset_drcs(Object *child, void *opaque)
1644 {
1645 SpaprDrc *drc =
1646 (SpaprDrc *) object_dynamic_cast(child,
1647 TYPE_SPAPR_DR_CONNECTOR);
1648
1649 if (drc) {
1650 spapr_drc_reset(drc);
1651 }
1652
1653 return 0;
1654 }
1655
spapr_machine_reset(MachineState * machine)1656 static void spapr_machine_reset(MachineState *machine)
1657 {
1658 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
1659 PowerPCCPU *first_ppc_cpu;
1660 hwaddr fdt_addr;
1661 void *fdt;
1662 int rc;
1663
1664 spapr_caps_apply(spapr);
1665
1666 first_ppc_cpu = POWERPC_CPU(first_cpu);
1667 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1668 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1669 spapr->max_compat_pvr)) {
1670 /*
1671 * If using KVM with radix mode available, VCPUs can be started
1672 * without a HPT because KVM will start them in radix mode.
1673 * Set the GR bit in PATE so that we know there is no HPT.
1674 */
1675 spapr->patb_entry = PATE1_GR;
1676 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT);
1677 } else {
1678 spapr_setup_hpt_and_vrma(spapr);
1679 }
1680
1681 qemu_devices_reset();
1682
1683 /*
1684 * If this reset wasn't generated by CAS, we should reset our
1685 * negotiated options and start from scratch
1686 */
1687 if (!spapr->cas_reboot) {
1688 spapr_ovec_cleanup(spapr->ov5_cas);
1689 spapr->ov5_cas = spapr_ovec_new();
1690
1691 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
1692 }
1693
1694 /*
1695 * This is fixing some of the default configuration of the XIVE
1696 * devices. To be called after the reset of the machine devices.
1697 */
1698 spapr_irq_reset(spapr, &error_fatal);
1699
1700 /*
1701 * There is no CAS under qtest. Simulate one to please the code that
1702 * depends on spapr->ov5_cas. This is especially needed to test device
1703 * unplug, so we do that before resetting the DRCs.
1704 */
1705 if (qtest_enabled()) {
1706 spapr_ovec_cleanup(spapr->ov5_cas);
1707 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
1708 }
1709
1710 /* DRC reset may cause a device to be unplugged. This will cause troubles
1711 * if this device is used by another device (eg, a running vhost backend
1712 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1713 * situations, we reset DRCs after all devices have been reset.
1714 */
1715 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1716
1717 spapr_clear_pending_events(spapr);
1718
1719 /*
1720 * We place the device tree and RTAS just below either the top of the RMA,
1721 * or just below 2GB, whichever is lower, so that it can be
1722 * processed with 32-bit real mode code if necessary
1723 */
1724 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE;
1725
1726 fdt = spapr_build_fdt(spapr, true);
1727
1728 rc = fdt_pack(fdt);
1729
1730 /* Should only fail if we've built a corrupted tree */
1731 assert(rc == 0);
1732
1733 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1734 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1735 fdt_totalsize(fdt), FDT_MAX_SIZE);
1736 exit(1);
1737 }
1738
1739 /* Load the fdt */
1740 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1741 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1742 g_free(spapr->fdt_blob);
1743 spapr->fdt_size = fdt_totalsize(fdt);
1744 spapr->fdt_initial_size = spapr->fdt_size;
1745 spapr->fdt_blob = fdt;
1746
1747 /* Set up the entry state */
1748 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr);
1749 first_ppc_cpu->env.gpr[5] = 0;
1750
1751 spapr->cas_reboot = false;
1752 }
1753
spapr_create_nvram(SpaprMachineState * spapr)1754 static void spapr_create_nvram(SpaprMachineState *spapr)
1755 {
1756 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1757 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1758
1759 if (dinfo) {
1760 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1761 &error_fatal);
1762 }
1763
1764 qdev_init_nofail(dev);
1765
1766 spapr->nvram = (struct SpaprNvram *)dev;
1767 }
1768
spapr_rtc_create(SpaprMachineState * spapr)1769 static void spapr_rtc_create(SpaprMachineState *spapr)
1770 {
1771 object_initialize_child(OBJECT(spapr), "rtc",
1772 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC,
1773 &error_fatal, NULL);
1774 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1775 &error_fatal);
1776 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1777 "date", &error_fatal);
1778 }
1779
1780 /* Returns whether we want to use VGA or not */
spapr_vga_init(PCIBus * pci_bus,Error ** errp)1781 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1782 {
1783 switch (vga_interface_type) {
1784 case VGA_NONE:
1785 return false;
1786 case VGA_DEVICE:
1787 return true;
1788 case VGA_STD:
1789 case VGA_VIRTIO:
1790 case VGA_CIRRUS:
1791 return pci_vga_init(pci_bus) != NULL;
1792 default:
1793 error_setg(errp,
1794 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1795 return false;
1796 }
1797 }
1798
spapr_pre_load(void * opaque)1799 static int spapr_pre_load(void *opaque)
1800 {
1801 int rc;
1802
1803 rc = spapr_caps_pre_load(opaque);
1804 if (rc) {
1805 return rc;
1806 }
1807
1808 return 0;
1809 }
1810
spapr_post_load(void * opaque,int version_id)1811 static int spapr_post_load(void *opaque, int version_id)
1812 {
1813 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1814 int err = 0;
1815
1816 err = spapr_caps_post_migration(spapr);
1817 if (err) {
1818 return err;
1819 }
1820
1821 /*
1822 * In earlier versions, there was no separate qdev for the PAPR
1823 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1824 * So when migrating from those versions, poke the incoming offset
1825 * value into the RTC device
1826 */
1827 if (version_id < 3) {
1828 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1829 if (err) {
1830 return err;
1831 }
1832 }
1833
1834 if (kvm_enabled() && spapr->patb_entry) {
1835 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1836 bool radix = !!(spapr->patb_entry & PATE1_GR);
1837 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1838
1839 /*
1840 * Update LPCR:HR and UPRT as they may not be set properly in
1841 * the stream
1842 */
1843 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0,
1844 LPCR_HR | LPCR_UPRT);
1845
1846 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1847 if (err) {
1848 error_report("Process table config unsupported by the host");
1849 return -EINVAL;
1850 }
1851 }
1852
1853 err = spapr_irq_post_load(spapr, version_id);
1854 if (err) {
1855 return err;
1856 }
1857
1858 return err;
1859 }
1860
spapr_pre_save(void * opaque)1861 static int spapr_pre_save(void *opaque)
1862 {
1863 int rc;
1864
1865 rc = spapr_caps_pre_save(opaque);
1866 if (rc) {
1867 return rc;
1868 }
1869
1870 return 0;
1871 }
1872
version_before_3(void * opaque,int version_id)1873 static bool version_before_3(void *opaque, int version_id)
1874 {
1875 return version_id < 3;
1876 }
1877
spapr_pending_events_needed(void * opaque)1878 static bool spapr_pending_events_needed(void *opaque)
1879 {
1880 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1881 return !QTAILQ_EMPTY(&spapr->pending_events);
1882 }
1883
1884 static const VMStateDescription vmstate_spapr_event_entry = {
1885 .name = "spapr_event_log_entry",
1886 .version_id = 1,
1887 .minimum_version_id = 1,
1888 .fields = (VMStateField[]) {
1889 VMSTATE_UINT32(summary, SpaprEventLogEntry),
1890 VMSTATE_UINT32(extended_length, SpaprEventLogEntry),
1891 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0,
1892 NULL, extended_length),
1893 VMSTATE_END_OF_LIST()
1894 },
1895 };
1896
1897 static const VMStateDescription vmstate_spapr_pending_events = {
1898 .name = "spapr_pending_events",
1899 .version_id = 1,
1900 .minimum_version_id = 1,
1901 .needed = spapr_pending_events_needed,
1902 .fields = (VMStateField[]) {
1903 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1,
1904 vmstate_spapr_event_entry, SpaprEventLogEntry, next),
1905 VMSTATE_END_OF_LIST()
1906 },
1907 };
1908
spapr_ov5_cas_needed(void * opaque)1909 static bool spapr_ov5_cas_needed(void *opaque)
1910 {
1911 SpaprMachineState *spapr = opaque;
1912 SpaprOptionVector *ov5_mask = spapr_ovec_new();
1913 SpaprOptionVector *ov5_legacy = spapr_ovec_new();
1914 SpaprOptionVector *ov5_removed = spapr_ovec_new();
1915 bool cas_needed;
1916
1917 /* Prior to the introduction of SpaprOptionVector, we had two option
1918 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1919 * Both of these options encode machine topology into the device-tree
1920 * in such a way that the now-booted OS should still be able to interact
1921 * appropriately with QEMU regardless of what options were actually
1922 * negotiatied on the source side.
1923 *
1924 * As such, we can avoid migrating the CAS-negotiated options if these
1925 * are the only options available on the current machine/platform.
1926 * Since these are the only options available for pseries-2.7 and
1927 * earlier, this allows us to maintain old->new/new->old migration
1928 * compatibility.
1929 *
1930 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1931 * via default pseries-2.8 machines and explicit command-line parameters.
1932 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1933 * of the actual CAS-negotiated values to continue working properly. For
1934 * example, availability of memory unplug depends on knowing whether
1935 * OV5_HP_EVT was negotiated via CAS.
1936 *
1937 * Thus, for any cases where the set of available CAS-negotiatable
1938 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1939 * include the CAS-negotiated options in the migration stream, unless
1940 * if they affect boot time behaviour only.
1941 */
1942 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1943 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1944 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
1945
1946 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1947 * the mask itself since in the future it's possible "legacy" bits may be
1948 * removed via machine options, which could generate a false positive
1949 * that breaks migration.
1950 */
1951 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1952 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1953
1954 spapr_ovec_cleanup(ov5_mask);
1955 spapr_ovec_cleanup(ov5_legacy);
1956 spapr_ovec_cleanup(ov5_removed);
1957
1958 return cas_needed;
1959 }
1960
1961 static const VMStateDescription vmstate_spapr_ov5_cas = {
1962 .name = "spapr_option_vector_ov5_cas",
1963 .version_id = 1,
1964 .minimum_version_id = 1,
1965 .needed = spapr_ov5_cas_needed,
1966 .fields = (VMStateField[]) {
1967 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1,
1968 vmstate_spapr_ovec, SpaprOptionVector),
1969 VMSTATE_END_OF_LIST()
1970 },
1971 };
1972
spapr_patb_entry_needed(void * opaque)1973 static bool spapr_patb_entry_needed(void *opaque)
1974 {
1975 SpaprMachineState *spapr = opaque;
1976
1977 return !!spapr->patb_entry;
1978 }
1979
1980 static const VMStateDescription vmstate_spapr_patb_entry = {
1981 .name = "spapr_patb_entry",
1982 .version_id = 1,
1983 .minimum_version_id = 1,
1984 .needed = spapr_patb_entry_needed,
1985 .fields = (VMStateField[]) {
1986 VMSTATE_UINT64(patb_entry, SpaprMachineState),
1987 VMSTATE_END_OF_LIST()
1988 },
1989 };
1990
spapr_irq_map_needed(void * opaque)1991 static bool spapr_irq_map_needed(void *opaque)
1992 {
1993 SpaprMachineState *spapr = opaque;
1994
1995 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
1996 }
1997
1998 static const VMStateDescription vmstate_spapr_irq_map = {
1999 .name = "spapr_irq_map",
2000 .version_id = 1,
2001 .minimum_version_id = 1,
2002 .needed = spapr_irq_map_needed,
2003 .fields = (VMStateField[]) {
2004 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr),
2005 VMSTATE_END_OF_LIST()
2006 },
2007 };
2008
spapr_dtb_needed(void * opaque)2009 static bool spapr_dtb_needed(void *opaque)
2010 {
2011 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque);
2012
2013 return smc->update_dt_enabled;
2014 }
2015
spapr_dtb_pre_load(void * opaque)2016 static int spapr_dtb_pre_load(void *opaque)
2017 {
2018 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
2019
2020 g_free(spapr->fdt_blob);
2021 spapr->fdt_blob = NULL;
2022 spapr->fdt_size = 0;
2023
2024 return 0;
2025 }
2026
2027 static const VMStateDescription vmstate_spapr_dtb = {
2028 .name = "spapr_dtb",
2029 .version_id = 1,
2030 .minimum_version_id = 1,
2031 .needed = spapr_dtb_needed,
2032 .pre_load = spapr_dtb_pre_load,
2033 .fields = (VMStateField[]) {
2034 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState),
2035 VMSTATE_UINT32(fdt_size, SpaprMachineState),
2036 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL,
2037 fdt_size),
2038 VMSTATE_END_OF_LIST()
2039 },
2040 };
2041
2042 static const VMStateDescription vmstate_spapr = {
2043 .name = "spapr",
2044 .version_id = 3,
2045 .minimum_version_id = 1,
2046 .pre_load = spapr_pre_load,
2047 .post_load = spapr_post_load,
2048 .pre_save = spapr_pre_save,
2049 .fields = (VMStateField[]) {
2050 /* used to be @next_irq */
2051 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
2052
2053 /* RTC offset */
2054 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3),
2055
2056 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2),
2057 VMSTATE_END_OF_LIST()
2058 },
2059 .subsections = (const VMStateDescription*[]) {
2060 &vmstate_spapr_ov5_cas,
2061 &vmstate_spapr_patb_entry,
2062 &vmstate_spapr_pending_events,
2063 &vmstate_spapr_cap_htm,
2064 &vmstate_spapr_cap_vsx,
2065 &vmstate_spapr_cap_dfp,
2066 &vmstate_spapr_cap_cfpc,
2067 &vmstate_spapr_cap_sbbc,
2068 &vmstate_spapr_cap_ibs,
2069 &vmstate_spapr_cap_hpt_maxpagesize,
2070 &vmstate_spapr_irq_map,
2071 &vmstate_spapr_cap_nested_kvm_hv,
2072 &vmstate_spapr_dtb,
2073 &vmstate_spapr_cap_large_decr,
2074 &vmstate_spapr_cap_ccf_assist,
2075 NULL
2076 }
2077 };
2078
htab_save_setup(QEMUFile * f,void * opaque)2079 static int htab_save_setup(QEMUFile *f, void *opaque)
2080 {
2081 SpaprMachineState *spapr = opaque;
2082
2083 /* "Iteration" header */
2084 if (!spapr->htab_shift) {
2085 qemu_put_be32(f, -1);
2086 } else {
2087 qemu_put_be32(f, spapr->htab_shift);
2088 }
2089
2090 if (spapr->htab) {
2091 spapr->htab_save_index = 0;
2092 spapr->htab_first_pass = true;
2093 } else {
2094 if (spapr->htab_shift) {
2095 assert(kvm_enabled());
2096 }
2097 }
2098
2099
2100 return 0;
2101 }
2102
htab_save_chunk(QEMUFile * f,SpaprMachineState * spapr,int chunkstart,int n_valid,int n_invalid)2103 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr,
2104 int chunkstart, int n_valid, int n_invalid)
2105 {
2106 qemu_put_be32(f, chunkstart);
2107 qemu_put_be16(f, n_valid);
2108 qemu_put_be16(f, n_invalid);
2109 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
2110 HASH_PTE_SIZE_64 * n_valid);
2111 }
2112
htab_save_end_marker(QEMUFile * f)2113 static void htab_save_end_marker(QEMUFile *f)
2114 {
2115 qemu_put_be32(f, 0);
2116 qemu_put_be16(f, 0);
2117 qemu_put_be16(f, 0);
2118 }
2119
htab_save_first_pass(QEMUFile * f,SpaprMachineState * spapr,int64_t max_ns)2120 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr,
2121 int64_t max_ns)
2122 {
2123 bool has_timeout = max_ns != -1;
2124 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2125 int index = spapr->htab_save_index;
2126 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2127
2128 assert(spapr->htab_first_pass);
2129
2130 do {
2131 int chunkstart;
2132
2133 /* Consume invalid HPTEs */
2134 while ((index < htabslots)
2135 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2136 CLEAN_HPTE(HPTE(spapr->htab, index));
2137 index++;
2138 }
2139
2140 /* Consume valid HPTEs */
2141 chunkstart = index;
2142 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2143 && HPTE_VALID(HPTE(spapr->htab, index))) {
2144 CLEAN_HPTE(HPTE(spapr->htab, index));
2145 index++;
2146 }
2147
2148 if (index > chunkstart) {
2149 int n_valid = index - chunkstart;
2150
2151 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2152
2153 if (has_timeout &&
2154 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2155 break;
2156 }
2157 }
2158 } while ((index < htabslots) && !qemu_file_rate_limit(f));
2159
2160 if (index >= htabslots) {
2161 assert(index == htabslots);
2162 index = 0;
2163 spapr->htab_first_pass = false;
2164 }
2165 spapr->htab_save_index = index;
2166 }
2167
htab_save_later_pass(QEMUFile * f,SpaprMachineState * spapr,int64_t max_ns)2168 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr,
2169 int64_t max_ns)
2170 {
2171 bool final = max_ns < 0;
2172 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2173 int examined = 0, sent = 0;
2174 int index = spapr->htab_save_index;
2175 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2176
2177 assert(!spapr->htab_first_pass);
2178
2179 do {
2180 int chunkstart, invalidstart;
2181
2182 /* Consume non-dirty HPTEs */
2183 while ((index < htabslots)
2184 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2185 index++;
2186 examined++;
2187 }
2188
2189 chunkstart = index;
2190 /* Consume valid dirty HPTEs */
2191 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2192 && HPTE_DIRTY(HPTE(spapr->htab, index))
2193 && HPTE_VALID(HPTE(spapr->htab, index))) {
2194 CLEAN_HPTE(HPTE(spapr->htab, index));
2195 index++;
2196 examined++;
2197 }
2198
2199 invalidstart = index;
2200 /* Consume invalid dirty HPTEs */
2201 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2202 && HPTE_DIRTY(HPTE(spapr->htab, index))
2203 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2204 CLEAN_HPTE(HPTE(spapr->htab, index));
2205 index++;
2206 examined++;
2207 }
2208
2209 if (index > chunkstart) {
2210 int n_valid = invalidstart - chunkstart;
2211 int n_invalid = index - invalidstart;
2212
2213 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2214 sent += index - chunkstart;
2215
2216 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2217 break;
2218 }
2219 }
2220
2221 if (examined >= htabslots) {
2222 break;
2223 }
2224
2225 if (index >= htabslots) {
2226 assert(index == htabslots);
2227 index = 0;
2228 }
2229 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2230
2231 if (index >= htabslots) {
2232 assert(index == htabslots);
2233 index = 0;
2234 }
2235
2236 spapr->htab_save_index = index;
2237
2238 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2239 }
2240
2241 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2242 #define MAX_KVM_BUF_SIZE 2048
2243
htab_save_iterate(QEMUFile * f,void * opaque)2244 static int htab_save_iterate(QEMUFile *f, void *opaque)
2245 {
2246 SpaprMachineState *spapr = opaque;
2247 int fd;
2248 int rc = 0;
2249
2250 /* Iteration header */
2251 if (!spapr->htab_shift) {
2252 qemu_put_be32(f, -1);
2253 return 1;
2254 } else {
2255 qemu_put_be32(f, 0);
2256 }
2257
2258 if (!spapr->htab) {
2259 assert(kvm_enabled());
2260
2261 fd = get_htab_fd(spapr);
2262 if (fd < 0) {
2263 return fd;
2264 }
2265
2266 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2267 if (rc < 0) {
2268 return rc;
2269 }
2270 } else if (spapr->htab_first_pass) {
2271 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2272 } else {
2273 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2274 }
2275
2276 htab_save_end_marker(f);
2277
2278 return rc;
2279 }
2280
htab_save_complete(QEMUFile * f,void * opaque)2281 static int htab_save_complete(QEMUFile *f, void *opaque)
2282 {
2283 SpaprMachineState *spapr = opaque;
2284 int fd;
2285
2286 /* Iteration header */
2287 if (!spapr->htab_shift) {
2288 qemu_put_be32(f, -1);
2289 return 0;
2290 } else {
2291 qemu_put_be32(f, 0);
2292 }
2293
2294 if (!spapr->htab) {
2295 int rc;
2296
2297 assert(kvm_enabled());
2298
2299 fd = get_htab_fd(spapr);
2300 if (fd < 0) {
2301 return fd;
2302 }
2303
2304 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2305 if (rc < 0) {
2306 return rc;
2307 }
2308 } else {
2309 if (spapr->htab_first_pass) {
2310 htab_save_first_pass(f, spapr, -1);
2311 }
2312 htab_save_later_pass(f, spapr, -1);
2313 }
2314
2315 /* End marker */
2316 htab_save_end_marker(f);
2317
2318 return 0;
2319 }
2320
htab_load(QEMUFile * f,void * opaque,int version_id)2321 static int htab_load(QEMUFile *f, void *opaque, int version_id)
2322 {
2323 SpaprMachineState *spapr = opaque;
2324 uint32_t section_hdr;
2325 int fd = -1;
2326 Error *local_err = NULL;
2327
2328 if (version_id < 1 || version_id > 1) {
2329 error_report("htab_load() bad version");
2330 return -EINVAL;
2331 }
2332
2333 section_hdr = qemu_get_be32(f);
2334
2335 if (section_hdr == -1) {
2336 spapr_free_hpt(spapr);
2337 return 0;
2338 }
2339
2340 if (section_hdr) {
2341 /* First section gives the htab size */
2342 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2343 if (local_err) {
2344 error_report_err(local_err);
2345 return -EINVAL;
2346 }
2347 return 0;
2348 }
2349
2350 if (!spapr->htab) {
2351 assert(kvm_enabled());
2352
2353 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2354 if (fd < 0) {
2355 error_report_err(local_err);
2356 return fd;
2357 }
2358 }
2359
2360 while (true) {
2361 uint32_t index;
2362 uint16_t n_valid, n_invalid;
2363
2364 index = qemu_get_be32(f);
2365 n_valid = qemu_get_be16(f);
2366 n_invalid = qemu_get_be16(f);
2367
2368 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2369 /* End of Stream */
2370 break;
2371 }
2372
2373 if ((index + n_valid + n_invalid) >
2374 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2375 /* Bad index in stream */
2376 error_report(
2377 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2378 index, n_valid, n_invalid, spapr->htab_shift);
2379 return -EINVAL;
2380 }
2381
2382 if (spapr->htab) {
2383 if (n_valid) {
2384 qemu_get_buffer(f, HPTE(spapr->htab, index),
2385 HASH_PTE_SIZE_64 * n_valid);
2386 }
2387 if (n_invalid) {
2388 memset(HPTE(spapr->htab, index + n_valid), 0,
2389 HASH_PTE_SIZE_64 * n_invalid);
2390 }
2391 } else {
2392 int rc;
2393
2394 assert(fd >= 0);
2395
2396 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2397 if (rc < 0) {
2398 return rc;
2399 }
2400 }
2401 }
2402
2403 if (!spapr->htab) {
2404 assert(fd >= 0);
2405 close(fd);
2406 }
2407
2408 return 0;
2409 }
2410
htab_save_cleanup(void * opaque)2411 static void htab_save_cleanup(void *opaque)
2412 {
2413 SpaprMachineState *spapr = opaque;
2414
2415 close_htab_fd(spapr);
2416 }
2417
2418 static SaveVMHandlers savevm_htab_handlers = {
2419 .save_setup = htab_save_setup,
2420 .save_live_iterate = htab_save_iterate,
2421 .save_live_complete_precopy = htab_save_complete,
2422 .save_cleanup = htab_save_cleanup,
2423 .load_state = htab_load,
2424 };
2425
spapr_boot_set(void * opaque,const char * boot_device,Error ** errp)2426 static void spapr_boot_set(void *opaque, const char *boot_device,
2427 Error **errp)
2428 {
2429 MachineState *machine = MACHINE(opaque);
2430 machine->boot_order = g_strdup(boot_device);
2431 }
2432
spapr_create_lmb_dr_connectors(SpaprMachineState * spapr)2433 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr)
2434 {
2435 MachineState *machine = MACHINE(spapr);
2436 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2437 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2438 int i;
2439
2440 for (i = 0; i < nr_lmbs; i++) {
2441 uint64_t addr;
2442
2443 addr = i * lmb_size + machine->device_memory->base;
2444 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2445 addr / lmb_size);
2446 }
2447 }
2448
2449 /*
2450 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2451 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2452 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2453 */
spapr_validate_node_memory(MachineState * machine,Error ** errp)2454 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2455 {
2456 int i;
2457
2458 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2459 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2460 " is not aligned to %" PRIu64 " MiB",
2461 machine->ram_size,
2462 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2463 return;
2464 }
2465
2466 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2467 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2468 " is not aligned to %" PRIu64 " MiB",
2469 machine->ram_size,
2470 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2471 return;
2472 }
2473
2474 for (i = 0; i < machine->numa_state->num_nodes; i++) {
2475 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2476 error_setg(errp,
2477 "Node %d memory size 0x%" PRIx64
2478 " is not aligned to %" PRIu64 " MiB",
2479 i, machine->numa_state->nodes[i].node_mem,
2480 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2481 return;
2482 }
2483 }
2484 }
2485
2486 /* find cpu slot in machine->possible_cpus by core_id */
spapr_find_cpu_slot(MachineState * ms,uint32_t id,int * idx)2487 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2488 {
2489 int index = id / ms->smp.threads;
2490
2491 if (index >= ms->possible_cpus->len) {
2492 return NULL;
2493 }
2494 if (idx) {
2495 *idx = index;
2496 }
2497 return &ms->possible_cpus->cpus[index];
2498 }
2499
spapr_set_vsmt_mode(SpaprMachineState * spapr,Error ** errp)2500 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
2501 {
2502 MachineState *ms = MACHINE(spapr);
2503 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
2504 Error *local_err = NULL;
2505 bool vsmt_user = !!spapr->vsmt;
2506 int kvm_smt = kvmppc_smt_threads();
2507 int ret;
2508 unsigned int smp_threads = ms->smp.threads;
2509
2510 if (!kvm_enabled() && (smp_threads > 1)) {
2511 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2512 "on a pseries machine");
2513 goto out;
2514 }
2515 if (!is_power_of_2(smp_threads)) {
2516 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2517 "machine because it must be a power of 2", smp_threads);
2518 goto out;
2519 }
2520
2521 /* Detemine the VSMT mode to use: */
2522 if (vsmt_user) {
2523 if (spapr->vsmt < smp_threads) {
2524 error_setg(&local_err, "Cannot support VSMT mode %d"
2525 " because it must be >= threads/core (%d)",
2526 spapr->vsmt, smp_threads);
2527 goto out;
2528 }
2529 /* In this case, spapr->vsmt has been set by the command line */
2530 } else if (!smc->smp_threads_vsmt) {
2531 /*
2532 * Default VSMT value is tricky, because we need it to be as
2533 * consistent as possible (for migration), but this requires
2534 * changing it for at least some existing cases. We pick 8 as
2535 * the value that we'd get with KVM on POWER8, the
2536 * overwhelmingly common case in production systems.
2537 */
2538 spapr->vsmt = MAX(8, smp_threads);
2539 } else {
2540 spapr->vsmt = smp_threads;
2541 }
2542
2543 /* KVM: If necessary, set the SMT mode: */
2544 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2545 ret = kvmppc_set_smt_threads(spapr->vsmt);
2546 if (ret) {
2547 /* Looks like KVM isn't able to change VSMT mode */
2548 error_setg(&local_err,
2549 "Failed to set KVM's VSMT mode to %d (errno %d)",
2550 spapr->vsmt, ret);
2551 /* We can live with that if the default one is big enough
2552 * for the number of threads, and a submultiple of the one
2553 * we want. In this case we'll waste some vcpu ids, but
2554 * behaviour will be correct */
2555 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2556 warn_report_err(local_err);
2557 local_err = NULL;
2558 goto out;
2559 } else {
2560 if (!vsmt_user) {
2561 error_append_hint(&local_err,
2562 "On PPC, a VM with %d threads/core"
2563 " on a host with %d threads/core"
2564 " requires the use of VSMT mode %d.\n",
2565 smp_threads, kvm_smt, spapr->vsmt);
2566 }
2567 kvmppc_hint_smt_possible(&local_err);
2568 goto out;
2569 }
2570 }
2571 }
2572 /* else TCG: nothing to do currently */
2573 out:
2574 error_propagate(errp, local_err);
2575 }
2576
spapr_init_cpus(SpaprMachineState * spapr)2577 static void spapr_init_cpus(SpaprMachineState *spapr)
2578 {
2579 MachineState *machine = MACHINE(spapr);
2580 MachineClass *mc = MACHINE_GET_CLASS(machine);
2581 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2582 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2583 const CPUArchIdList *possible_cpus;
2584 unsigned int smp_cpus = machine->smp.cpus;
2585 unsigned int smp_threads = machine->smp.threads;
2586 unsigned int max_cpus = machine->smp.max_cpus;
2587 int boot_cores_nr = smp_cpus / smp_threads;
2588 int i;
2589
2590 possible_cpus = mc->possible_cpu_arch_ids(machine);
2591 if (mc->has_hotpluggable_cpus) {
2592 if (smp_cpus % smp_threads) {
2593 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2594 smp_cpus, smp_threads);
2595 exit(1);
2596 }
2597 if (max_cpus % smp_threads) {
2598 error_report("max_cpus (%u) must be multiple of threads (%u)",
2599 max_cpus, smp_threads);
2600 exit(1);
2601 }
2602 } else {
2603 if (max_cpus != smp_cpus) {
2604 error_report("This machine version does not support CPU hotplug");
2605 exit(1);
2606 }
2607 boot_cores_nr = possible_cpus->len;
2608 }
2609
2610 if (smc->pre_2_10_has_unused_icps) {
2611 int i;
2612
2613 for (i = 0; i < spapr_max_server_number(spapr); i++) {
2614 /* Dummy entries get deregistered when real ICPState objects
2615 * are registered during CPU core hotplug.
2616 */
2617 pre_2_10_vmstate_register_dummy_icp(i);
2618 }
2619 }
2620
2621 for (i = 0; i < possible_cpus->len; i++) {
2622 int core_id = i * smp_threads;
2623
2624 if (mc->has_hotpluggable_cpus) {
2625 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2626 spapr_vcpu_id(spapr, core_id));
2627 }
2628
2629 if (i < boot_cores_nr) {
2630 Object *core = object_new(type);
2631 int nr_threads = smp_threads;
2632
2633 /* Handle the partially filled core for older machine types */
2634 if ((i + 1) * smp_threads >= smp_cpus) {
2635 nr_threads = smp_cpus - i * smp_threads;
2636 }
2637
2638 object_property_set_int(core, nr_threads, "nr-threads",
2639 &error_fatal);
2640 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2641 &error_fatal);
2642 object_property_set_bool(core, true, "realized", &error_fatal);
2643
2644 object_unref(core);
2645 }
2646 }
2647 }
2648
spapr_create_default_phb(void)2649 static PCIHostState *spapr_create_default_phb(void)
2650 {
2651 DeviceState *dev;
2652
2653 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
2654 qdev_prop_set_uint32(dev, "index", 0);
2655 qdev_init_nofail(dev);
2656
2657 return PCI_HOST_BRIDGE(dev);
2658 }
2659
2660 /* pSeries LPAR / sPAPR hardware init */
spapr_machine_init(MachineState * machine)2661 static void spapr_machine_init(MachineState *machine)
2662 {
2663 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
2664 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2665 const char *kernel_filename = machine->kernel_filename;
2666 const char *initrd_filename = machine->initrd_filename;
2667 PCIHostState *phb;
2668 int i;
2669 MemoryRegion *sysmem = get_system_memory();
2670 MemoryRegion *ram = g_new(MemoryRegion, 1);
2671 hwaddr node0_size = spapr_node0_size(machine);
2672 long load_limit, fw_size;
2673 char *filename;
2674 Error *resize_hpt_err = NULL;
2675
2676 msi_nonbroken = true;
2677
2678 QLIST_INIT(&spapr->phbs);
2679 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2680
2681 /* Determine capabilities to run with */
2682 spapr_caps_init(spapr);
2683
2684 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2685 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2686 /*
2687 * If the user explicitly requested a mode we should either
2688 * supply it, or fail completely (which we do below). But if
2689 * it's not set explicitly, we reset our mode to something
2690 * that works
2691 */
2692 if (resize_hpt_err) {
2693 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2694 error_free(resize_hpt_err);
2695 resize_hpt_err = NULL;
2696 } else {
2697 spapr->resize_hpt = smc->resize_hpt_default;
2698 }
2699 }
2700
2701 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2702
2703 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2704 /*
2705 * User requested HPT resize, but this host can't supply it. Bail out
2706 */
2707 error_report_err(resize_hpt_err);
2708 exit(1);
2709 }
2710
2711 spapr->rma_size = node0_size;
2712
2713 /* With KVM, we don't actually know whether KVM supports an
2714 * unbounded RMA (PR KVM) or is limited by the hash table size
2715 * (HV KVM using VRMA), so we always assume the latter
2716 *
2717 * In that case, we also limit the initial allocations for RTAS
2718 * etc... to 256M since we have no way to know what the VRMA size
2719 * is going to be as it depends on the size of the hash table
2720 * which isn't determined yet.
2721 */
2722 if (kvm_enabled()) {
2723 spapr->vrma_adjust = 1;
2724 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2725 }
2726
2727 /* Actually we don't support unbounded RMA anymore since we added
2728 * proper emulation of HV mode. The max we can get is 16G which
2729 * also happens to be what we configure for PAPR mode so make sure
2730 * we don't do anything bigger than that
2731 */
2732 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2733
2734 if (spapr->rma_size > node0_size) {
2735 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2736 spapr->rma_size);
2737 exit(1);
2738 }
2739
2740 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2741 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2742
2743 /*
2744 * VSMT must be set in order to be able to compute VCPU ids, ie to
2745 * call spapr_max_server_number() or spapr_vcpu_id().
2746 */
2747 spapr_set_vsmt_mode(spapr, &error_fatal);
2748
2749 /* Set up Interrupt Controller before we create the VCPUs */
2750 spapr_irq_init(spapr, &error_fatal);
2751
2752 /* Set up containers for ibm,client-architecture-support negotiated options
2753 */
2754 spapr->ov5 = spapr_ovec_new();
2755 spapr->ov5_cas = spapr_ovec_new();
2756
2757 if (smc->dr_lmb_enabled) {
2758 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2759 spapr_validate_node_memory(machine, &error_fatal);
2760 }
2761
2762 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2763
2764 /* advertise support for dedicated HP event source to guests */
2765 if (spapr->use_hotplug_event_source) {
2766 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2767 }
2768
2769 /* advertise support for HPT resizing */
2770 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2771 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2772 }
2773
2774 /* advertise support for ibm,dyamic-memory-v2 */
2775 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2776
2777 /* advertise XIVE on POWER9 machines */
2778 if (spapr->irq->xive) {
2779 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
2780 }
2781
2782 /* init CPUs */
2783 spapr_init_cpus(spapr);
2784
2785 /*
2786 * check we don't have a memory-less/cpu-less NUMA node
2787 * Firmware relies on the existing memory/cpu topology to provide the
2788 * NUMA topology to the kernel.
2789 * And the linux kernel needs to know the NUMA topology at start
2790 * to be able to hotplug CPUs later.
2791 */
2792 if (machine->numa_state->num_nodes) {
2793 for (i = 0; i < machine->numa_state->num_nodes; ++i) {
2794 /* check for memory-less node */
2795 if (machine->numa_state->nodes[i].node_mem == 0) {
2796 CPUState *cs;
2797 int found = 0;
2798 /* check for cpu-less node */
2799 CPU_FOREACH(cs) {
2800 PowerPCCPU *cpu = POWERPC_CPU(cs);
2801 if (cpu->node_id == i) {
2802 found = 1;
2803 break;
2804 }
2805 }
2806 /* memory-less and cpu-less node */
2807 if (!found) {
2808 error_report(
2809 "Memory-less/cpu-less nodes are not supported (node %d)",
2810 i);
2811 exit(1);
2812 }
2813 }
2814 }
2815
2816 }
2817
2818 /*
2819 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
2820 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
2821 * called from vPHB reset handler so we initialize the counter here.
2822 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
2823 * must be equally distant from any other node.
2824 * The final value of spapr->gpu_numa_id is going to be written to
2825 * max-associativity-domains in spapr_build_fdt().
2826 */
2827 spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes);
2828
2829 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2830 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2831 spapr->max_compat_pvr)) {
2832 /* KVM and TCG always allow GTSE with radix... */
2833 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2834 }
2835 /* ... but not with hash (currently). */
2836
2837 if (kvm_enabled()) {
2838 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2839 kvmppc_enable_logical_ci_hcalls();
2840 kvmppc_enable_set_mode_hcall();
2841
2842 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2843 kvmppc_enable_clear_ref_mod_hcalls();
2844
2845 /* Enable H_PAGE_INIT */
2846 kvmppc_enable_h_page_init();
2847 }
2848
2849 /* allocate RAM */
2850 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2851 machine->ram_size);
2852 memory_region_add_subregion(sysmem, 0, ram);
2853
2854 /* always allocate the device memory information */
2855 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2856
2857 /* initialize hotplug memory address space */
2858 if (machine->ram_size < machine->maxram_size) {
2859 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2860 /*
2861 * Limit the number of hotpluggable memory slots to half the number
2862 * slots that KVM supports, leaving the other half for PCI and other
2863 * devices. However ensure that number of slots doesn't drop below 32.
2864 */
2865 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2866 SPAPR_MAX_RAM_SLOTS;
2867
2868 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2869 max_memslots = SPAPR_MAX_RAM_SLOTS;
2870 }
2871 if (machine->ram_slots > max_memslots) {
2872 error_report("Specified number of memory slots %"
2873 PRIu64" exceeds max supported %d",
2874 machine->ram_slots, max_memslots);
2875 exit(1);
2876 }
2877
2878 machine->device_memory->base = ROUND_UP(machine->ram_size,
2879 SPAPR_DEVICE_MEM_ALIGN);
2880 memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2881 "device-memory", device_mem_size);
2882 memory_region_add_subregion(sysmem, machine->device_memory->base,
2883 &machine->device_memory->mr);
2884 }
2885
2886 if (smc->dr_lmb_enabled) {
2887 spapr_create_lmb_dr_connectors(spapr);
2888 }
2889
2890 /* Set up RTAS event infrastructure */
2891 spapr_events_init(spapr);
2892
2893 /* Set up the RTC RTAS interfaces */
2894 spapr_rtc_create(spapr);
2895
2896 /* Set up VIO bus */
2897 spapr->vio_bus = spapr_vio_bus_init();
2898
2899 for (i = 0; i < serial_max_hds(); i++) {
2900 if (serial_hd(i)) {
2901 spapr_vty_create(spapr->vio_bus, serial_hd(i));
2902 }
2903 }
2904
2905 /* We always have at least the nvram device on VIO */
2906 spapr_create_nvram(spapr);
2907
2908 /*
2909 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2910 * connectors (described in root DT node's "ibm,drc-types" property)
2911 * are pre-initialized here. additional child connectors (such as
2912 * connectors for a PHBs PCI slots) are added as needed during their
2913 * parent's realization.
2914 */
2915 if (smc->dr_phb_enabled) {
2916 for (i = 0; i < SPAPR_MAX_PHBS; i++) {
2917 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i);
2918 }
2919 }
2920
2921 /* Set up PCI */
2922 spapr_pci_rtas_init();
2923
2924 phb = spapr_create_default_phb();
2925
2926 for (i = 0; i < nb_nics; i++) {
2927 NICInfo *nd = &nd_table[i];
2928
2929 if (!nd->model) {
2930 nd->model = g_strdup("spapr-vlan");
2931 }
2932
2933 if (g_str_equal(nd->model, "spapr-vlan") ||
2934 g_str_equal(nd->model, "ibmveth")) {
2935 spapr_vlan_create(spapr->vio_bus, nd);
2936 } else {
2937 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2938 }
2939 }
2940
2941 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2942 spapr_vscsi_create(spapr->vio_bus);
2943 }
2944
2945 /* Graphics */
2946 if (spapr_vga_init(phb->bus, &error_fatal)) {
2947 spapr->has_graphics = true;
2948 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2949 }
2950
2951 if (machine->usb) {
2952 if (smc->use_ohci_by_default) {
2953 pci_create_simple(phb->bus, -1, "pci-ohci");
2954 } else {
2955 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2956 }
2957
2958 if (spapr->has_graphics) {
2959 USBBus *usb_bus = usb_bus_find(-1);
2960
2961 usb_create_simple(usb_bus, "usb-kbd");
2962 usb_create_simple(usb_bus, "usb-mouse");
2963 }
2964 }
2965
2966 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) {
2967 error_report(
2968 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2969 MIN_RMA_SLOF);
2970 exit(1);
2971 }
2972
2973 if (kernel_filename) {
2974 uint64_t lowaddr = 0;
2975
2976 spapr->kernel_size = load_elf(kernel_filename, NULL,
2977 translate_kernel_address, NULL,
2978 NULL, &lowaddr, NULL, 1,
2979 PPC_ELF_MACHINE, 0, 0);
2980 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2981 spapr->kernel_size = load_elf(kernel_filename, NULL,
2982 translate_kernel_address, NULL, NULL,
2983 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2984 0, 0);
2985 spapr->kernel_le = spapr->kernel_size > 0;
2986 }
2987 if (spapr->kernel_size < 0) {
2988 error_report("error loading %s: %s", kernel_filename,
2989 load_elf_strerror(spapr->kernel_size));
2990 exit(1);
2991 }
2992
2993 /* load initrd */
2994 if (initrd_filename) {
2995 /* Try to locate the initrd in the gap between the kernel
2996 * and the firmware. Add a bit of space just in case
2997 */
2998 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2999 + 0x1ffff) & ~0xffff;
3000 spapr->initrd_size = load_image_targphys(initrd_filename,
3001 spapr->initrd_base,
3002 load_limit
3003 - spapr->initrd_base);
3004 if (spapr->initrd_size < 0) {
3005 error_report("could not load initial ram disk '%s'",
3006 initrd_filename);
3007 exit(1);
3008 }
3009 }
3010 }
3011
3012 if (bios_name == NULL) {
3013 bios_name = FW_FILE_NAME;
3014 }
3015 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
3016 if (!filename) {
3017 error_report("Could not find LPAR firmware '%s'", bios_name);
3018 exit(1);
3019 }
3020 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
3021 if (fw_size <= 0) {
3022 error_report("Could not load LPAR firmware '%s'", filename);
3023 exit(1);
3024 }
3025 g_free(filename);
3026
3027 /* FIXME: Should register things through the MachineState's qdev
3028 * interface, this is a legacy from the sPAPREnvironment structure
3029 * which predated MachineState but had a similar function */
3030 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
3031 register_savevm_live("spapr/htab", -1, 1,
3032 &savevm_htab_handlers, spapr);
3033
3034 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine),
3035 &error_fatal);
3036
3037 qemu_register_boot_set(spapr_boot_set, spapr);
3038
3039 /*
3040 * Nothing needs to be done to resume a suspended guest because
3041 * suspending does not change the machine state, so no need for
3042 * a ->wakeup method.
3043 */
3044 qemu_register_wakeup_support();
3045
3046 if (kvm_enabled()) {
3047 /* to stop and start vmclock */
3048 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
3049 &spapr->tb);
3050
3051 kvmppc_spapr_enable_inkernel_multitce();
3052 }
3053 }
3054
spapr_kvm_type(MachineState * machine,const char * vm_type)3055 static int spapr_kvm_type(MachineState *machine, const char *vm_type)
3056 {
3057 if (!vm_type) {
3058 return 0;
3059 }
3060
3061 if (!strcmp(vm_type, "HV")) {
3062 return 1;
3063 }
3064
3065 if (!strcmp(vm_type, "PR")) {
3066 return 2;
3067 }
3068
3069 error_report("Unknown kvm-type specified '%s'", vm_type);
3070 exit(1);
3071 }
3072
3073 /*
3074 * Implementation of an interface to adjust firmware path
3075 * for the bootindex property handling.
3076 */
spapr_get_fw_dev_path(FWPathProvider * p,BusState * bus,DeviceState * dev)3077 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
3078 DeviceState *dev)
3079 {
3080 #define CAST(type, obj, name) \
3081 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3082 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
3083 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
3084 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
3085
3086 if (d) {
3087 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
3088 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
3089 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
3090
3091 if (spapr) {
3092 /*
3093 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3094 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3095 * 0x8000 | (target << 8) | (bus << 5) | lun
3096 * (see the "Logical unit addressing format" table in SAM5)
3097 */
3098 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun;
3099 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3100 (uint64_t)id << 48);
3101 } else if (virtio) {
3102 /*
3103 * We use SRP luns of the form 01000000 | (target << 8) | lun
3104 * in the top 32 bits of the 64-bit LUN
3105 * Note: the quote above is from SLOF and it is wrong,
3106 * the actual binding is:
3107 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3108 */
3109 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
3110 if (d->lun >= 256) {
3111 /* Use the LUN "flat space addressing method" */
3112 id |= 0x4000;
3113 }
3114 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3115 (uint64_t)id << 32);
3116 } else if (usb) {
3117 /*
3118 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3119 * in the top 32 bits of the 64-bit LUN
3120 */
3121 unsigned usb_port = atoi(usb->port->path);
3122 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
3123 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3124 (uint64_t)id << 32);
3125 }
3126 }
3127
3128 /*
3129 * SLOF probes the USB devices, and if it recognizes that the device is a
3130 * storage device, it changes its name to "storage" instead of "usb-host",
3131 * and additionally adds a child node for the SCSI LUN, so the correct
3132 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3133 */
3134 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
3135 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
3136 if (usb_host_dev_is_scsi_storage(usbdev)) {
3137 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
3138 }
3139 }
3140
3141 if (phb) {
3142 /* Replace "pci" with "pci@800000020000000" */
3143 return g_strdup_printf("pci@%"PRIX64, phb->buid);
3144 }
3145
3146 if (vsc) {
3147 /* Same logic as virtio above */
3148 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
3149 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
3150 }
3151
3152 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
3153 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3154 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
3155 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
3156 }
3157
3158 return NULL;
3159 }
3160
spapr_get_kvm_type(Object * obj,Error ** errp)3161 static char *spapr_get_kvm_type(Object *obj, Error **errp)
3162 {
3163 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3164
3165 return g_strdup(spapr->kvm_type);
3166 }
3167
spapr_set_kvm_type(Object * obj,const char * value,Error ** errp)3168 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
3169 {
3170 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3171
3172 g_free(spapr->kvm_type);
3173 spapr->kvm_type = g_strdup(value);
3174 }
3175
spapr_get_modern_hotplug_events(Object * obj,Error ** errp)3176 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
3177 {
3178 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3179
3180 return spapr->use_hotplug_event_source;
3181 }
3182
spapr_set_modern_hotplug_events(Object * obj,bool value,Error ** errp)3183 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
3184 Error **errp)
3185 {
3186 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3187
3188 spapr->use_hotplug_event_source = value;
3189 }
3190
spapr_get_msix_emulation(Object * obj,Error ** errp)3191 static bool spapr_get_msix_emulation(Object *obj, Error **errp)
3192 {
3193 return true;
3194 }
3195
spapr_get_resize_hpt(Object * obj,Error ** errp)3196 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
3197 {
3198 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3199
3200 switch (spapr->resize_hpt) {
3201 case SPAPR_RESIZE_HPT_DEFAULT:
3202 return g_strdup("default");
3203 case SPAPR_RESIZE_HPT_DISABLED:
3204 return g_strdup("disabled");
3205 case SPAPR_RESIZE_HPT_ENABLED:
3206 return g_strdup("enabled");
3207 case SPAPR_RESIZE_HPT_REQUIRED:
3208 return g_strdup("required");
3209 }
3210 g_assert_not_reached();
3211 }
3212
spapr_set_resize_hpt(Object * obj,const char * value,Error ** errp)3213 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3214 {
3215 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3216
3217 if (strcmp(value, "default") == 0) {
3218 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3219 } else if (strcmp(value, "disabled") == 0) {
3220 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3221 } else if (strcmp(value, "enabled") == 0) {
3222 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3223 } else if (strcmp(value, "required") == 0) {
3224 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3225 } else {
3226 error_setg(errp, "Bad value for \"resize-hpt\" property");
3227 }
3228 }
3229
spapr_get_vsmt(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)3230 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
3231 void *opaque, Error **errp)
3232 {
3233 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3234 }
3235
spapr_set_vsmt(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)3236 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
3237 void *opaque, Error **errp)
3238 {
3239 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3240 }
3241
spapr_get_ic_mode(Object * obj,Error ** errp)3242 static char *spapr_get_ic_mode(Object *obj, Error **errp)
3243 {
3244 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3245
3246 if (spapr->irq == &spapr_irq_xics_legacy) {
3247 return g_strdup("legacy");
3248 } else if (spapr->irq == &spapr_irq_xics) {
3249 return g_strdup("xics");
3250 } else if (spapr->irq == &spapr_irq_xive) {
3251 return g_strdup("xive");
3252 } else if (spapr->irq == &spapr_irq_dual) {
3253 return g_strdup("dual");
3254 }
3255 g_assert_not_reached();
3256 }
3257
spapr_set_ic_mode(Object * obj,const char * value,Error ** errp)3258 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp)
3259 {
3260 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3261
3262 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
3263 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3264 return;
3265 }
3266
3267 /* The legacy IRQ backend can not be set */
3268 if (strcmp(value, "xics") == 0) {
3269 spapr->irq = &spapr_irq_xics;
3270 } else if (strcmp(value, "xive") == 0) {
3271 spapr->irq = &spapr_irq_xive;
3272 } else if (strcmp(value, "dual") == 0) {
3273 spapr->irq = &spapr_irq_dual;
3274 } else {
3275 error_setg(errp, "Bad value for \"ic-mode\" property");
3276 }
3277 }
3278
spapr_get_host_model(Object * obj,Error ** errp)3279 static char *spapr_get_host_model(Object *obj, Error **errp)
3280 {
3281 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3282
3283 return g_strdup(spapr->host_model);
3284 }
3285
spapr_set_host_model(Object * obj,const char * value,Error ** errp)3286 static void spapr_set_host_model(Object *obj, const char *value, Error **errp)
3287 {
3288 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3289
3290 g_free(spapr->host_model);
3291 spapr->host_model = g_strdup(value);
3292 }
3293
spapr_get_host_serial(Object * obj,Error ** errp)3294 static char *spapr_get_host_serial(Object *obj, Error **errp)
3295 {
3296 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3297
3298 return g_strdup(spapr->host_serial);
3299 }
3300
spapr_set_host_serial(Object * obj,const char * value,Error ** errp)3301 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp)
3302 {
3303 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3304
3305 g_free(spapr->host_serial);
3306 spapr->host_serial = g_strdup(value);
3307 }
3308
spapr_instance_init(Object * obj)3309 static void spapr_instance_init(Object *obj)
3310 {
3311 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3312 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3313
3314 spapr->htab_fd = -1;
3315 spapr->use_hotplug_event_source = true;
3316 object_property_add_str(obj, "kvm-type",
3317 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
3318 object_property_set_description(obj, "kvm-type",
3319 "Specifies the KVM virtualization mode (HV, PR)",
3320 NULL);
3321 object_property_add_bool(obj, "modern-hotplug-events",
3322 spapr_get_modern_hotplug_events,
3323 spapr_set_modern_hotplug_events,
3324 NULL);
3325 object_property_set_description(obj, "modern-hotplug-events",
3326 "Use dedicated hotplug event mechanism in"
3327 " place of standard EPOW events when possible"
3328 " (required for memory hot-unplug support)",
3329 NULL);
3330 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
3331 "Maximum permitted CPU compatibility mode",
3332 &error_fatal);
3333
3334 object_property_add_str(obj, "resize-hpt",
3335 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
3336 object_property_set_description(obj, "resize-hpt",
3337 "Resizing of the Hash Page Table (enabled, disabled, required)",
3338 NULL);
3339 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
3340 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
3341 object_property_set_description(obj, "vsmt",
3342 "Virtual SMT: KVM behaves as if this were"
3343 " the host's SMT mode", &error_abort);
3344 object_property_add_bool(obj, "vfio-no-msix-emulation",
3345 spapr_get_msix_emulation, NULL, NULL);
3346
3347 /* The machine class defines the default interrupt controller mode */
3348 spapr->irq = smc->irq;
3349 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode,
3350 spapr_set_ic_mode, NULL);
3351 object_property_set_description(obj, "ic-mode",
3352 "Specifies the interrupt controller mode (xics, xive, dual)",
3353 NULL);
3354
3355 object_property_add_str(obj, "host-model",
3356 spapr_get_host_model, spapr_set_host_model,
3357 &error_abort);
3358 object_property_set_description(obj, "host-model",
3359 "Host model to advertise in guest device tree", &error_abort);
3360 object_property_add_str(obj, "host-serial",
3361 spapr_get_host_serial, spapr_set_host_serial,
3362 &error_abort);
3363 object_property_set_description(obj, "host-serial",
3364 "Host serial number to advertise in guest device tree", &error_abort);
3365 }
3366
spapr_machine_finalizefn(Object * obj)3367 static void spapr_machine_finalizefn(Object *obj)
3368 {
3369 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3370
3371 g_free(spapr->kvm_type);
3372 }
3373
spapr_do_system_reset_on_cpu(CPUState * cs,run_on_cpu_data arg)3374 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
3375 {
3376 cpu_synchronize_state(cs);
3377 ppc_cpu_do_system_reset(cs);
3378 }
3379
spapr_nmi(NMIState * n,int cpu_index,Error ** errp)3380 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
3381 {
3382 CPUState *cs;
3383
3384 CPU_FOREACH(cs) {
3385 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
3386 }
3387 }
3388
spapr_lmb_dt_populate(SpaprDrc * drc,SpaprMachineState * spapr,void * fdt,int * fdt_start_offset,Error ** errp)3389 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3390 void *fdt, int *fdt_start_offset, Error **errp)
3391 {
3392 uint64_t addr;
3393 uint32_t node;
3394
3395 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE;
3396 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP,
3397 &error_abort);
3398 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr,
3399 SPAPR_MEMORY_BLOCK_SIZE);
3400 return 0;
3401 }
3402
spapr_add_lmbs(DeviceState * dev,uint64_t addr_start,uint64_t size,bool dedicated_hp_event_source,Error ** errp)3403 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
3404 bool dedicated_hp_event_source, Error **errp)
3405 {
3406 SpaprDrc *drc;
3407 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
3408 int i;
3409 uint64_t addr = addr_start;
3410 bool hotplugged = spapr_drc_hotplugged(dev);
3411 Error *local_err = NULL;
3412
3413 for (i = 0; i < nr_lmbs; i++) {
3414 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3415 addr / SPAPR_MEMORY_BLOCK_SIZE);
3416 g_assert(drc);
3417
3418 spapr_drc_attach(drc, dev, &local_err);
3419 if (local_err) {
3420 while (addr > addr_start) {
3421 addr -= SPAPR_MEMORY_BLOCK_SIZE;
3422 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3423 addr / SPAPR_MEMORY_BLOCK_SIZE);
3424 spapr_drc_detach(drc);
3425 }
3426 error_propagate(errp, local_err);
3427 return;
3428 }
3429 if (!hotplugged) {
3430 spapr_drc_reset(drc);
3431 }
3432 addr += SPAPR_MEMORY_BLOCK_SIZE;
3433 }
3434 /* send hotplug notification to the
3435 * guest only in case of hotplugged memory
3436 */
3437 if (hotplugged) {
3438 if (dedicated_hp_event_source) {
3439 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3440 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3441 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3442 nr_lmbs,
3443 spapr_drc_index(drc));
3444 } else {
3445 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3446 nr_lmbs);
3447 }
3448 }
3449 }
3450
spapr_memory_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3451 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3452 Error **errp)
3453 {
3454 Error *local_err = NULL;
3455 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3456 PCDIMMDevice *dimm = PC_DIMM(dev);
3457 uint64_t size, addr;
3458
3459 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort);
3460
3461 pc_dimm_plug(dimm, MACHINE(ms), &local_err);
3462 if (local_err) {
3463 goto out;
3464 }
3465
3466 addr = object_property_get_uint(OBJECT(dimm),
3467 PC_DIMM_ADDR_PROP, &local_err);
3468 if (local_err) {
3469 goto out_unplug;
3470 }
3471
3472 spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
3473 &local_err);
3474 if (local_err) {
3475 goto out_unplug;
3476 }
3477
3478 return;
3479
3480 out_unplug:
3481 pc_dimm_unplug(dimm, MACHINE(ms));
3482 out:
3483 error_propagate(errp, local_err);
3484 }
3485
spapr_memory_pre_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3486 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3487 Error **errp)
3488 {
3489 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev);
3490 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3491 PCDIMMDevice *dimm = PC_DIMM(dev);
3492 Error *local_err = NULL;
3493 uint64_t size;
3494 Object *memdev;
3495 hwaddr pagesize;
3496
3497 if (!smc->dr_lmb_enabled) {
3498 error_setg(errp, "Memory hotplug not supported for this machine");
3499 return;
3500 }
3501
3502 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err);
3503 if (local_err) {
3504 error_propagate(errp, local_err);
3505 return;
3506 }
3507
3508 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3509 error_setg(errp, "Hotplugged memory size must be a multiple of "
3510 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
3511 return;
3512 }
3513
3514 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP,
3515 &error_abort);
3516 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev));
3517 spapr_check_pagesize(spapr, pagesize, &local_err);
3518 if (local_err) {
3519 error_propagate(errp, local_err);
3520 return;
3521 }
3522
3523 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp);
3524 }
3525
3526 struct SpaprDimmState {
3527 PCDIMMDevice *dimm;
3528 uint32_t nr_lmbs;
3529 QTAILQ_ENTRY(SpaprDimmState) next;
3530 };
3531
spapr_pending_dimm_unplugs_find(SpaprMachineState * s,PCDIMMDevice * dimm)3532 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s,
3533 PCDIMMDevice *dimm)
3534 {
3535 SpaprDimmState *dimm_state = NULL;
3536
3537 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3538 if (dimm_state->dimm == dimm) {
3539 break;
3540 }
3541 }
3542 return dimm_state;
3543 }
3544
spapr_pending_dimm_unplugs_add(SpaprMachineState * spapr,uint32_t nr_lmbs,PCDIMMDevice * dimm)3545 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr,
3546 uint32_t nr_lmbs,
3547 PCDIMMDevice *dimm)
3548 {
3549 SpaprDimmState *ds = NULL;
3550
3551 /*
3552 * If this request is for a DIMM whose removal had failed earlier
3553 * (due to guest's refusal to remove the LMBs), we would have this
3554 * dimm already in the pending_dimm_unplugs list. In that
3555 * case don't add again.
3556 */
3557 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3558 if (!ds) {
3559 ds = g_malloc0(sizeof(SpaprDimmState));
3560 ds->nr_lmbs = nr_lmbs;
3561 ds->dimm = dimm;
3562 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3563 }
3564 return ds;
3565 }
3566
spapr_pending_dimm_unplugs_remove(SpaprMachineState * spapr,SpaprDimmState * dimm_state)3567 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr,
3568 SpaprDimmState *dimm_state)
3569 {
3570 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3571 g_free(dimm_state);
3572 }
3573
spapr_recover_pending_dimm_state(SpaprMachineState * ms,PCDIMMDevice * dimm)3574 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms,
3575 PCDIMMDevice *dimm)
3576 {
3577 SpaprDrc *drc;
3578 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm),
3579 &error_abort);
3580 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3581 uint32_t avail_lmbs = 0;
3582 uint64_t addr_start, addr;
3583 int i;
3584
3585 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3586 &error_abort);
3587
3588 addr = addr_start;
3589 for (i = 0; i < nr_lmbs; i++) {
3590 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3591 addr / SPAPR_MEMORY_BLOCK_SIZE);
3592 g_assert(drc);
3593 if (drc->dev) {
3594 avail_lmbs++;
3595 }
3596 addr += SPAPR_MEMORY_BLOCK_SIZE;
3597 }
3598
3599 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3600 }
3601
3602 /* Callback to be called during DRC release. */
spapr_lmb_release(DeviceState * dev)3603 void spapr_lmb_release(DeviceState *dev)
3604 {
3605 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3606 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl);
3607 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3608
3609 /* This information will get lost if a migration occurs
3610 * during the unplug process. In this case recover it. */
3611 if (ds == NULL) {
3612 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3613 g_assert(ds);
3614 /* The DRC being examined by the caller at least must be counted */
3615 g_assert(ds->nr_lmbs);
3616 }
3617
3618 if (--ds->nr_lmbs) {
3619 return;
3620 }
3621
3622 /*
3623 * Now that all the LMBs have been removed by the guest, call the
3624 * unplug handler chain. This can never fail.
3625 */
3626 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3627 object_unparent(OBJECT(dev));
3628 }
3629
spapr_memory_unplug(HotplugHandler * hotplug_dev,DeviceState * dev)3630 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3631 {
3632 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3633 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3634
3635 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev));
3636 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3637 spapr_pending_dimm_unplugs_remove(spapr, ds);
3638 }
3639
spapr_memory_unplug_request(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3640 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3641 DeviceState *dev, Error **errp)
3642 {
3643 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3644 Error *local_err = NULL;
3645 PCDIMMDevice *dimm = PC_DIMM(dev);
3646 uint32_t nr_lmbs;
3647 uint64_t size, addr_start, addr;
3648 int i;
3649 SpaprDrc *drc;
3650
3651 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort);
3652 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3653
3654 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3655 &local_err);
3656 if (local_err) {
3657 goto out;
3658 }
3659
3660 /*
3661 * An existing pending dimm state for this DIMM means that there is an
3662 * unplug operation in progress, waiting for the spapr_lmb_release
3663 * callback to complete the job (BQL can't cover that far). In this case,
3664 * bail out to avoid detaching DRCs that were already released.
3665 */
3666 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3667 error_setg(&local_err,
3668 "Memory unplug already in progress for device %s",
3669 dev->id);
3670 goto out;
3671 }
3672
3673 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3674
3675 addr = addr_start;
3676 for (i = 0; i < nr_lmbs; i++) {
3677 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3678 addr / SPAPR_MEMORY_BLOCK_SIZE);
3679 g_assert(drc);
3680
3681 spapr_drc_detach(drc);
3682 addr += SPAPR_MEMORY_BLOCK_SIZE;
3683 }
3684
3685 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3686 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3687 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3688 nr_lmbs, spapr_drc_index(drc));
3689 out:
3690 error_propagate(errp, local_err);
3691 }
3692
3693 /* Callback to be called during DRC release. */
spapr_core_release(DeviceState * dev)3694 void spapr_core_release(DeviceState *dev)
3695 {
3696 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3697
3698 /* Call the unplug handler chain. This can never fail. */
3699 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3700 object_unparent(OBJECT(dev));
3701 }
3702
spapr_core_unplug(HotplugHandler * hotplug_dev,DeviceState * dev)3703 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3704 {
3705 MachineState *ms = MACHINE(hotplug_dev);
3706 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3707 CPUCore *cc = CPU_CORE(dev);
3708 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3709
3710 if (smc->pre_2_10_has_unused_icps) {
3711 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3712 int i;
3713
3714 for (i = 0; i < cc->nr_threads; i++) {
3715 CPUState *cs = CPU(sc->threads[i]);
3716
3717 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3718 }
3719 }
3720
3721 assert(core_slot);
3722 core_slot->cpu = NULL;
3723 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3724 }
3725
3726 static
spapr_core_unplug_request(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3727 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3728 Error **errp)
3729 {
3730 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3731 int index;
3732 SpaprDrc *drc;
3733 CPUCore *cc = CPU_CORE(dev);
3734
3735 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3736 error_setg(errp, "Unable to find CPU core with core-id: %d",
3737 cc->core_id);
3738 return;
3739 }
3740 if (index == 0) {
3741 error_setg(errp, "Boot CPU core may not be unplugged");
3742 return;
3743 }
3744
3745 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3746 spapr_vcpu_id(spapr, cc->core_id));
3747 g_assert(drc);
3748
3749 if (!spapr_drc_unplug_requested(drc)) {
3750 spapr_drc_detach(drc);
3751 spapr_hotplug_req_remove_by_index(drc);
3752 }
3753 }
3754
spapr_core_dt_populate(SpaprDrc * drc,SpaprMachineState * spapr,void * fdt,int * fdt_start_offset,Error ** errp)3755 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3756 void *fdt, int *fdt_start_offset, Error **errp)
3757 {
3758 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev);
3759 CPUState *cs = CPU(core->threads[0]);
3760 PowerPCCPU *cpu = POWERPC_CPU(cs);
3761 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3762 int id = spapr_get_vcpu_id(cpu);
3763 char *nodename;
3764 int offset;
3765
3766 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3767 offset = fdt_add_subnode(fdt, 0, nodename);
3768 g_free(nodename);
3769
3770 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3771
3772 *fdt_start_offset = offset;
3773 return 0;
3774 }
3775
spapr_core_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3776 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3777 Error **errp)
3778 {
3779 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3780 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3781 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3782 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3783 CPUCore *cc = CPU_CORE(dev);
3784 CPUState *cs;
3785 SpaprDrc *drc;
3786 Error *local_err = NULL;
3787 CPUArchId *core_slot;
3788 int index;
3789 bool hotplugged = spapr_drc_hotplugged(dev);
3790 int i;
3791
3792 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3793 if (!core_slot) {
3794 error_setg(errp, "Unable to find CPU core with core-id: %d",
3795 cc->core_id);
3796 return;
3797 }
3798 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3799 spapr_vcpu_id(spapr, cc->core_id));
3800
3801 g_assert(drc || !mc->has_hotpluggable_cpus);
3802
3803 if (drc) {
3804 spapr_drc_attach(drc, dev, &local_err);
3805 if (local_err) {
3806 error_propagate(errp, local_err);
3807 return;
3808 }
3809
3810 if (hotplugged) {
3811 /*
3812 * Send hotplug notification interrupt to the guest only
3813 * in case of hotplugged CPUs.
3814 */
3815 spapr_hotplug_req_add_by_index(drc);
3816 } else {
3817 spapr_drc_reset(drc);
3818 }
3819 }
3820
3821 core_slot->cpu = OBJECT(dev);
3822
3823 if (smc->pre_2_10_has_unused_icps) {
3824 for (i = 0; i < cc->nr_threads; i++) {
3825 cs = CPU(core->threads[i]);
3826 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3827 }
3828 }
3829
3830 /*
3831 * Set compatibility mode to match the boot CPU, which was either set
3832 * by the machine reset code or by CAS.
3833 */
3834 if (hotplugged) {
3835 for (i = 0; i < cc->nr_threads; i++) {
3836 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr,
3837 &local_err);
3838 if (local_err) {
3839 error_propagate(errp, local_err);
3840 return;
3841 }
3842 }
3843 }
3844 }
3845
spapr_core_pre_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3846 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3847 Error **errp)
3848 {
3849 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3850 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3851 Error *local_err = NULL;
3852 CPUCore *cc = CPU_CORE(dev);
3853 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3854 const char *type = object_get_typename(OBJECT(dev));
3855 CPUArchId *core_slot;
3856 int index;
3857 unsigned int smp_threads = machine->smp.threads;
3858
3859 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3860 error_setg(&local_err, "CPU hotplug not supported for this machine");
3861 goto out;
3862 }
3863
3864 if (strcmp(base_core_type, type)) {
3865 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3866 goto out;
3867 }
3868
3869 if (cc->core_id % smp_threads) {
3870 error_setg(&local_err, "invalid core id %d", cc->core_id);
3871 goto out;
3872 }
3873
3874 /*
3875 * In general we should have homogeneous threads-per-core, but old
3876 * (pre hotplug support) machine types allow the last core to have
3877 * reduced threads as a compatibility hack for when we allowed
3878 * total vcpus not a multiple of threads-per-core.
3879 */
3880 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3881 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3882 cc->nr_threads, smp_threads);
3883 goto out;
3884 }
3885
3886 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3887 if (!core_slot) {
3888 error_setg(&local_err, "core id %d out of range", cc->core_id);
3889 goto out;
3890 }
3891
3892 if (core_slot->cpu) {
3893 error_setg(&local_err, "core %d already populated", cc->core_id);
3894 goto out;
3895 }
3896
3897 numa_cpu_pre_plug(core_slot, dev, &local_err);
3898
3899 out:
3900 error_propagate(errp, local_err);
3901 }
3902
spapr_phb_dt_populate(SpaprDrc * drc,SpaprMachineState * spapr,void * fdt,int * fdt_start_offset,Error ** errp)3903 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3904 void *fdt, int *fdt_start_offset, Error **errp)
3905 {
3906 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev);
3907 int intc_phandle;
3908
3909 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp);
3910 if (intc_phandle <= 0) {
3911 return -1;
3912 }
3913
3914 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) {
3915 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index);
3916 return -1;
3917 }
3918
3919 /* generally SLOF creates these, for hotplug it's up to QEMU */
3920 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci"));
3921
3922 return 0;
3923 }
3924
spapr_phb_pre_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3925 static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3926 Error **errp)
3927 {
3928 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3929 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3930 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3931 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
3932
3933 if (dev->hotplugged && !smc->dr_phb_enabled) {
3934 error_setg(errp, "PHB hotplug not supported for this machine");
3935 return;
3936 }
3937
3938 if (sphb->index == (uint32_t)-1) {
3939 error_setg(errp, "\"index\" for PAPR PHB is mandatory");
3940 return;
3941 }
3942
3943 /*
3944 * This will check that sphb->index doesn't exceed the maximum number of
3945 * PHBs for the current machine type.
3946 */
3947 smc->phb_placement(spapr, sphb->index,
3948 &sphb->buid, &sphb->io_win_addr,
3949 &sphb->mem_win_addr, &sphb->mem64_win_addr,
3950 windows_supported, sphb->dma_liobn,
3951 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr,
3952 errp);
3953 }
3954
spapr_phb_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3955 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3956 Error **errp)
3957 {
3958 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3959 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3960 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3961 SpaprDrc *drc;
3962 bool hotplugged = spapr_drc_hotplugged(dev);
3963 Error *local_err = NULL;
3964
3965 if (!smc->dr_phb_enabled) {
3966 return;
3967 }
3968
3969 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
3970 /* hotplug hooks should check it's enabled before getting this far */
3971 assert(drc);
3972
3973 spapr_drc_attach(drc, DEVICE(dev), &local_err);
3974 if (local_err) {
3975 error_propagate(errp, local_err);
3976 return;
3977 }
3978
3979 if (hotplugged) {
3980 spapr_hotplug_req_add_by_index(drc);
3981 } else {
3982 spapr_drc_reset(drc);
3983 }
3984 }
3985
spapr_phb_release(DeviceState * dev)3986 void spapr_phb_release(DeviceState *dev)
3987 {
3988 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3989
3990 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3991 object_unparent(OBJECT(dev));
3992 }
3993
spapr_phb_unplug(HotplugHandler * hotplug_dev,DeviceState * dev)3994 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3995 {
3996 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3997 }
3998
spapr_phb_unplug_request(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3999 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev,
4000 DeviceState *dev, Error **errp)
4001 {
4002 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
4003 SpaprDrc *drc;
4004
4005 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
4006 assert(drc);
4007
4008 if (!spapr_drc_unplug_requested(drc)) {
4009 spapr_drc_detach(drc);
4010 spapr_hotplug_req_remove_by_index(drc);
4011 }
4012 }
4013
spapr_tpm_proxy_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)4014 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
4015 Error **errp)
4016 {
4017 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
4018 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev);
4019
4020 if (spapr->tpm_proxy != NULL) {
4021 error_setg(errp, "Only one TPM proxy can be specified for this machine");
4022 return;
4023 }
4024
4025 spapr->tpm_proxy = tpm_proxy;
4026 }
4027
spapr_tpm_proxy_unplug(HotplugHandler * hotplug_dev,DeviceState * dev)4028 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
4029 {
4030 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
4031
4032 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
4033 object_unparent(OBJECT(dev));
4034 spapr->tpm_proxy = NULL;
4035 }
4036
spapr_machine_device_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)4037 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
4038 DeviceState *dev, Error **errp)
4039 {
4040 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4041 spapr_memory_plug(hotplug_dev, dev, errp);
4042 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4043 spapr_core_plug(hotplug_dev, dev, errp);
4044 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4045 spapr_phb_plug(hotplug_dev, dev, errp);
4046 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4047 spapr_tpm_proxy_plug(hotplug_dev, dev, errp);
4048 }
4049 }
4050
spapr_machine_device_unplug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)4051 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
4052 DeviceState *dev, Error **errp)
4053 {
4054 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4055 spapr_memory_unplug(hotplug_dev, dev);
4056 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4057 spapr_core_unplug(hotplug_dev, dev);
4058 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4059 spapr_phb_unplug(hotplug_dev, dev);
4060 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4061 spapr_tpm_proxy_unplug(hotplug_dev, dev);
4062 }
4063 }
4064
spapr_machine_device_unplug_request(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)4065 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
4066 DeviceState *dev, Error **errp)
4067 {
4068 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
4069 MachineClass *mc = MACHINE_GET_CLASS(sms);
4070 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4071
4072 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4073 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
4074 spapr_memory_unplug_request(hotplug_dev, dev, errp);
4075 } else {
4076 /* NOTE: this means there is a window after guest reset, prior to
4077 * CAS negotiation, where unplug requests will fail due to the
4078 * capability not being detected yet. This is a bit different than
4079 * the case with PCI unplug, where the events will be queued and
4080 * eventually handled by the guest after boot
4081 */
4082 error_setg(errp, "Memory hot unplug not supported for this guest");
4083 }
4084 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4085 if (!mc->has_hotpluggable_cpus) {
4086 error_setg(errp, "CPU hot unplug not supported on this machine");
4087 return;
4088 }
4089 spapr_core_unplug_request(hotplug_dev, dev, errp);
4090 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4091 if (!smc->dr_phb_enabled) {
4092 error_setg(errp, "PHB hot unplug not supported on this machine");
4093 return;
4094 }
4095 spapr_phb_unplug_request(hotplug_dev, dev, errp);
4096 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4097 spapr_tpm_proxy_unplug(hotplug_dev, dev);
4098 }
4099 }
4100
spapr_machine_device_pre_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)4101 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
4102 DeviceState *dev, Error **errp)
4103 {
4104 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4105 spapr_memory_pre_plug(hotplug_dev, dev, errp);
4106 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4107 spapr_core_pre_plug(hotplug_dev, dev, errp);
4108 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4109 spapr_phb_pre_plug(hotplug_dev, dev, errp);
4110 }
4111 }
4112
spapr_get_hotplug_handler(MachineState * machine,DeviceState * dev)4113 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
4114 DeviceState *dev)
4115 {
4116 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
4117 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) ||
4118 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) ||
4119 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) {
4120 return HOTPLUG_HANDLER(machine);
4121 }
4122 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
4123 PCIDevice *pcidev = PCI_DEVICE(dev);
4124 PCIBus *root = pci_device_root_bus(pcidev);
4125 SpaprPhbState *phb =
4126 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent),
4127 TYPE_SPAPR_PCI_HOST_BRIDGE);
4128
4129 if (phb) {
4130 return HOTPLUG_HANDLER(phb);
4131 }
4132 }
4133 return NULL;
4134 }
4135
4136 static CpuInstanceProperties
spapr_cpu_index_to_props(MachineState * machine,unsigned cpu_index)4137 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
4138 {
4139 CPUArchId *core_slot;
4140 MachineClass *mc = MACHINE_GET_CLASS(machine);
4141
4142 /* make sure possible_cpu are intialized */
4143 mc->possible_cpu_arch_ids(machine);
4144 /* get CPU core slot containing thread that matches cpu_index */
4145 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
4146 assert(core_slot);
4147 return core_slot->props;
4148 }
4149
spapr_get_default_cpu_node_id(const MachineState * ms,int idx)4150 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
4151 {
4152 return idx / ms->smp.cores % ms->numa_state->num_nodes;
4153 }
4154
spapr_possible_cpu_arch_ids(MachineState * machine)4155 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
4156 {
4157 int i;
4158 unsigned int smp_threads = machine->smp.threads;
4159 unsigned int smp_cpus = machine->smp.cpus;
4160 const char *core_type;
4161 int spapr_max_cores = machine->smp.max_cpus / smp_threads;
4162 MachineClass *mc = MACHINE_GET_CLASS(machine);
4163
4164 if (!mc->has_hotpluggable_cpus) {
4165 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
4166 }
4167 if (machine->possible_cpus) {
4168 assert(machine->possible_cpus->len == spapr_max_cores);
4169 return machine->possible_cpus;
4170 }
4171
4172 core_type = spapr_get_cpu_core_type(machine->cpu_type);
4173 if (!core_type) {
4174 error_report("Unable to find sPAPR CPU Core definition");
4175 exit(1);
4176 }
4177
4178 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
4179 sizeof(CPUArchId) * spapr_max_cores);
4180 machine->possible_cpus->len = spapr_max_cores;
4181 for (i = 0; i < machine->possible_cpus->len; i++) {
4182 int core_id = i * smp_threads;
4183
4184 machine->possible_cpus->cpus[i].type = core_type;
4185 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
4186 machine->possible_cpus->cpus[i].arch_id = core_id;
4187 machine->possible_cpus->cpus[i].props.has_core_id = true;
4188 machine->possible_cpus->cpus[i].props.core_id = core_id;
4189 }
4190 return machine->possible_cpus;
4191 }
4192
spapr_phb_placement(SpaprMachineState * spapr,uint32_t index,uint64_t * buid,hwaddr * pio,hwaddr * mmio32,hwaddr * mmio64,unsigned n_dma,uint32_t * liobns,hwaddr * nv2gpa,hwaddr * nv2atsd,Error ** errp)4193 static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index,
4194 uint64_t *buid, hwaddr *pio,
4195 hwaddr *mmio32, hwaddr *mmio64,
4196 unsigned n_dma, uint32_t *liobns,
4197 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4198 {
4199 /*
4200 * New-style PHB window placement.
4201 *
4202 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4203 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4204 * windows.
4205 *
4206 * Some guest kernels can't work with MMIO windows above 1<<46
4207 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4208 *
4209 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4210 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
4211 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
4212 * 1TiB 64-bit MMIO windows for each PHB.
4213 */
4214 const uint64_t base_buid = 0x800000020000000ULL;
4215 int i;
4216
4217 /* Sanity check natural alignments */
4218 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4219 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4220 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
4221 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
4222 /* Sanity check bounds */
4223 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
4224 SPAPR_PCI_MEM32_WIN_SIZE);
4225 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
4226 SPAPR_PCI_MEM64_WIN_SIZE);
4227
4228 if (index >= SPAPR_MAX_PHBS) {
4229 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
4230 SPAPR_MAX_PHBS - 1);
4231 return;
4232 }
4233
4234 *buid = base_buid + index;
4235 for (i = 0; i < n_dma; ++i) {
4236 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4237 }
4238
4239 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
4240 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
4241 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
4242
4243 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE;
4244 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE;
4245 }
4246
spapr_ics_get(XICSFabric * dev,int irq)4247 static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
4248 {
4249 SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4250
4251 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
4252 }
4253
spapr_ics_resend(XICSFabric * dev)4254 static void spapr_ics_resend(XICSFabric *dev)
4255 {
4256 SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4257
4258 ics_resend(spapr->ics);
4259 }
4260
spapr_icp_get(XICSFabric * xi,int vcpu_id)4261 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
4262 {
4263 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
4264
4265 return cpu ? spapr_cpu_state(cpu)->icp : NULL;
4266 }
4267
spapr_pic_print_info(InterruptStatsProvider * obj,Monitor * mon)4268 static void spapr_pic_print_info(InterruptStatsProvider *obj,
4269 Monitor *mon)
4270 {
4271 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
4272
4273 spapr_irq_print_info(spapr, mon);
4274 monitor_printf(mon, "irqchip: %s\n",
4275 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4276 }
4277
spapr_get_vcpu_id(PowerPCCPU * cpu)4278 int spapr_get_vcpu_id(PowerPCCPU *cpu)
4279 {
4280 return cpu->vcpu_id;
4281 }
4282
spapr_set_vcpu_id(PowerPCCPU * cpu,int cpu_index,Error ** errp)4283 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
4284 {
4285 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
4286 MachineState *ms = MACHINE(spapr);
4287 int vcpu_id;
4288
4289 vcpu_id = spapr_vcpu_id(spapr, cpu_index);
4290
4291 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) {
4292 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
4293 error_append_hint(errp, "Adjust the number of cpus to %d "
4294 "or try to raise the number of threads per core\n",
4295 vcpu_id * ms->smp.threads / spapr->vsmt);
4296 return;
4297 }
4298
4299 cpu->vcpu_id = vcpu_id;
4300 }
4301
spapr_find_cpu(int vcpu_id)4302 PowerPCCPU *spapr_find_cpu(int vcpu_id)
4303 {
4304 CPUState *cs;
4305
4306 CPU_FOREACH(cs) {
4307 PowerPCCPU *cpu = POWERPC_CPU(cs);
4308
4309 if (spapr_get_vcpu_id(cpu) == vcpu_id) {
4310 return cpu;
4311 }
4312 }
4313
4314 return NULL;
4315 }
4316
spapr_cpu_exec_enter(PPCVirtualHypervisor * vhyp,PowerPCCPU * cpu)4317 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
4318 {
4319 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
4320
4321 /* These are only called by TCG, KVM maintains dispatch state */
4322
4323 spapr_cpu->prod = false;
4324 if (spapr_cpu->vpa_addr) {
4325 CPUState *cs = CPU(cpu);
4326 uint32_t dispatch;
4327
4328 dispatch = ldl_be_phys(cs->as,
4329 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER);
4330 dispatch++;
4331 if ((dispatch & 1) != 0) {
4332 qemu_log_mask(LOG_GUEST_ERROR,
4333 "VPA: incorrect dispatch counter value for "
4334 "dispatched partition %u, correcting.\n", dispatch);
4335 dispatch++;
4336 }
4337 stl_be_phys(cs->as,
4338 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch);
4339 }
4340 }
4341
spapr_cpu_exec_exit(PPCVirtualHypervisor * vhyp,PowerPCCPU * cpu)4342 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
4343 {
4344 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
4345
4346 if (spapr_cpu->vpa_addr) {
4347 CPUState *cs = CPU(cpu);
4348 uint32_t dispatch;
4349
4350 dispatch = ldl_be_phys(cs->as,
4351 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER);
4352 dispatch++;
4353 if ((dispatch & 1) != 1) {
4354 qemu_log_mask(LOG_GUEST_ERROR,
4355 "VPA: incorrect dispatch counter value for "
4356 "preempted partition %u, correcting.\n", dispatch);
4357 dispatch++;
4358 }
4359 stl_be_phys(cs->as,
4360 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch);
4361 }
4362 }
4363
spapr_machine_class_init(ObjectClass * oc,void * data)4364 static void spapr_machine_class_init(ObjectClass *oc, void *data)
4365 {
4366 MachineClass *mc = MACHINE_CLASS(oc);
4367 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
4368 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
4369 NMIClass *nc = NMI_CLASS(oc);
4370 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
4371 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
4372 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
4373 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
4374
4375 mc->desc = "pSeries Logical Partition (PAPR compliant)";
4376 mc->ignore_boot_device_suffixes = true;
4377
4378 /*
4379 * We set up the default / latest behaviour here. The class_init
4380 * functions for the specific versioned machine types can override
4381 * these details for backwards compatibility
4382 */
4383 mc->init = spapr_machine_init;
4384 mc->reset = spapr_machine_reset;
4385 mc->block_default_type = IF_SCSI;
4386 mc->max_cpus = 1024;
4387 mc->no_parallel = 1;
4388 mc->default_boot_order = "";
4389 mc->default_ram_size = 512 * MiB;
4390 mc->default_display = "std";
4391 mc->kvm_type = spapr_kvm_type;
4392 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
4393 mc->pci_allow_0_address = true;
4394 assert(!mc->get_hotplug_handler);
4395 mc->get_hotplug_handler = spapr_get_hotplug_handler;
4396 hc->pre_plug = spapr_machine_device_pre_plug;
4397 hc->plug = spapr_machine_device_plug;
4398 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
4399 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
4400 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
4401 hc->unplug_request = spapr_machine_device_unplug_request;
4402 hc->unplug = spapr_machine_device_unplug;
4403
4404 smc->dr_lmb_enabled = true;
4405 smc->update_dt_enabled = true;
4406 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
4407 mc->has_hotpluggable_cpus = true;
4408 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
4409 fwc->get_dev_path = spapr_get_fw_dev_path;
4410 nc->nmi_monitor_handler = spapr_nmi;
4411 smc->phb_placement = spapr_phb_placement;
4412 vhc->hypercall = emulate_spapr_hypercall;
4413 vhc->hpt_mask = spapr_hpt_mask;
4414 vhc->map_hptes = spapr_map_hptes;
4415 vhc->unmap_hptes = spapr_unmap_hptes;
4416 vhc->hpte_set_c = spapr_hpte_set_c;
4417 vhc->hpte_set_r = spapr_hpte_set_r;
4418 vhc->get_pate = spapr_get_pate;
4419 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
4420 vhc->cpu_exec_enter = spapr_cpu_exec_enter;
4421 vhc->cpu_exec_exit = spapr_cpu_exec_exit;
4422 xic->ics_get = spapr_ics_get;
4423 xic->ics_resend = spapr_ics_resend;
4424 xic->icp_get = spapr_icp_get;
4425 ispc->print_info = spapr_pic_print_info;
4426 /* Force NUMA node memory size to be a multiple of
4427 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4428 * in which LMBs are represented and hot-added
4429 */
4430 mc->numa_mem_align_shift = 28;
4431 mc->numa_mem_supported = true;
4432 mc->auto_enable_numa = true;
4433
4434 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
4435 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
4436 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
4437 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4438 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4439 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND;
4440 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */
4441 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
4442 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON;
4443 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF;
4444 spapr_caps_add_properties(smc, &error_abort);
4445 smc->irq = &spapr_irq_dual;
4446 smc->dr_phb_enabled = true;
4447 smc->linux_pci_probe = true;
4448 smc->smp_threads_vsmt = true;
4449 smc->nr_xirqs = SPAPR_NR_XIRQS;
4450 }
4451
4452 static const TypeInfo spapr_machine_info = {
4453 .name = TYPE_SPAPR_MACHINE,
4454 .parent = TYPE_MACHINE,
4455 .abstract = true,
4456 .instance_size = sizeof(SpaprMachineState),
4457 .instance_init = spapr_instance_init,
4458 .instance_finalize = spapr_machine_finalizefn,
4459 .class_size = sizeof(SpaprMachineClass),
4460 .class_init = spapr_machine_class_init,
4461 .interfaces = (InterfaceInfo[]) {
4462 { TYPE_FW_PATH_PROVIDER },
4463 { TYPE_NMI },
4464 { TYPE_HOTPLUG_HANDLER },
4465 { TYPE_PPC_VIRTUAL_HYPERVISOR },
4466 { TYPE_XICS_FABRIC },
4467 { TYPE_INTERRUPT_STATS_PROVIDER },
4468 { }
4469 },
4470 };
4471
4472 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4473 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4474 void *data) \
4475 { \
4476 MachineClass *mc = MACHINE_CLASS(oc); \
4477 spapr_machine_##suffix##_class_options(mc); \
4478 if (latest) { \
4479 mc->alias = "pseries"; \
4480 mc->is_default = 1; \
4481 } \
4482 } \
4483 static const TypeInfo spapr_machine_##suffix##_info = { \
4484 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4485 .parent = TYPE_SPAPR_MACHINE, \
4486 .class_init = spapr_machine_##suffix##_class_init, \
4487 }; \
4488 static void spapr_machine_register_##suffix(void) \
4489 { \
4490 type_register(&spapr_machine_##suffix##_info); \
4491 } \
4492 type_init(spapr_machine_register_##suffix)
4493
4494 /*
4495 * pseries-4.2
4496 */
spapr_machine_4_2_class_options(MachineClass * mc)4497 static void spapr_machine_4_2_class_options(MachineClass *mc)
4498 {
4499 /* Defaults for the latest behaviour inherited from the base class */
4500 }
4501
4502 DEFINE_SPAPR_MACHINE(4_2, "4.2", true);
4503
4504 /*
4505 * pseries-4.1
4506 */
spapr_machine_4_1_class_options(MachineClass * mc)4507 static void spapr_machine_4_1_class_options(MachineClass *mc)
4508 {
4509 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4510 static GlobalProperty compat[] = {
4511 /* Only allow 4kiB and 64kiB IOMMU pagesizes */
4512 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" },
4513 };
4514
4515 spapr_machine_4_2_class_options(mc);
4516 smc->linux_pci_probe = false;
4517 smc->smp_threads_vsmt = false;
4518 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
4519 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4520 }
4521
4522 DEFINE_SPAPR_MACHINE(4_1, "4.1", false);
4523
4524 /*
4525 * pseries-4.0
4526 */
phb_placement_4_0(SpaprMachineState * spapr,uint32_t index,uint64_t * buid,hwaddr * pio,hwaddr * mmio32,hwaddr * mmio64,unsigned n_dma,uint32_t * liobns,hwaddr * nv2gpa,hwaddr * nv2atsd,Error ** errp)4527 static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index,
4528 uint64_t *buid, hwaddr *pio,
4529 hwaddr *mmio32, hwaddr *mmio64,
4530 unsigned n_dma, uint32_t *liobns,
4531 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4532 {
4533 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns,
4534 nv2gpa, nv2atsd, errp);
4535 *nv2gpa = 0;
4536 *nv2atsd = 0;
4537 }
4538
spapr_machine_4_0_class_options(MachineClass * mc)4539 static void spapr_machine_4_0_class_options(MachineClass *mc)
4540 {
4541 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4542
4543 spapr_machine_4_1_class_options(mc);
4544 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
4545 smc->phb_placement = phb_placement_4_0;
4546 smc->irq = &spapr_irq_xics;
4547 smc->pre_4_1_migration = true;
4548 }
4549
4550 DEFINE_SPAPR_MACHINE(4_0, "4.0", false);
4551
4552 /*
4553 * pseries-3.1
4554 */
spapr_machine_3_1_class_options(MachineClass * mc)4555 static void spapr_machine_3_1_class_options(MachineClass *mc)
4556 {
4557 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4558
4559 spapr_machine_4_0_class_options(mc);
4560 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
4561
4562 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
4563 smc->update_dt_enabled = false;
4564 smc->dr_phb_enabled = false;
4565 smc->broken_host_serial_model = true;
4566 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
4567 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
4568 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
4569 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF;
4570 }
4571
4572 DEFINE_SPAPR_MACHINE(3_1, "3.1", false);
4573
4574 /*
4575 * pseries-3.0
4576 */
4577
spapr_machine_3_0_class_options(MachineClass * mc)4578 static void spapr_machine_3_0_class_options(MachineClass *mc)
4579 {
4580 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4581
4582 spapr_machine_3_1_class_options(mc);
4583 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
4584
4585 smc->legacy_irq_allocation = true;
4586 smc->nr_xirqs = 0x400;
4587 smc->irq = &spapr_irq_xics_legacy;
4588 }
4589
4590 DEFINE_SPAPR_MACHINE(3_0, "3.0", false);
4591
4592 /*
4593 * pseries-2.12
4594 */
spapr_machine_2_12_class_options(MachineClass * mc)4595 static void spapr_machine_2_12_class_options(MachineClass *mc)
4596 {
4597 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4598 static GlobalProperty compat[] = {
4599 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" },
4600 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" },
4601 };
4602
4603 spapr_machine_3_0_class_options(mc);
4604 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
4605 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4606
4607 /* We depend on kvm_enabled() to choose a default value for the
4608 * hpt-max-page-size capability. Of course we can't do it here
4609 * because this is too early and the HW accelerator isn't initialzed
4610 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4611 */
4612 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;
4613 }
4614
4615 DEFINE_SPAPR_MACHINE(2_12, "2.12", false);
4616
spapr_machine_2_12_sxxm_class_options(MachineClass * mc)4617 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc)
4618 {
4619 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4620
4621 spapr_machine_2_12_class_options(mc);
4622 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4623 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4624 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
4625 }
4626
4627 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false);
4628
4629 /*
4630 * pseries-2.11
4631 */
4632
spapr_machine_2_11_class_options(MachineClass * mc)4633 static void spapr_machine_2_11_class_options(MachineClass *mc)
4634 {
4635 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4636
4637 spapr_machine_2_12_class_options(mc);
4638 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
4639 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
4640 }
4641
4642 DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
4643
4644 /*
4645 * pseries-2.10
4646 */
4647
spapr_machine_2_10_class_options(MachineClass * mc)4648 static void spapr_machine_2_10_class_options(MachineClass *mc)
4649 {
4650 spapr_machine_2_11_class_options(mc);
4651 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
4652 }
4653
4654 DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
4655
4656 /*
4657 * pseries-2.9
4658 */
4659
spapr_machine_2_9_class_options(MachineClass * mc)4660 static void spapr_machine_2_9_class_options(MachineClass *mc)
4661 {
4662 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4663 static GlobalProperty compat[] = {
4664 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" },
4665 };
4666
4667 spapr_machine_2_10_class_options(mc);
4668 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
4669 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4670 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
4671 smc->pre_2_10_has_unused_icps = true;
4672 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
4673 }
4674
4675 DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
4676
4677 /*
4678 * pseries-2.8
4679 */
4680
spapr_machine_2_8_class_options(MachineClass * mc)4681 static void spapr_machine_2_8_class_options(MachineClass *mc)
4682 {
4683 static GlobalProperty compat[] = {
4684 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" },
4685 };
4686
4687 spapr_machine_2_9_class_options(mc);
4688 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
4689 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4690 mc->numa_mem_align_shift = 23;
4691 }
4692
4693 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
4694
4695 /*
4696 * pseries-2.7
4697 */
4698
phb_placement_2_7(SpaprMachineState * spapr,uint32_t index,uint64_t * buid,hwaddr * pio,hwaddr * mmio32,hwaddr * mmio64,unsigned n_dma,uint32_t * liobns,hwaddr * nv2gpa,hwaddr * nv2atsd,Error ** errp)4699 static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index,
4700 uint64_t *buid, hwaddr *pio,
4701 hwaddr *mmio32, hwaddr *mmio64,
4702 unsigned n_dma, uint32_t *liobns,
4703 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4704 {
4705 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4706 const uint64_t base_buid = 0x800000020000000ULL;
4707 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
4708 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
4709 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
4710 const uint32_t max_index = 255;
4711 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
4712
4713 uint64_t ram_top = MACHINE(spapr)->ram_size;
4714 hwaddr phb0_base, phb_base;
4715 int i;
4716
4717 /* Do we have device memory? */
4718 if (MACHINE(spapr)->maxram_size > ram_top) {
4719 /* Can't just use maxram_size, because there may be an
4720 * alignment gap between normal and device memory regions
4721 */
4722 ram_top = MACHINE(spapr)->device_memory->base +
4723 memory_region_size(&MACHINE(spapr)->device_memory->mr);
4724 }
4725
4726 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4727
4728 if (index > max_index) {
4729 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4730 max_index);
4731 return;
4732 }
4733
4734 *buid = base_buid + index;
4735 for (i = 0; i < n_dma; ++i) {
4736 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4737 }
4738
4739 phb_base = phb0_base + index * phb_spacing;
4740 *pio = phb_base + pio_offset;
4741 *mmio32 = phb_base + mmio_offset;
4742 /*
4743 * We don't set the 64-bit MMIO window, relying on the PHB's
4744 * fallback behaviour of automatically splitting a large "32-bit"
4745 * window into contiguous 32-bit and 64-bit windows
4746 */
4747
4748 *nv2gpa = 0;
4749 *nv2atsd = 0;
4750 }
4751
spapr_machine_2_7_class_options(MachineClass * mc)4752 static void spapr_machine_2_7_class_options(MachineClass *mc)
4753 {
4754 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4755 static GlobalProperty compat[] = {
4756 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", },
4757 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", },
4758 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", },
4759 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", },
4760 };
4761
4762 spapr_machine_2_8_class_options(mc);
4763 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
4764 mc->default_machine_opts = "modern-hotplug-events=off";
4765 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
4766 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4767 smc->phb_placement = phb_placement_2_7;
4768 }
4769
4770 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
4771
4772 /*
4773 * pseries-2.6
4774 */
4775
spapr_machine_2_6_class_options(MachineClass * mc)4776 static void spapr_machine_2_6_class_options(MachineClass *mc)
4777 {
4778 static GlobalProperty compat[] = {
4779 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" },
4780 };
4781
4782 spapr_machine_2_7_class_options(mc);
4783 mc->has_hotpluggable_cpus = false;
4784 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
4785 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4786 }
4787
4788 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4789
4790 /*
4791 * pseries-2.5
4792 */
4793
spapr_machine_2_5_class_options(MachineClass * mc)4794 static void spapr_machine_2_5_class_options(MachineClass *mc)
4795 {
4796 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4797 static GlobalProperty compat[] = {
4798 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4799 };
4800
4801 spapr_machine_2_6_class_options(mc);
4802 smc->use_ohci_by_default = true;
4803 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len);
4804 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4805 }
4806
4807 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
4808
4809 /*
4810 * pseries-2.4
4811 */
4812
spapr_machine_2_4_class_options(MachineClass * mc)4813 static void spapr_machine_2_4_class_options(MachineClass *mc)
4814 {
4815 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4816
4817 spapr_machine_2_5_class_options(mc);
4818 smc->dr_lmb_enabled = false;
4819 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len);
4820 }
4821
4822 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
4823
4824 /*
4825 * pseries-2.3
4826 */
4827
spapr_machine_2_3_class_options(MachineClass * mc)4828 static void spapr_machine_2_3_class_options(MachineClass *mc)
4829 {
4830 static GlobalProperty compat[] = {
4831 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4832 };
4833 spapr_machine_2_4_class_options(mc);
4834 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len);
4835 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4836 }
4837 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
4838
4839 /*
4840 * pseries-2.2
4841 */
4842
spapr_machine_2_2_class_options(MachineClass * mc)4843 static void spapr_machine_2_2_class_options(MachineClass *mc)
4844 {
4845 static GlobalProperty compat[] = {
4846 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" },
4847 };
4848
4849 spapr_machine_2_3_class_options(mc);
4850 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len);
4851 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4852 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on";
4853 }
4854 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4855
4856 /*
4857 * pseries-2.1
4858 */
4859
spapr_machine_2_1_class_options(MachineClass * mc)4860 static void spapr_machine_2_1_class_options(MachineClass *mc)
4861 {
4862 spapr_machine_2_2_class_options(mc);
4863 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len);
4864 }
4865 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4866
spapr_machine_register_types(void)4867 static void spapr_machine_register_types(void)
4868 {
4869 type_register_static(&spapr_machine_info);
4870 }
4871
4872 type_init(spapr_machine_register_types)
4873