1 /** @file 2 * SMSC LAN91x series Network Controller Driver. 3 * 4 * Copyright (c) 2013-2017 Linaro.org 5 * 6 * SPDX-License-Identifier: BSD-2-Clause-Patent 7 * 8 **/ 9 10 #ifndef __LAN91XDXEHW_H__ 11 #define __LAN91XDXEHW_H__ 12 13 #include <Base.h> 14 15 #define MakeRegister(Bank, Offset) (((Bank) << 8) | (Offset)) 16 #define RegisterToBank(Register) (((Register) >> 8) & 0x07) 17 #define RegisterToOffset(Register) ((Register) & 0x0f) 18 19 /*--------------------------------------------------------------------------------------------------------------------- 20 21 SMSC LAN91x Registers 22 23 ---------------------------------------------------------------------------------------------------------------------*/ 24 #define LAN91X_BANK_OFFSET 0xe // Bank Select Register (all banks) 25 26 #define LAN91X_TCR MakeRegister (0, 0x0) // Transmit Control Register 27 #define LAN91X_EPHSR MakeRegister (0, 0x2) // EPH Status Register 28 #define LAN91X_RCR MakeRegister (0, 0x4) // Receive Control Register 29 #define LAN91X_ECR MakeRegister (0, 0x6) // Counter Register 30 #define LAN91X_MIR MakeRegister (0, 0x8) // Memory Information Register 31 #define LAN91X_RPCR MakeRegister (0, 0xa) // Receive/Phy Control Register 32 33 #define LAN91X_CR MakeRegister (1, 0x0) // Configuration Register 34 #define LAN91X_BAR MakeRegister (1, 0x2) // Base Address Register 35 #define LAN91X_IAR0 MakeRegister (1, 0x4) // Individual Address Register 0 36 #define LAN91X_IAR1 MakeRegister (1, 0x5) // Individual Address Register 1 37 #define LAN91X_IAR2 MakeRegister (1, 0x6) // Individual Address Register 2 38 #define LAN91X_IAR3 MakeRegister (1, 0x7) // Individual Address Register 3 39 #define LAN91X_IAR4 MakeRegister (1, 0x8) // Individual Address Register 4 40 #define LAN91X_IAR5 MakeRegister (1, 0x9) // Individual Address Register 5 41 #define LAN91X_GPR MakeRegister (1, 0xa) // General Purpose Register 42 #define LAN91X_CTR MakeRegister (1, 0xc) // Control Register 43 44 #define LAN91X_MMUCR MakeRegister (2, 0x0) // MMU Command Register 45 #define LAN91X_PNR MakeRegister (2, 0x2) // Packet Number Register 46 #define LAN91X_ARR MakeRegister (2, 0x3) // Allocation Result Register 47 #define LAN91X_FIFO MakeRegister (2, 0x4) // FIFO Ports Register 48 #define LAN91X_PTR MakeRegister (2, 0x6) // Pointer Register 49 #define LAN91X_DATA0 MakeRegister (2, 0x8) // Data Register 0 50 #define LAN91X_DATA1 MakeRegister (2, 0x9) // Data Register 1 51 #define LAN91X_DATA2 MakeRegister (2, 0xa) // Data Register 2 52 #define LAN91X_DATA3 MakeRegister (2, 0xb) // Data Register 3 53 #define LAN91X_IST MakeRegister (2, 0xc) // Interrupt Status Register 54 #define LAN91X_MSK MakeRegister (2, 0xd) // Interrupt Mask Register 55 56 #define LAN91X_MT0 MakeRegister (3, 0x0) // Multicast Table Register 0 57 #define LAN91X_MT1 MakeRegister (3, 0x1) // Multicast Table Register 1 58 #define LAN91X_MT2 MakeRegister (3, 0x2) // Multicast Table Register 2 59 #define LAN91X_MT3 MakeRegister (3, 0x3) // Multicast Table Register 3 60 #define LAN91X_MT4 MakeRegister (3, 0x4) // Multicast Table Register 4 61 #define LAN91X_MT5 MakeRegister (3, 0x5) // Multicast Table Register 5 62 #define LAN91X_MT6 MakeRegister (3, 0x6) // Multicast Table Register 6 63 #define LAN91X_MT7 MakeRegister (3, 0x7) // Multicast Table Register 7 64 #define LAN91X_MGMT MakeRegister (3, 0x8) // Management Interface Register 65 #define LAN91X_REV MakeRegister (3, 0xa) // Revision Register 66 #define LAN91X_RCV MakeRegister (3, 0xc) // RCV Register 67 68 // Transmit Control Register Bits 69 #define TCR_TXENA BIT0 70 #define TCR_LOOP BIT1 71 #define TCR_FORCOL BIT2 72 #define TCR_PAD_EN BIT7 73 #define TCR_NOCRC BIT8 74 #define TCR_MON_CSN BIT10 75 #define TCR_FDUPLX BIT11 76 #define TCR_STP_SQET BIT12 77 #define TCR_EPH_LOOP BIT13 78 #define TCR_SWFDUP BIT15 79 80 #define TCR_DEFAULT (TCR_TXENA | TCR_PAD_EN) 81 #define TCR_CLEAR 0x0 82 83 // EPH Status Register Bits 84 #define EPHSR_TX_SUC BIT0 85 #define EPHSR_SNGLCOL BIT1 86 #define EPHSR_MULCOL BIT2 87 #define EPHSR_LTX_MULT BIT3 88 #define EPHSR_16COL BIT4 89 #define EPHSR_SQET BIT5 90 #define EPHSR_LTX_BRD BIT6 91 #define EPHSR_TX_DEFR BIT7 92 #define EPHSR_LATCOL BIT9 93 #define EPHSR_LOST_CARR BIT10 94 #define EPHSR_EXC_DEF BIT11 95 #define EPHSR_CTR_ROL BIT12 96 #define EPHSR_LINK_OK BIT14 97 98 // Receive Control Register Bits 99 #define RCR_RX_ABORT BIT0 100 #define RCR_PRMS BIT1 101 #define RCR_ALMUL BIT2 102 #define RCR_RXEN BIT8 103 #define RCR_STRIP_CRC BIT9 104 #define RCR_ABORT_ENB BIT13 105 #define RCR_FILT_CAR BIT14 106 #define RCR_SOFT_RST BIT15 107 108 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) 109 #define RCR_CLEAR 0x0 110 111 // Receive/Phy Control Register Bits 112 #define RPCR_LS0B BIT2 113 #define RPCR_LS1B BIT3 114 #define RPCR_LS2B BIT4 115 #define RPCR_LS0A BIT5 116 #define RPCR_LS1A BIT6 117 #define RPCR_LS2A BIT7 118 #define RPCR_ANEG BIT11 119 #define RPCR_DPLX BIT12 120 #define RPCR_SPEED BIT13 121 122 // Configuration Register Bits 123 #define CR_EXT_PHY BIT9 124 #define CR_GPCNTRL BIT10 125 #define CR_NO_WAIT BIT12 126 #define CR_EPH_POWER_EN BIT15 127 128 #define CR_DEFAULT (CR_EPH_POWER_EN | CR_NO_WAIT) 129 130 // Control Register Bits 131 #define CTR_STORE BIT0 132 #define CTR_RELOAD BIT1 133 #define CTR_EEPROM_SEL BIT2 134 #define CTR_TE_ENABLE BIT5 135 #define CTR_CR_ENABLE BIT6 136 #define CTR_LE_ENABLE BIT7 137 #define CTR_AUTO_REL BIT11 138 #define CTR_RCV_BAD BIT14 139 140 #define CTR_RESERVED (BIT12 | BIT9 | BIT4) 141 #define CTR_DEFAULT (CTR_RESERVED | CTR_AUTO_REL) 142 143 // MMU Command Register Bits 144 #define MMUCR_BUSY BIT0 145 146 // MMU Command Register Operaction Codes 147 #define MMUCR_OP_NOOP (0 << 5) // No operation 148 #define MMUCR_OP_TX_ALLOC (1 << 5) // Allocate memory for TX 149 #define MMUCR_OP_RESET_MMU (2 << 5) // Reset MMU to initial state 150 #define MMUCR_OP_RX_POP (3 << 5) // Remove frame from top of RX FIFO 151 #define MMUCR_OP_RX_POP_REL (4 << 5) // Remove and release frame from top of RX FIFO 152 #define MMUCR_OP_RX_REL (5 << 5) // Release specific RX frame 153 #define MMUCR_OP_TX_PUSH (6 << 5) // Enqueue packet number into TX FIFO 154 #define MMUCR_OP_TX_RESET (7 << 5) // Reset TX FIFOs 155 156 // Packet Number Register Bits 157 #define PNR_PACKET (0x3f) 158 159 // Allocation Result Register Bits 160 #define ARR_PACKET (0x3f) 161 #define ARR_FAILED BIT7 162 163 // FIFO Ports Register Bits 164 #define FIFO_TX_PACKET (0x003f) 165 #define FIFO_TEMPTY BIT7 166 #define FIFO_RX_PACKET (0x3f00) 167 #define FIFO_REMPTY BIT15 168 169 // Pointer Register Bits 170 #define PTR_POINTER (0x07ff) 171 #define PTR_NOT_EMPTY BIT11 172 #define PTR_READ BIT13 173 #define PTR_AUTO_INCR BIT14 174 #define PTR_RCV BIT15 175 176 // Interupt Status and Mask Register Bits 177 #define IST_RCV BIT0 178 #define IST_TX BIT1 179 #define IST_TX_EMPTY BIT2 180 #define IST_ALLOC BIT3 181 #define IST_RX_OVRN BIT4 182 #define IST_EPH BIT5 183 #define IST_MD BIT7 184 185 // Management Interface 186 #define MGMT_MDO BIT0 187 #define MGMT_MDI BIT1 188 #define MGMT_MCLK BIT2 189 #define MGMT_MDOE BIT3 190 #define MGMT_MSK_CRS100 BIT14 191 192 // RCV Register 193 #define RCV_MBO (0x1f) 194 #define RCV_RCV_DISCRD BIT7 195 196 // Packet RX Status word bits 197 #define RX_MULTICAST BIT0 198 #define RX_HASH (0x7e) 199 #define RX_TOO_SHORT BIT10 200 #define RX_TOO_LONG BIT11 201 #define RX_ODD_FRAME BIT12 202 #define RX_BAD_CRC BIT13 203 #define RX_BROADCAST BIT14 204 #define RX_ALGN_ERR BIT15 205 206 // Packet Byte Count word bits 207 #define BCW_COUNT (0x7fe) 208 209 // Packet Control Word bits 210 #define PCW_ODD_BYTE (0x00ff) 211 #define PCW_CRC BIT12 212 #define PCW_ODD BIT13 213 214 /*--------------------------------------------------------------------------------------------------------------------- 215 216 SMSC PHY Registers 217 218 Most of these should be common, as there is 219 documented STANDARD for PHY registers! 220 221 ---------------------------------------------------------------------------------------------------------------------*/ 222 // 223 // PHY Register Numbers 224 // 225 #define PHY_INDEX_BASIC_CTRL 0 226 #define PHY_INDEX_BASIC_STATUS 1 227 #define PHY_INDEX_ID1 2 228 #define PHY_INDEX_ID2 3 229 #define PHY_INDEX_AUTO_NEG_ADVERT 4 230 #define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5 231 232 #define PHY_INDEX_CONFIG1 16 233 #define PHY_INDEX_CONFIG2 17 234 #define PHY_INDEX_STATUS_OUTPUT 18 235 #define PHY_INDEX_MASK 19 236 237 238 // PHY control register bits 239 #define PHYCR_COLL_TEST BIT7 // Collision test enable 240 #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode 241 #define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities 242 #define PHYCR_PD BIT11 // Power-Down switch 243 #define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable 244 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection 245 #define PHYCR_LOOPBK BIT14 // Set loopback mode 246 #define PHYCR_RESET BIT15 // Do a PHY reset 247 248 // PHY status register bits 249 #define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability 250 #define PHYSTS_JABBER BIT1 // Jabber condition detected 251 #define PHYSTS_LINK_STS BIT2 // Link Status 252 #define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability 253 #define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected 254 #define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed 255 #define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability 256 #define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability 257 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability 258 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability 259 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability 260 261 // PHY Auto-Negotiation advertisement 262 #define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector 263 #define PHYANA_CSMA BIT0 // Advertise CSMA capability 264 #define PHYANA_10BASET BIT5 // Advertise 10BASET capability 265 #define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability 266 #define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability 267 #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability 268 #define PHYANA_100BASET4 BIT9 // Advertise 100 BASETX Full duplex capability 269 #define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability 270 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected 271 272 #endif /* __LAN91XDXEHW_H__ */ 273