1 /** @file 2 Private Header file for Usb Host Controller PEIM 3 4 Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR> 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef _RECOVERY_EHC_H_ 11 #define _RECOVERY_EHC_H_ 12 13 #include <PiPei.h> 14 15 #include <Ppi/UsbController.h> 16 #include <Ppi/Usb2HostController.h> 17 #include <Ppi/IoMmu.h> 18 #include <Ppi/EndOfPeiPhase.h> 19 20 #include <Library/DebugLib.h> 21 #include <Library/PeimEntryPoint.h> 22 #include <Library/PeiServicesLib.h> 23 #include <Library/BaseMemoryLib.h> 24 #include <Library/TimerLib.h> 25 #include <Library/IoLib.h> 26 27 typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV; 28 29 #define EFI_LIST_ENTRY LIST_ENTRY 30 31 #include "UsbHcMem.h" 32 #include "EhciReg.h" 33 #include "EhciUrb.h" 34 #include "EhciSched.h" 35 36 #define EFI_USB_SPEED_FULL 0x0000 37 #define EFI_USB_SPEED_LOW 0x0001 38 #define EFI_USB_SPEED_HIGH 0x0002 39 40 #define PAGESIZE 4096 41 42 #define EHC_1_MICROSECOND 1 43 #define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND) 44 #define EHC_1_SECOND (1000 * EHC_1_MILLISECOND) 45 46 // 47 // EHCI register operation timeout, set by experience 48 // 49 #define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND) 50 #define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND) 51 52 53 // 54 // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9] 55 // 56 #define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND) 57 58 // 59 // Sync transfer polling interval, set by experience. 60 // 61 #define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND) 62 63 // 64 //Iterate through the double linked list. NOT delete safe 65 // 66 #define EFI_LIST_FOR_EACH(Entry, ListHead) \ 67 for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink) 68 69 // 70 //Iterate through the double linked list. This is delete-safe. 71 //Don't touch NextEntry 72 // 73 #define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \ 74 for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\ 75 Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink) 76 77 #define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field) 78 79 80 #define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF)) 81 #define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF)) 82 #define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit))) 83 84 #define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \ 85 (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit))) 86 87 #define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i') 88 89 struct _PEI_USB2_HC_DEV { 90 UINTN Signature; 91 PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi; 92 EDKII_IOMMU_PPI *IoMmu; 93 EFI_PEI_PPI_DESCRIPTOR PpiDescriptor; 94 // 95 // EndOfPei callback is used to stop the EHC DMA operation 96 // after exit PEI phase. 97 // 98 EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList; 99 UINT32 UsbHostControllerBaseAddress; 100 PEI_URB *Urb; 101 USBHC_MEM_POOL *MemPool; 102 103 // 104 // Schedule data shared between asynchronous and periodic 105 // transfers: 106 // ShortReadStop, as its name indicates, is used to terminate 107 // the short read except the control transfer. EHCI follows 108 // the alternative next QTD point when a short read happens. 109 // For control transfer, even the short read happens, try the 110 // status stage. 111 // 112 PEI_EHC_QTD *ShortReadStop; 113 EFI_EVENT PollTimer; 114 115 // 116 // Asynchronous(bulk and control) transfer schedule data: 117 // ReclaimHead is used as the head of the asynchronous transfer 118 // list. It acts as the reclamation header. 119 // 120 PEI_EHC_QH *ReclaimHead; 121 122 // 123 // Periodic (interrupt) transfer schedule data: 124 // 125 VOID *PeriodFrame; // Mapped as common buffer 126 VOID *PeriodFrameMap; 127 128 PEI_EHC_QH *PeriodOne; 129 EFI_LIST_ENTRY AsyncIntTransfers; 130 131 // 132 // EHCI configuration data 133 // 134 UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET 135 UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS 136 UINT32 CapLen; // Capability length 137 UINT32 High32bitAddr; 138 }; 139 140 #define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE) 141 #define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE) 142 143 /** 144 @param EhcDev EHCI Device. 145 146 @retval EFI_SUCCESS EHCI successfully initialized. 147 @retval EFI_ABORTED EHCI was failed to be initialized. 148 149 **/ 150 EFI_STATUS 151 InitializeUsbHC ( 152 IN PEI_USB2_HC_DEV *EhcDev 153 ); 154 155 /** 156 Initialize the memory management pool for the host controller. 157 158 @param Ehc The EHCI device. 159 @param Check4G Whether the host controller requires allocated memory 160 from one 4G address space. 161 @param Which4G The 4G memory area each memory allocated should be from. 162 163 @retval EFI_SUCCESS The memory pool is initialized. 164 @retval EFI_OUT_OF_RESOURCE Fail to init the memory pool. 165 166 **/ 167 USBHC_MEM_POOL * 168 UsbHcInitMemPool ( 169 IN PEI_USB2_HC_DEV *Ehc, 170 IN BOOLEAN Check4G, 171 IN UINT32 Which4G 172 ) 173 ; 174 175 /** 176 Release the memory management pool. 177 178 @param Ehc The EHCI device. 179 @param Pool The USB memory pool to free. 180 181 @retval EFI_DEVICE_ERROR Fail to free the memory pool. 182 @retval EFI_SUCCESS The memory pool is freed. 183 184 **/ 185 EFI_STATUS 186 UsbHcFreeMemPool ( 187 IN PEI_USB2_HC_DEV *Ehc, 188 IN USBHC_MEM_POOL *Pool 189 ) 190 ; 191 192 /** 193 Allocate some memory from the host controller's memory pool 194 which can be used to communicate with host controller. 195 196 @param Ehc The EHCI device. 197 @param Pool The host controller's memory pool. 198 @param Size Size of the memory to allocate. 199 200 @return The allocated memory or NULL. 201 202 **/ 203 VOID * 204 UsbHcAllocateMem ( 205 IN PEI_USB2_HC_DEV *Ehc, 206 IN USBHC_MEM_POOL *Pool, 207 IN UINTN Size 208 ) 209 ; 210 211 /** 212 Free the allocated memory back to the memory pool. 213 214 @param Ehc The EHCI device. 215 @param Pool The memory pool of the host controller. 216 @param Mem The memory to free. 217 @param Size The size of the memory to free. 218 219 **/ 220 VOID 221 UsbHcFreeMem ( 222 IN PEI_USB2_HC_DEV *Ehc, 223 IN USBHC_MEM_POOL *Pool, 224 IN VOID *Mem, 225 IN UINTN Size 226 ) 227 ; 228 229 /** 230 Provides the controller-specific addresses required to access system memory from a 231 DMA bus master. 232 233 @param IoMmu Pointer to IOMMU PPI. 234 @param Operation Indicates if the bus master is going to read or write to system memory. 235 @param HostAddress The system memory address to map to the PCI controller. 236 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes 237 that were mapped. 238 @param DeviceAddress The resulting map address for the bus master PCI controller to use to 239 access the hosts HostAddress. 240 @param Mapping A resulting value to pass to Unmap(). 241 242 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. 243 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. 244 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 245 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 246 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address. 247 248 **/ 249 EFI_STATUS 250 IoMmuMap ( 251 IN EDKII_IOMMU_PPI *IoMmu, 252 IN EDKII_IOMMU_OPERATION Operation, 253 IN VOID *HostAddress, 254 IN OUT UINTN *NumberOfBytes, 255 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, 256 OUT VOID **Mapping 257 ); 258 259 /** 260 Completes the Map() operation and releases any corresponding resources. 261 262 @param IoMmu Pointer to IOMMU PPI. 263 @param Mapping The mapping value returned from Map(). 264 265 **/ 266 VOID 267 IoMmuUnmap ( 268 IN EDKII_IOMMU_PPI *IoMmu, 269 IN VOID *Mapping 270 ); 271 272 /** 273 Allocates pages that are suitable for an OperationBusMasterCommonBuffer or 274 OperationBusMasterCommonBuffer64 mapping. 275 276 @param IoMmu Pointer to IOMMU PPI. 277 @param Pages The number of pages to allocate. 278 @param HostAddress A pointer to store the base system memory address of the 279 allocated range. 280 @param DeviceAddress The resulting map address for the bus master PCI controller to use to 281 access the hosts HostAddress. 282 @param Mapping A resulting value to pass to Unmap(). 283 284 @retval EFI_SUCCESS The requested memory pages were allocated. 285 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are 286 MEMORY_WRITE_COMBINE and MEMORY_CACHED. 287 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 288 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. 289 290 **/ 291 EFI_STATUS 292 IoMmuAllocateBuffer ( 293 IN EDKII_IOMMU_PPI *IoMmu, 294 IN UINTN Pages, 295 OUT VOID **HostAddress, 296 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, 297 OUT VOID **Mapping 298 ); 299 300 /** 301 Frees memory that was allocated with AllocateBuffer(). 302 303 @param IoMmu Pointer to IOMMU PPI. 304 @param Pages The number of pages to free. 305 @param HostAddress The base system memory address of the allocated range. 306 @param Mapping The mapping value returned from Map(). 307 308 **/ 309 VOID 310 IoMmuFreeBuffer ( 311 IN EDKII_IOMMU_PPI *IoMmu, 312 IN UINTN Pages, 313 IN VOID *HostAddress, 314 IN VOID *Mapping 315 ); 316 317 /** 318 Initialize IOMMU. 319 320 @param IoMmu Pointer to pointer to IOMMU PPI. 321 322 **/ 323 VOID 324 IoMmuInit ( 325 OUT EDKII_IOMMU_PPI **IoMmu 326 ); 327 328 #endif 329