1 /*
2 * OpenBIOS pci driver
3 *
4 * This driver is compliant to the
5 * PCI bus binding to IEEE 1275-1994 Rev 2.1
6 *
7 * (C) 2004 Stefan Reinauer
8 * (C) 2005 Ed Schouten <ed@fxq.nl>
9 *
10 * Some parts from OpenHackWare-0.4, Copyright (c) 2004-2005 Jocelyn Mayer
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2
15 *
16 */
17
18 #include "config.h"
19 #include "libopenbios/bindings.h"
20 #include "libopenbios/ofmem.h"
21 #include "kernel/kernel.h"
22 #include "drivers/pci.h"
23 #include "libc/byteorder.h"
24 #include "libc/vsprintf.h"
25
26 #include "drivers/drivers.h"
27 #include "drivers/vga.h"
28 #include "packages/video.h"
29 #include "libopenbios/video.h"
30 #include "timer.h"
31 #include "pci.h"
32 #include "pci_database.h"
33 #ifdef CONFIG_DRIVER_MACIO
34 #include "macio.h"
35 #endif
36 #ifdef CONFIG_DRIVER_USB
37 #include "drivers/usb.h"
38 #endif
39 #ifdef CONFIG_DRIVER_VIRTIO_BLK
40 #include "virtio.h"
41 #endif
42
43 #if defined (CONFIG_DEBUG_PCI)
44 # define PCI_DPRINTF(format, ...) printk(format, ## __VA_ARGS__)
45 #else
46 # define PCI_DPRINTF(format, ...) do { } while (0)
47 #endif
48
49 #define set_bool_property(ph, name) set_property(ph, name, NULL, 0);
50
51 /* DECLARE data structures for the nodes. */
52
53 DECLARE_UNNAMED_NODE( ob_pci_bus_node, INSTALL_OPEN, 2*sizeof(int) );
54 DECLARE_UNNAMED_NODE( ob_pci_bridge_node, INSTALL_OPEN, 2*sizeof(int) );
55 DECLARE_UNNAMED_NODE( ob_pci_simple_node, 0, 2*sizeof(int) );
56
57 const pci_arch_t *arch;
58
59 #define IS_NOT_RELOCATABLE 0x80000000
60 #define IS_PREFETCHABLE 0x40000000
61 #define IS_ALIASED 0x20000000
62
encode_int32_cells(int num_cells,u32 * prop,ucell val)63 static int encode_int32_cells(int num_cells, u32 *prop, ucell val)
64 {
65 int i = 0;
66
67 /* hi ... lo */
68 for (i=0; i < num_cells; ++i) {
69 prop[num_cells - i - 1] = val;
70 val >>= 16;
71 val >>= 16;
72 }
73
74 return num_cells;
75 }
76
pci_encode_phys_addr(u32 * phys,int flags,int space_code,pci_addr dev,uint8_t reg,uint64_t addr)77 static inline int pci_encode_phys_addr(u32 *phys, int flags, int space_code,
78 pci_addr dev, uint8_t reg, uint64_t addr)
79 {
80
81 /* phys.hi */
82
83 phys[0] = flags | (space_code << 24) | dev | reg;
84
85 /* phys.mid */
86
87 phys[1] = addr >> 32;
88
89 /* phys.lo */
90
91 phys[2] = addr;
92
93 return 3;
94 }
95
pci_encode_size(u32 * prop,uint64_t size)96 static inline int pci_encode_size(u32 *prop, uint64_t size)
97 {
98 return encode_int32_cells(2, prop, size);
99 }
100
host_address_cells(void)101 static int host_address_cells(void)
102 {
103 return get_int_property(find_dev("/"), "#address-cells", NULL);
104 }
105
host_encode_phys_addr(u32 * prop,ucell addr)106 static int host_encode_phys_addr(u32 *prop, ucell addr)
107 {
108 return encode_int32_cells(host_address_cells(), prop, addr);
109 }
110
host_size_cells(void)111 static int host_size_cells(void)
112 {
113 return get_int_property(find_dev("/"), "#size-cells", NULL);
114 }
115
116 /*
117 static int parent_address_cells(void)
118 {
119 phandle_t parent_ph = ih_to_phandle(my_parent());
120 return get_int_property(parent_ph, "#address-cells", NULL);
121 }
122
123 static int parent_size_cells(void)
124 {
125 phandle_t parent_ph = ih_to_phandle(my_parent());
126 return get_int_property(parent_ph, "#size-cells", NULL);
127 }
128 */
129
130 #if defined(CONFIG_DEBUG_PCI)
dump_reg_property(const char * description,int nreg,u32 * reg)131 static void dump_reg_property(const char* description, int nreg, u32 *reg)
132 {
133 int i;
134 printk("%s reg", description);
135 for (i=0; i < nreg; ++i) {
136 printk(" %08X", reg[i]);
137 }
138 printk("\n");
139 }
140 #endif
141
pci_bus_addr_to_host_addr(int space,uint32_t ba)142 static unsigned long pci_bus_addr_to_host_addr(int space, uint32_t ba)
143 {
144 if (space == IO_SPACE) {
145 return arch->io_base + (unsigned long)ba;
146 } else if (space == MEMORY_SPACE_32) {
147 return arch->host_pci_base + (unsigned long)ba;
148 } else {
149 /* Return unaltered to aid debugging property values */
150 return (unsigned long)ba;
151 }
152 }
153
pci_decode_pci_addr(pci_addr addr,int * flags,int * space_code,uint32_t * mask)154 static inline void pci_decode_pci_addr(pci_addr addr, int *flags,
155 int *space_code, uint32_t *mask)
156 {
157 *flags = 0;
158
159 if (addr & 0x01) {
160 *space_code = IO_SPACE;
161 *mask = 0x00000001;
162 } else {
163 if (addr & 0x04) {
164 *space_code = MEMORY_SPACE_64;
165 *flags |= IS_NOT_RELOCATABLE; /* XXX: why not relocatable? */
166 } else {
167 *space_code = MEMORY_SPACE_32;
168 }
169
170 if (addr & 0x08) {
171 *flags |= IS_PREFETCHABLE;
172 }
173
174 *mask = 0x0000000F;
175 }
176 }
177
178 static void
ob_pci_open(int * idx)179 ob_pci_open(int *idx)
180 {
181 int ret=1;
182 RET ( -ret );
183 }
184
185 static void
ob_pci_close(int * idx)186 ob_pci_close(int *idx)
187 {
188 }
189
190 /* ( str len -- phys.lo phys.mid phys.hi ) */
191
192 static void
ob_pci_decode_unit(int * idx)193 ob_pci_decode_unit(int *idx)
194 {
195 ucell hi, mid, lo;
196 const char *arg = pop_fstr_copy();
197 int dev, fn, reg, ss, n, p, t;
198 int bus, len;
199 char *ptr;
200
201 PCI_DPRINTF("ob_pci_decode_unit idx=%p\n", idx);
202
203 fn = 0;
204 reg = 0;
205 n = 0;
206 p = 0;
207 t = 0;
208
209 ptr = (char*)arg;
210 if (*ptr == 'n') {
211 n = IS_NOT_RELOCATABLE;
212 ptr++;
213 }
214 if (*ptr == 'i') {
215 ss = IO_SPACE;
216 ptr++;
217 if (*ptr == 't') {
218 t = IS_ALIASED;
219 ptr++;
220 }
221
222 /* DD,F,RR,NNNNNNNN */
223
224 dev = strtol(ptr, &ptr, 16);
225 ptr++;
226 fn = strtol(ptr, &ptr, 16);
227 ptr++;
228 reg = strtol(ptr, &ptr, 16);
229 ptr++;
230 lo = strtol(ptr, &ptr, 16);
231 mid = 0;
232
233 } else if (*ptr == 'm') {
234 ss = MEMORY_SPACE_32;
235 ptr++;
236 if (*ptr == 't') {
237 t = IS_ALIASED;
238 ptr++;
239 }
240 if (*ptr == 'p') {
241 p = IS_PREFETCHABLE;
242 ptr++;
243 }
244
245 /* DD,F,RR,NNNNNNNN */
246
247 dev = strtol(ptr, &ptr, 16);
248 ptr++;
249 fn = strtol(ptr, &ptr, 16);
250 ptr++;
251 reg = strtol(ptr, &ptr, 16);
252 ptr++;
253 lo = strtol(ptr, &ptr, 16);
254 mid = 0;
255
256 } else if (*ptr == 'x') {
257 unsigned long long addr64;
258 ss = MEMORY_SPACE_64;
259 ptr++;
260 if (*ptr == 'p') {
261 p = IS_PREFETCHABLE;
262 ptr++;
263 }
264
265 /* DD,F,RR,NNNNNNNNNNNNNNNN */
266
267 dev = strtol(ptr, &ptr, 16);
268 ptr++;
269 fn = strtol(ptr, &ptr, 16);
270 ptr++;
271 reg = strtol(ptr, &ptr, 16);
272 ptr++;
273 addr64 = strtoll(ptr, &ptr, 16);
274 lo = (ucell)addr64;
275 mid = addr64 >> 32;
276
277 } else {
278 ss = CONFIGURATION_SPACE;
279 /* "DD" or "DD,FF" */
280 dev = strtol(ptr, &ptr, 16);
281 if (*ptr == ',') {
282 ptr++;
283 fn = strtol(ptr, NULL, 16);
284 }
285 lo = 0;
286 mid = 0;
287 }
288 free((char*)arg);
289
290 bus = get_int_property(get_cur_dev(), "bus-range", &len);
291
292 hi = n | p | t | (ss << 24) | (bus << 16) | (dev << 11) | (fn << 8) | reg;
293
294 PUSH(lo);
295 PUSH(mid);
296 PUSH(hi);
297
298 PCI_DPRINTF("ob_pci_decode_unit idx=%p addr="
299 FMT_ucellx " " FMT_ucellx " " FMT_ucellx "\n",
300 idx, lo, mid, hi);
301 }
302
303 /* ( phys.lo phy.mid phys.hi -- str len ) */
304
305 static void
ob_pci_encode_unit(int * idx)306 ob_pci_encode_unit(int *idx)
307 {
308 char buf[28];
309 cell hi = POP();
310 cell mid = POP();
311 cell lo = POP();
312 int n, p, t, ss, dev, fn, reg;
313
314 n = hi & IS_NOT_RELOCATABLE;
315 p = hi & IS_PREFETCHABLE;
316 t = hi & IS_ALIASED;
317 ss = (hi >> 24) & 0x03;
318
319 dev = (hi >> 11) & 0x1F;
320 fn = (hi >> 8) & 0x07;
321 reg = hi & 0xFF;
322
323 switch(ss) {
324 case CONFIGURATION_SPACE:
325
326 if (fn == 0) /* DD */
327 snprintf(buf, sizeof(buf), "%x", dev);
328 else /* DD,F */
329 snprintf(buf, sizeof(buf), "%x,%x", dev, fn);
330 break;
331
332 case IO_SPACE:
333
334 /* [n]i[t]DD,F,RR,NNNNNNNN */
335 snprintf(buf, sizeof(buf), "%si%s%x,%x,%x," FMT_ucellx,
336 n ? "n" : "", /* relocatable */
337 t ? "t" : "", /* aliased */
338 dev, fn, reg, t ? lo & 0x03FF : lo);
339 break;
340
341 case MEMORY_SPACE_32:
342
343 /* [n]m[t][p]DD,F,RR,NNNNNNNN */
344 snprintf(buf, sizeof(buf), "%sm%s%s%x,%x,%x," FMT_ucellx,
345 n ? "n" : "", /* relocatable */
346 t ? "t" : "", /* aliased */
347 p ? "p" : "", /* prefetchable */
348 dev, fn, reg, lo );
349 break;
350
351 case MEMORY_SPACE_64:
352
353 /* [n]x[p]DD,F,RR,NNNNNNNNNNNNNNNN */
354 snprintf(buf, sizeof(buf), "%sx%s%x,%x,%x,%llx",
355 n ? "n" : "", /* relocatable */
356 p ? "p" : "", /* prefetchable */
357 dev, fn, reg, ((long long)mid << 32) | (long long)lo);
358 break;
359 }
360 push_str(buf);
361
362 PCI_DPRINTF("ob_pci_encode_unit space=%d dev=%d fn=%d buf=%s\n",
363 ss, dev, fn, buf);
364 }
365
366 /* Map PCI MMIO or IO space from the BAR address. Note it is up to the caller
367 to understand whether the resulting address is in MEM or IO space and
368 use the appropriate accesses */
ob_pci_map(uint32_t ba,ucell size)369 static ucell ob_pci_map(uint32_t ba, ucell size) {
370 phys_addr_t phys;
371 uint32_t mask;
372 int flags, space_code;
373 ucell virt;
374
375 pci_decode_pci_addr(ba, &flags, &space_code, &mask);
376
377 phys = pci_bus_addr_to_host_addr(space_code,
378 ba & ~mask);
379
380 #if defined(CONFIG_OFMEM)
381 ofmem_claim_phys(phys, size, 0);
382
383 #if defined(CONFIG_PPC)
384 /* For some reason PPC gets upset when virt != phys for map-in... */
385 virt = ofmem_claim_virt(phys, size, 0);
386 #else
387 virt = ofmem_claim_virt(-1, size, size);
388 #endif
389
390 ofmem_map(phys, virt, size, ofmem_arch_io_translation_mode(phys));
391
392 #else
393 virt = size; /* Keep compiler quiet */
394 virt = phys;
395 #endif
396
397 return virt;
398 }
399
ob_pci_unmap(ucell virt,ucell size)400 static void ob_pci_unmap(ucell virt, ucell size) {
401 #if defined(CONFIG_OFMEM)
402 ofmem_unmap(virt, size);
403 #endif
404 }
405
406 /* ( pci-addr.lo pci-addr.mid pci-addr.hi size -- virt ) */
407
408 static void
ob_pci_bus_map_in(int * idx)409 ob_pci_bus_map_in(int *idx)
410 {
411 uint32_t ba;
412 ucell size;
413 ucell virt;
414
415 PCI_DPRINTF("ob_pci_bar_map_in idx=%p\n", idx);
416
417 size = POP();
418 POP();
419 POP();
420 ba = POP();
421
422 virt = ob_pci_map(ba, size);
423
424 PUSH(virt);
425 }
426
427 static void
ob_pci_dma_alloc(int * idx)428 ob_pci_dma_alloc(int *idx)
429 {
430 call_parent_method("dma-alloc");
431 }
432
433 static void
ob_pci_dma_free(int * idx)434 ob_pci_dma_free(int *idx)
435 {
436 call_parent_method("dma-free");
437 }
438
439 static void
ob_pci_dma_map_in(int * idx)440 ob_pci_dma_map_in(int *idx)
441 {
442 call_parent_method("dma-map-in");
443 }
444
445 static void
ob_pci_dma_map_out(int * idx)446 ob_pci_dma_map_out(int *idx)
447 {
448 call_parent_method("dma-map-out");
449 }
450
451 static void
ob_pci_dma_sync(int * idx)452 ob_pci_dma_sync(int *idx)
453 {
454 call_parent_method("dma-sync");
455 }
456
457 NODE_METHODS(ob_pci_bus_node) = {
458 { "open", ob_pci_open },
459 { "close", ob_pci_close },
460 { "decode-unit", ob_pci_decode_unit },
461 { "encode-unit", ob_pci_encode_unit },
462 { "pci-map-in", ob_pci_bus_map_in },
463 { "dma-alloc", ob_pci_dma_alloc },
464 { "dma-free", ob_pci_dma_free },
465 { "dma-map-in", ob_pci_dma_map_in },
466 { "dma-map-out", ob_pci_dma_map_out },
467 { "dma-sync", ob_pci_dma_sync },
468 };
469
470 /* ( pci-addr.lo pci-addr.mid pci-addr.hi size -- virt ) */
471
472 static void
ob_pci_bridge_map_in(int * idx)473 ob_pci_bridge_map_in(int *idx)
474 {
475 /* As per the IEEE-1275 PCI specification, chain up to the parent */
476 call_parent_method("pci-map-in");
477 }
478
479 NODE_METHODS(ob_pci_bridge_node) = {
480 { "open", ob_pci_open },
481 { "close", ob_pci_close },
482 { "decode-unit", ob_pci_decode_unit },
483 { "encode-unit", ob_pci_encode_unit },
484 { "pci-map-in", ob_pci_bridge_map_in },
485 { "dma-alloc", ob_pci_dma_alloc },
486 { "dma-free", ob_pci_dma_free },
487 { "dma-map-in", ob_pci_dma_map_in },
488 { "dma-map-out", ob_pci_dma_map_out },
489 { "dma-sync", ob_pci_dma_sync },
490 };
491
492 NODE_METHODS(ob_pci_simple_node) = {
493 { "open", ob_pci_open },
494 { "close", ob_pci_close },
495 };
496
pci_set_bus_range(const pci_config_t * config)497 static void pci_set_bus_range(const pci_config_t *config)
498 {
499 phandle_t dev = find_dev(config->path);
500 u32 props[2];
501
502 props[0] = config->secondary_bus;
503 props[1] = config->subordinate_bus;
504
505 PCI_DPRINTF("setting bus range for %s PCI device, "
506 "package handle " FMT_ucellx " "
507 "bus primary=%d secondary=%d subordinate=%d\n",
508 config->path,
509 dev,
510 config->primary_bus,
511 config->secondary_bus,
512 config->subordinate_bus);
513
514
515 set_property(dev, "bus-range", (char *)props, 2 * sizeof(props[0]));
516 }
517
518 static void ob_pci_reload_device_path(phandle_t phandle, pci_config_t *config);
519
pci_host_set_reg(phandle_t phandle,pci_config_t * config)520 static void pci_host_set_reg(phandle_t phandle, pci_config_t *config)
521 {
522 phandle_t dev = phandle;
523
524 /* at most 2 integers for address and size */
525 u32 props[4];
526 int ncells = 0;
527
528 ncells += encode_int32_cells(host_address_cells(), props + ncells,
529 arch->cfg_base);
530
531 ncells += encode_int32_cells(host_size_cells(), props + ncells,
532 arch->cfg_len);
533
534 set_property(dev, "reg", (char *)props, ncells * sizeof(props[0]));
535
536 ob_pci_reload_device_path(dev, config);
537
538 #if defined(CONFIG_DEBUG_PCI)
539 dump_reg_property("pci_host_set_reg", 4, props);
540 #endif
541 }
542
543 /* child-phys : parent-phys : size */
544 /* 3 cells for PCI : 2 cells for 64bit parent : 2 cells for PCI */
545
pci_host_set_ranges(const pci_config_t * config)546 static void pci_host_set_ranges(const pci_config_t *config)
547 {
548 phandle_t dev = get_cur_dev();
549 u32 props[32];
550 int ncells = 0;
551 pci_range_t range;
552 int i;
553
554 for (i = 0; i < 4; i++) {
555 range = arch->host_ranges[i];
556
557 /* End of range list reached */
558 if (range.type == 0x0 && range.len == 0x0) {
559 break;
560 }
561
562 ncells += pci_encode_phys_addr(props + ncells, 0, range.type,
563 0, 0, range.parentaddr);
564 ncells += host_encode_phys_addr(props + ncells, range.childaddr);
565 ncells += pci_encode_size(props + ncells, range.len);
566 }
567
568 set_property(dev, "ranges", (char *)props, ncells * sizeof(props[0]));
569 }
570
host_config_cb(const pci_config_t * config)571 int host_config_cb(const pci_config_t *config)
572 {
573 pci_host_set_ranges(config);
574
575 return 0;
576 }
577
sabre_configure(phandle_t dev)578 static int sabre_configure(phandle_t dev)
579 {
580 uint32_t props[28];
581
582 /* Sabre has a custom reg property from the default */
583 props[0] = 0x1fe;
584 props[1] = 0x0;
585 props[2] = 0x0;
586 props[3] = 0x10000;
587 props[4] = 0x1fe;
588 props[5] = 0x1000000;
589 props[6] = 0x0;
590 props[7] = 0x100;
591 set_property(dev, "reg", (char *)props, 8 * sizeof(props[0]));
592
593 props[0] = 0xc0000000;
594 props[1] = 0x20000000;
595 set_property(dev, "virtual-dma", (char *)props, 2 * sizeof(props[0]));
596 props[0] = 1;
597 set_property(dev, "#virtual-dma-size-cells", (char *)props,
598 sizeof(props[0]));
599 set_property(dev, "#virtual-dma-addr-cells", (char *)props,
600 sizeof(props[0]));
601
602 set_property(dev, "no-streaming-cache", (char *)props, 0);
603
604 props[0] = 0x000007f0;
605 props[1] = 0x000007ee;
606 props[2] = 0x000007ef;
607 props[3] = 0x000007e5;
608 set_property(dev, "interrupts", (char *)props, 4 * sizeof(props[0]));
609 props[0] = 0x0000001f;
610 set_property(dev, "upa-portid", (char *)props, 1 * sizeof(props[0]));
611 return 0;
612 }
613
sabre_config_cb(const pci_config_t * config)614 int sabre_config_cb(const pci_config_t *config)
615 {
616 host_config_cb(config);
617
618 return sabre_configure(get_cur_dev());
619 }
620
bridge_config_cb(const pci_config_t * config)621 int bridge_config_cb(const pci_config_t *config)
622 {
623 phandle_t aliases;
624
625 aliases = find_dev("/aliases");
626 set_property(aliases, "bridge", config->path, strlen(config->path) + 1);
627
628 return 0;
629 }
630
simba_config_cb(const pci_config_t * config)631 int simba_config_cb(const pci_config_t *config)
632 {
633 u32 props[128];
634 int ncells = 0;
635
636 bridge_config_cb(config);
637
638 /* Configure the simba ranges as per the mostly undocumented
639 PCI config register in Linux's apb_fake_ranges():
640
641 pci@1,1 (pciA):
642 IO: 0x1fe02000000-0x1fe027fffff
643 MEM: 0x1ff20000000-0x1ff5fffffff
644
645 pci@1 (pciB):
646 IO: 0x1fe02800000-0x1fe02ffffff
647 MEM: 0x1ff60000000-0x1ff9fffffff
648 */
649
650 switch (PCI_FN(config->dev)) {
651 case 1:
652 /* IO: 0x1fe02000000-0x1fe027fffff */
653 pci_config_write8(config->dev, 0xde, 0x0f);
654
655 /* MEM: 0x1ff20000000-0x1ff5fffffff */
656 pci_config_write8(config->dev, 0xdf, 0x06);
657
658 /* Onboard NIC: slot 1, intno 0x21 */
659 ncells += pci_encode_phys_addr(props + ncells, 0, 0, PCI_ADDR(1, 1, 0), 0, 0);
660 props[ncells++] = 0x1;
661 props[ncells++] = find_dev("/pci");
662 props[ncells++] = 0x21;
663
664 /* Onboard IDE: slot 3, intno 0x20 */
665 ncells += pci_encode_phys_addr(props + ncells, 0, 0, PCI_ADDR(1, 3, 0), 0, 0);
666 props[ncells++] = 0x1;
667 props[ncells++] = find_dev("/pci");
668 props[ncells++] = 0x20;
669 set_property(get_cur_dev(), "interrupt-map", (char *)props, ncells * sizeof(props[0]));
670
671 props[0] = 0x00fff800;
672 props[1] = 0x0;
673 props[2] = 0x0;
674 props[3] = 0x7;
675 set_property(get_cur_dev(), "interrupt-map-mask", (char *)props, 4 * sizeof(props[0]));
676 break;
677
678 case 0:
679 /* IO: 0x1fe02800000-0x1fe02ffffff */
680 pci_config_write8(config->dev, 0xde, 0xf0);
681
682 /* MEM: 0x1ff60000000-0x1ff9fffffff */
683 pci_config_write8(config->dev, 0xdf, 0x18);
684 break;
685 }
686
687 return 0;
688 }
689
ide_config_cb2(const pci_config_t * config)690 int ide_config_cb2 (const pci_config_t *config)
691 {
692 ob_ide_init(config->path,
693 config->assigned[0] & ~0x0000000F,
694 (config->assigned[1] & ~0x0000000F) + 2,
695 config->assigned[2] & ~0x0000000F,
696 (config->assigned[3] & ~0x0000000F) + 2);
697 return 0;
698 }
699
eth_config_cb(const pci_config_t * config)700 int eth_config_cb (const pci_config_t *config)
701 {
702 phandle_t ph = get_cur_dev();
703
704 set_property(ph, "network-type", "ethernet", 9);
705 set_property(ph, "removable", "network", 8);
706 set_property(ph, "category", "net", 4);
707
708 return 0;
709 }
710
sunhme_config_cb(const pci_config_t * config)711 int sunhme_config_cb(const pci_config_t *config)
712 {
713 phandle_t ph = get_cur_dev();
714
715 set_int_property(ph, "hm-rev", 0x21);
716
717 return eth_config_cb(config);
718 }
719
rtl8139_config_cb(const pci_config_t * config)720 int rtl8139_config_cb(const pci_config_t *config)
721 {
722 #ifdef CONFIG_PPC
723 /* Apple's OF seemingly enables bus mastering on some cards by
724 * default, which means that some buggy drivers forget to
725 * explicitly set it (OS X, MorphOS). Mimic this behaviour so
726 * that these buggy drivers work under emulation. */
727 if (is_apple()) {
728 ob_pci_enable_bus_master(config);
729 }
730 #endif
731
732 return eth_config_cb(config);
733 }
734
sungem_config_cb(const pci_config_t * config)735 int sungem_config_cb (const pci_config_t *config)
736 {
737 phandle_t ph = get_cur_dev();
738 uint32_t val, *mmio;
739 uint8_t mac[6];
740 ucell virt;
741
742 #define MAC_ADDR0 (0x6080UL/4) /* MAC Address 0 Register */
743 #define MAC_ADDR1 (0x6084UL/4) /* MAC Address 1 Register */
744 #define MAC_ADDR2 (0x6088UL/4) /* MAC Address 2 Register */
745
746 /* Map PCI memory BAR 0 to access the sungem registers */
747 virt = ob_pci_map(config->assigned[0], 0x8000);
748 mmio = (void *)(uintptr_t)virt;
749
750 val = __le32_to_cpu(*(mmio + MAC_ADDR0));
751 mac[5] = val & 0xff;
752 mac[4] = (val >> 8) & 0xff;
753 val = __le32_to_cpu(*(mmio + MAC_ADDR1));
754 mac[3] = val & 0xff;
755 mac[2] = (val >> 8) & 0xff;
756 val = __le32_to_cpu(*(mmio + MAC_ADDR2));
757 mac[1] = val & 0xff;
758 mac[0] = (val >> 8) & 0xff;
759 set_property(ph, "local-mac-address", (char *)mac, 6);
760
761 ob_pci_unmap(virt, 0x8000);
762 return 0;
763 }
764
virtio_blk_config_cb(const pci_config_t * config)765 int virtio_blk_config_cb(const pci_config_t *config)
766 {
767 #ifdef CONFIG_DRIVER_VIRTIO_BLK
768 pci_addr addr;
769 uint8_t idx, cap_idx, cap_vndr;
770 uint8_t cfg_type, bar;
771 uint16_t status;
772 uint32_t offset, notify_mult = 0;
773 uint64_t common_cfg = 0, device_cfg = 0, notify_base = 0;
774
775 addr = PCI_ADDR(
776 PCI_BUS(config->dev),
777 PCI_DEV(config->dev),
778 PCI_FN(config->dev));
779
780 idx = (uint8_t)(pci_config_read16(addr, PCI_DEVICE_ID) & 0xff) - 1;
781
782 /* Check PCI capabilties: if they don't exist then we're certainly not
783 a 1.0 device */
784 status = pci_config_read16(addr, PCI_STATUS);
785 if (!(status & PCI_STATUS_CAP_LIST)) {
786 return 0;
787 }
788
789 /* Locate VIRTIO_PCI_CAP_COMMON_CFG and VIRTIO_PCI_CAP_DEVICE_CFG */
790 cap_idx = pci_config_read8(addr, PCI_CAPABILITY_LIST);
791 while ((cap_vndr = pci_config_read8(addr, cap_idx)) != 0) {
792 if (cap_vndr == PCI_CAP_ID_VNDR) {
793 cfg_type = pci_config_read8(addr, cap_idx + 0x3);
794 bar = pci_config_read8(addr, cap_idx + 0x4);
795 offset = pci_config_read32(addr, cap_idx + 0x8);
796
797 switch (cfg_type) {
798 case VIRTIO_PCI_CAP_COMMON_CFG:
799 common_cfg = arch->host_pci_base + (config->assigned[bar] & ~0x0000000F) + offset;
800 break;
801 case VIRTIO_PCI_CAP_NOTIFY_CFG:
802 notify_base = arch->host_pci_base + (config->assigned[bar] & ~0x0000000F) + offset;
803 notify_mult = pci_config_read32(addr, cap_idx + 16);
804 break;
805 case VIRTIO_PCI_CAP_DEVICE_CFG:
806 device_cfg = arch->host_pci_base + (config->assigned[bar] & ~0x0000000F) + offset;
807 break;
808 }
809 }
810
811 cap_idx = pci_config_read8(addr, cap_idx + 1);
812 }
813
814 /* If we didn't find the required configuration then exit */
815 if (common_cfg == 0 || device_cfg == 0 || notify_base == 0) {
816 return 0;
817 }
818
819 ob_virtio_init(config->path, "virtio-blk", common_cfg, device_cfg,
820 notify_base, notify_mult, idx);
821 #endif
822 return 0;
823 }
824
825 /*
826 * "Designing PCI Cards and Drivers for Power Macintosh Computers", p. 454
827 *
828 * "AAPL,address" provides an array of 32-bit logical addresses
829 * Nth entry corresponding to Nth "assigned-address" base address entry.
830 */
831
pci_set_AAPL_address(const pci_config_t * config)832 static void pci_set_AAPL_address(const pci_config_t *config)
833 {
834 phandle_t dev = get_cur_dev();
835 cell props[7];
836 uint32_t mask;
837 int ncells, i, flags, space_code;
838
839 ncells = 0;
840 for (i = 0; i < 6; i++) {
841 if (!config->assigned[i] || !config->sizes[i])
842 continue;
843 pci_decode_pci_addr(config->assigned[i],
844 &flags, &space_code, &mask);
845
846 props[ncells++] = pci_bus_addr_to_host_addr(space_code,
847 config->assigned[i] & ~mask);
848 }
849 if (ncells)
850 set_property(dev, "AAPL,address", (char *)props,
851 ncells * sizeof(cell));
852 }
853
pci_set_assigned_addresses(phandle_t phandle,const pci_config_t * config,int num_bars)854 static void pci_set_assigned_addresses(phandle_t phandle,
855 const pci_config_t *config, int num_bars)
856 {
857 phandle_t dev = phandle;
858 u32 props[32];
859 int ncells;
860 int i;
861 uint32_t mask;
862 int flags, space_code;
863
864 ncells = 0;
865 for (i = 0; i < num_bars; i++) {
866 /* consider only bars with non-zero region size */
867 if (!config->sizes[i])
868 continue;
869 pci_decode_pci_addr(config->assigned[i],
870 &flags, &space_code, &mask);
871
872 ncells += pci_encode_phys_addr(props + ncells,
873 flags, space_code, config->dev,
874 PCI_BASE_ADDR_0 + (i * sizeof(uint32_t)),
875 config->assigned[i] & ~mask);
876
877 props[ncells++] = 0x00000000;
878 props[ncells++] = config->sizes[i];
879 }
880 if (ncells)
881 set_property(dev, "assigned-addresses", (char *)props,
882 ncells * sizeof(props[0]));
883 }
884
885 /* call after writing "reg" property to update config->path */
ob_pci_reload_device_path(phandle_t phandle,pci_config_t * config)886 static void ob_pci_reload_device_path(phandle_t phandle, pci_config_t *config)
887 {
888 /* since "name" and "reg" are now assigned
889 we need to reload current node name */
890 char *new_path = get_path_from_ph(phandle);
891 if (new_path) {
892 if (0 != strcmp(config->path, new_path)) {
893 PCI_DPRINTF("\n=== CHANGED === package path old=%s new=%s\n",
894 config->path, new_path);
895 strncpy(config->path, new_path, sizeof(config->path));
896 config->path[sizeof(config->path)-1] = '\0';
897 }
898 free(new_path);
899 } else {
900 PCI_DPRINTF("\n=== package path old=%s new=NULL\n", config->path);
901 }
902 }
903
pci_set_reg(phandle_t phandle,pci_config_t * config,int num_bars)904 static void pci_set_reg(phandle_t phandle,
905 pci_config_t *config, int num_bars)
906 {
907 phandle_t dev = phandle;
908 u32 props[38];
909 int ncells;
910 int i;
911 uint32_t mask;
912 int space_code, flags;
913
914 ncells = 0;
915
916 /* first (addr, size) pair is the beginning of configuration address space */
917 ncells += pci_encode_phys_addr(props + ncells, 0, CONFIGURATION_SPACE,
918 config->dev, 0, 0);
919
920 ncells += pci_encode_size(props + ncells, 0);
921
922 for (i = 0; i < num_bars; i++) {
923 /* consider only bars with non-zero region size */
924 if (!config->sizes[i])
925 continue;
926
927 pci_decode_pci_addr(config->regions[i],
928 &flags, &space_code, &mask);
929
930 ncells += pci_encode_phys_addr(props + ncells,
931 flags, space_code, config->dev,
932 PCI_BASE_ADDR_0 + (i * sizeof(uint32_t)),
933 config->regions[i] & ~mask);
934
935 /* set size */
936 ncells += pci_encode_size(props + ncells, config->sizes[i]);
937 }
938
939 set_property(dev, "reg", (char *)props, ncells * sizeof(props[0]));
940 ob_pci_reload_device_path(dev, config);
941
942 #if defined(CONFIG_DEBUG_PCI)
943 dump_reg_property("pci_set_reg", ncells, props);
944 #endif
945 }
946
947
pci_set_ranges(const pci_config_t * config)948 static void pci_set_ranges(const pci_config_t *config)
949 {
950 phandle_t dev = get_cur_dev();
951 u32 props[32];
952 int ncells;
953 int i;
954 uint32_t mask;
955 int flags;
956 int space_code;
957
958 ncells = 0;
959 for (i = 0; i < 6; i++) {
960 if (!config->assigned[i] || !config->sizes[i])
961 continue;
962
963 /* child address */
964
965 props[ncells++] = 0x00000000;
966
967 /* parent address */
968
969 pci_decode_pci_addr(config->assigned[i],
970 &flags, &space_code, &mask);
971 ncells += pci_encode_phys_addr(props + ncells, flags, space_code,
972 config->dev, 0x10 + i * 4,
973 config->assigned[i] & ~mask);
974
975 /* size */
976
977 props[ncells++] = config->sizes[i];
978 }
979 set_property(dev, "ranges", (char *)props, ncells * sizeof(props[0]));
980 }
981
macio_heathrow_config_cb(const pci_config_t * config)982 int macio_heathrow_config_cb (const pci_config_t *config)
983 {
984 pci_set_ranges(config);
985
986 #ifdef CONFIG_DRIVER_MACIO
987 ob_macio_heathrow_init(config->path, config->assigned[0] & ~0x0000000F);
988 #endif
989 return 0;
990 }
991
macio_keylargo_config_cb(const pci_config_t * config)992 int macio_keylargo_config_cb (const pci_config_t *config)
993 {
994 pci_set_ranges(config);
995
996 #ifdef CONFIG_DRIVER_MACIO
997 ob_macio_keylargo_init(config->path, config->assigned[0] & ~0x0000000F);
998 #endif
999 return 0;
1000 }
1001
vga_config_cb(const pci_config_t * config)1002 int vga_config_cb (const pci_config_t *config)
1003 {
1004 #ifdef CONFIG_PPC
1005 unsigned long rom;
1006 uint32_t rom_size, size, bar;
1007 phandle_t ph;
1008 #endif
1009 if (config->assigned[0] != 0x00000000) {
1010 setup_video();
1011
1012 #ifdef CONFIG_PPC
1013 if (config->assigned[6]) {
1014 rom = pci_bus_addr_to_host_addr(MEMORY_SPACE_32,
1015 config->assigned[6] & ~0x0000000F);
1016 rom_size = config->sizes[6];
1017
1018 bar = pci_config_read32(config->dev, PCI_ROM_ADDRESS);
1019 bar |= PCI_ROM_ADDRESS_ENABLE;
1020 pci_config_write32(config->dev, PCI_COMMAND, bar);
1021 ph = get_cur_dev();
1022
1023 if (rom_size >= 8) {
1024 const char *p;
1025
1026 p = (const char *)rom;
1027 if (p[0] == 'N' && p[1] == 'D' && p[2] == 'R' && p[3] == 'V') {
1028 size = *(uint32_t*)(p + 4);
1029 set_property(ph, "driver,AAPL,MacOS,PowerPC",
1030 p + 8, size);
1031 } else if (p[0] == 'J' && p[1] == 'o' &&
1032 p[2] == 'y' && p[3] == '!') {
1033 set_property(ph, "driver,AAPL,MacOS,PowerPC",
1034 p, rom_size);
1035 }
1036 }
1037 }
1038 #endif
1039
1040 /* Currently we don't read FCode from the hardware but execute
1041 * it directly */
1042 feval("['] vga-driver-fcode 2 cells + 1 byte-load");
1043
1044 #ifdef CONFIG_MOL
1045 /* Install special words for Mac On Linux */
1046 molvideo_init();
1047 #endif
1048 }
1049
1050 return 0;
1051 }
1052
ebus_config_cb(const pci_config_t * config)1053 int ebus_config_cb(const pci_config_t *config)
1054 {
1055 #ifdef CONFIG_DRIVER_EBUS
1056 phandle_t dev = get_cur_dev();
1057 uint32_t props[12];
1058 int ncells;
1059 int i;
1060 uint32_t mask;
1061 int flags, space_code;
1062 ucell virt;
1063 phys_addr_t io_phys_base = 0;
1064
1065 /* Serial */
1066 props[0] = 0x14;
1067 props[1] = 0x3f8;
1068 props[2] = 1;
1069 props[3] = find_dev("/pci");
1070 props[4] = 0x2b;
1071
1072 /* PS2 keyboard */
1073 props[5] = 0x14;
1074 props[6] = 0x60;
1075 props[7] = 1;
1076 props[8] = find_dev("/pci");
1077 props[9] = 0x29;
1078
1079 set_property(dev, "interrupt-map", (char *)props, 10 * sizeof(props[0]));
1080
1081 props[0] = 0x000001ff;
1082 props[1] = 0xffffffff;
1083 props[2] = 3;
1084 set_property(dev, "interrupt-map-mask", (char *)props, 3 * sizeof(props[0]));
1085
1086 /* Build ranges property from the BARs */
1087 ncells = 0;
1088 for (i = 0; i < 6; i++) {
1089 /* consider only bars with non-zero region size */
1090 if (!config->sizes[i])
1091 continue;
1092
1093 pci_decode_pci_addr(config->assigned[i],
1094 &flags, &space_code, &mask);
1095
1096 props[ncells++] = PCI_BASE_ADDR_0 + (i * sizeof(uint32_t));
1097 props[ncells++] = 0x0;
1098
1099 ncells += pci_encode_phys_addr(props + ncells,
1100 flags, space_code, config->dev,
1101 PCI_BASE_ADDR_0 + (i * sizeof(uint32_t)),
1102 config->assigned[i] & ~mask);
1103
1104 props[ncells++] = config->sizes[i];
1105
1106 /* Store base of IO space for NVRAM */
1107 if (io_phys_base == 0x0 && space_code == IO_SPACE) {
1108 io_phys_base = pci_bus_addr_to_host_addr(space_code, config->assigned[i] & ~mask);
1109 }
1110 }
1111
1112 set_property(dev, "ranges", (char *)props, ncells * sizeof(props[0]));
1113
1114 /* Build eeprom node */
1115 fword("new-device");
1116 PUSH(0x14);
1117 fword("encode-int");
1118 PUSH(0x2000);
1119 fword("encode-int");
1120 fword("encode+");
1121 PUSH(0x2000);
1122 fword("encode-int");
1123 fword("encode+");
1124 push_str("reg");
1125 fword("property");
1126
1127 push_str("mk48t59");
1128 fword("model");
1129
1130 /* OpenSolaris (e.g. Milax) requires the RTC to be pre-mapped by the PROM */
1131 virt = ofmem_map_io(io_phys_base + 0x2000, 0x2000);
1132 PUSH(virt);
1133 fword("encode-int");
1134 push_str("address");
1135 fword("property");
1136
1137 push_str("eeprom");
1138 fword("device-name");
1139 fword("finish-device");
1140
1141 /* Build power node */
1142 fword("new-device");
1143 PUSH(0x14);
1144 fword("encode-int");
1145 PUSH(0x7240);
1146 fword("encode-int");
1147 fword("encode+");
1148 PUSH(0x4);
1149 fword("encode-int");
1150 fword("encode+");
1151 push_str("reg");
1152 fword("property");
1153
1154 PUSH(0);
1155 PUSH(0);
1156 push_str("button");
1157 fword("property");
1158
1159 PUSH(1);
1160 fword("encode-int");
1161 push_str("interrupts");
1162 fword("property");
1163
1164 /* Map the power registers so we can use them */
1165 virt = ofmem_map_io(io_phys_base + 0x7240, 0x4);
1166 PUSH(virt);
1167 fword("encode-int");
1168 push_str("address");
1169 fword("property");
1170
1171 push_str("power");
1172 fword("device-name");
1173 fword("finish-device");
1174
1175 #ifdef CONFIG_DRIVER_FLOPPY
1176 ob_floppy_init(config->path, "fdthree", 0x3f0ULL, 0);
1177 #endif
1178 #ifdef CONFIG_DRIVER_PC_SERIAL
1179 ob_pc_serial_init(config->path, "su", (PCI_BASE_ADDR_1 | 0ULL) << 32, 0x3f8ULL, 0);
1180 #endif
1181 #ifdef CONFIG_DRIVER_PC_KBD
1182 ob_pc_kbd_init(config->path, "kb_ps2", NULL, (PCI_BASE_ADDR_1 | 0ULL) << 32, 0x60ULL, 1, 0);
1183 #endif
1184 #endif
1185 return 0;
1186 }
1187
i82378_config_cb(const pci_config_t * config)1188 int i82378_config_cb(const pci_config_t *config)
1189 {
1190 #ifdef CONFIG_DRIVER_PC_SERIAL
1191 ob_pc_serial_init(config->path, "serial", arch->io_base, 0x3f8ULL, 0);
1192 #endif
1193 #ifdef CONFIG_DRIVER_PC_KBD
1194 ob_pc_kbd_init(config->path, "keyboard", NULL, arch->io_base, 0x60ULL, 0, 0);
1195 #endif
1196 #ifdef CONFIG_DRIVER_IDE
1197 ob_ide_init(config->path, 0x1f0, 0x3f6, 0x170, 0x376);
1198 #endif
1199
1200 return 0;
1201 }
1202
usb_ohci_config_cb(const pci_config_t * config)1203 int usb_ohci_config_cb(const pci_config_t *config)
1204 {
1205 #ifdef CONFIG_DRIVER_USB
1206 pci_addr addr = PCI_ADDR(
1207 PCI_BUS(config->dev), PCI_DEV(config->dev), PCI_FN(config->dev));
1208
1209 ob_usb_ohci_init(config->path, addr);
1210 #endif
1211 return 0;
1212 }
1213
lsi53c810_config_cb(const pci_config_t * config)1214 int lsi53c810_config_cb(const pci_config_t *config)
1215 {
1216 #ifdef CONFIG_DRIVER_LSI_53C810
1217 uint64_t mmio, ram;
1218
1219 /* Enable PCI bus mastering */
1220 ob_pci_enable_bus_master(config);
1221
1222 /* Map PCI memory BAR 1: LSI MMIO */
1223 mmio = ob_pci_map(config->assigned[1], 0x400);
1224
1225 /* Map PCI memory BAR 2: LSI RAM */
1226 ram = ob_pci_map(config->assigned[2], 0x400);
1227
1228 ob_lsi_init(config->path, mmio, ram);
1229 #endif
1230 return 0;
1231 }
1232
ob_pci_enable_bus_master(const pci_config_t * config)1233 void ob_pci_enable_bus_master(const pci_config_t *config)
1234 {
1235 /* Enable bus mastering for the PCI device */
1236 uint16_t cmd;
1237 pci_addr addr = PCI_ADDR(
1238 PCI_BUS(config->dev), PCI_DEV(config->dev), PCI_FN(config->dev));
1239
1240 cmd = pci_config_read16(addr, PCI_COMMAND);
1241 cmd |= PCI_COMMAND_BUS_MASTER;
1242 pci_config_write16(addr, PCI_COMMAND, cmd);
1243 }
1244
ob_pci_add_properties(phandle_t phandle,pci_addr addr,const pci_dev_t * pci_dev,const pci_config_t * config,int num_bars)1245 static void ob_pci_add_properties(phandle_t phandle,
1246 pci_addr addr, const pci_dev_t *pci_dev,
1247 const pci_config_t *config, int num_bars)
1248 {
1249 /* cannot use get_cur_dev() path resolution since "name" and "reg"
1250 properties are being changed */
1251 phandle_t dev=phandle;
1252 int status,id;
1253 uint16_t vendor_id, device_id;
1254 uint8_t rev;
1255 uint8_t class_prog;
1256 uint32_t class_code;
1257 char path[256];
1258
1259 vendor_id = pci_config_read16(addr, PCI_VENDOR_ID);
1260 device_id = pci_config_read16(addr, PCI_DEVICE_ID);
1261 rev = pci_config_read8(addr, PCI_REVISION_ID);
1262 class_prog = pci_config_read8(addr, PCI_CLASS_PROG);
1263 class_code = pci_config_read16(addr, PCI_CLASS_DEVICE);
1264
1265 /* Default path if we don't match anything */
1266 snprintf(path, sizeof(path), "pci%x,%x", vendor_id, device_id);
1267
1268 if (pci_dev) {
1269 /**/
1270 if (pci_dev->name) {
1271 push_str(pci_dev->name);
1272 fword("device-name");
1273 } else {
1274 push_str(path);
1275 fword("device-name");
1276 }
1277 } else {
1278 PCI_DPRINTF("*** missing pci_dev\n");
1279 push_str(path);
1280 fword("device-name");
1281 }
1282
1283 /* create properties as described in 2.5 */
1284
1285 set_int_property(dev, "vendor-id", vendor_id);
1286 set_int_property(dev, "device-id", device_id);
1287 set_int_property(dev, "revision-id", rev);
1288 set_int_property(dev, "class-code", class_code << 8 | class_prog);
1289
1290 if (config->irq_pin) {
1291 if (is_oldworld()) {
1292 set_int_property(dev, "AAPL,interrupts", config->irq_line);
1293 } else {
1294 set_int_property(dev, "interrupts", config->irq_pin);
1295 }
1296 }
1297
1298 set_int_property(dev, "min-grant", pci_config_read8(addr, PCI_MIN_GNT));
1299 set_int_property(dev, "max-latency", pci_config_read8(addr, PCI_MAX_LAT));
1300
1301 status=pci_config_read16(addr, PCI_STATUS);
1302
1303 set_int_property(dev, "devsel-speed",
1304 (status&PCI_STATUS_DEVSEL_MASK)>>10);
1305
1306 if(status&PCI_STATUS_FAST_BACK)
1307 set_bool_property(dev, "fast-back-to-back");
1308 if(status&PCI_STATUS_66MHZ)
1309 set_bool_property(dev, "66mhz-capable");
1310 if(status&PCI_STATUS_UDF)
1311 set_bool_property(dev, "udf-supported");
1312
1313 id=pci_config_read16(addr, PCI_SUBSYSTEM_VENDOR_ID);
1314 if(id)
1315 set_int_property(dev, "subsystem-vendor-id", id);
1316 id=pci_config_read16(addr, PCI_SUBSYSTEM_ID);
1317 if(id)
1318 set_int_property(dev, "subsystem-id", id);
1319
1320 set_int_property(dev, "cache-line-size",
1321 pci_config_read16(addr, PCI_CACHE_LINE_SIZE));
1322
1323 if (pci_dev) {
1324 if (pci_dev->type) {
1325 push_str(pci_dev->type);
1326 fword("device-type");
1327 }
1328 if (pci_dev->model) {
1329 push_str(pci_dev->model);
1330 fword("model");
1331 }
1332 if (pci_dev->compat)
1333 set_property(dev, "compatible",
1334 pci_dev->compat, pci_compat_len(pci_dev));
1335
1336 if (pci_dev->acells)
1337 set_int_property(dev, "#address-cells",
1338 pci_dev->acells);
1339 if (pci_dev->scells)
1340 set_int_property(dev, "#size-cells",
1341 pci_dev->scells);
1342 if (pci_dev->icells)
1343 set_int_property(dev, "#interrupt-cells",
1344 pci_dev->icells);
1345 }
1346
1347 pci_set_assigned_addresses(phandle, config, num_bars);
1348
1349 if (is_apple() && is_oldworld())
1350 pci_set_AAPL_address(config);
1351
1352 PCI_DPRINTF("\n");
1353 }
1354
1355 #ifdef CONFIG_XBOX
pci_xbox_blacklisted(int bus,int devnum,int fn)1356 static char pci_xbox_blacklisted (int bus, int devnum, int fn)
1357 {
1358 /*
1359 * The Xbox MCPX chipset is a derivative of the nForce 1
1360 * chipset. It almost has the same bus layout; some devices
1361 * cannot be used, because they have been removed.
1362 */
1363
1364 /*
1365 * Devices 00:00.1 and 00:00.2 used to be memory controllers on
1366 * the nForce chipset, but on the Xbox, using them will lockup
1367 * the chipset.
1368 */
1369 if ((bus == 0) && (devnum == 0) && ((fn == 1) || (fn == 2)))
1370 return 1;
1371
1372 /*
1373 * Bus 1 only contains a VGA controller at 01:00.0. When you try
1374 * to probe beyond that device, you only get garbage, which
1375 * could cause lockups.
1376 */
1377 if ((bus == 1) && ((devnum != 0) || (fn != 0)))
1378 return 1;
1379
1380 /*
1381 * Bus 2 used to contain the AGP controller, but the Xbox MCPX
1382 * doesn't have one. Probing it can cause lockups.
1383 */
1384 if (bus >= 2)
1385 return 1;
1386
1387 /*
1388 * The device is not blacklisted.
1389 */
1390 return 0;
1391 }
1392 #endif
1393
ob_pci_configure_bar(pci_addr addr,pci_config_t * config,int reg,int config_addr,uint32_t * p_omask,unsigned long * mem_base,unsigned long * io_base)1394 static void ob_pci_configure_bar(pci_addr addr, pci_config_t *config,
1395 int reg, int config_addr,
1396 uint32_t *p_omask,
1397 unsigned long *mem_base,
1398 unsigned long *io_base)
1399 {
1400 uint32_t smask, amask, size, reloc, min_align;
1401 unsigned long base;
1402
1403 config->assigned[reg] = 0x00000000;
1404 config->sizes[reg] = 0x00000000;
1405
1406 if ((*p_omask & 0x0000000f) == 0x4) {
1407 /* 64 bits memory mapping */
1408 PCI_DPRINTF("Skipping 64 bit BARs for %s\n", config->path);
1409 return;
1410 }
1411
1412 config->regions[reg] = pci_config_read32(addr, config_addr);
1413
1414 /* get region size */
1415
1416 pci_config_write32(addr, config_addr, 0xffffffff);
1417 smask = pci_config_read32(addr, config_addr);
1418 if (smask == 0x00000000 || smask == 0xffffffff)
1419 return;
1420
1421 if (smask & 0x00000001 && reg != 6) {
1422 /* I/O space */
1423 base = *io_base;
1424 min_align = 1 << 7;
1425 amask = 0x00000001;
1426 } else {
1427 /* Memory Space */
1428 base = *mem_base;
1429 min_align = 1 << 16;
1430 amask = 0x0000000F;
1431 if (reg == 6) {
1432 smask |= 1; /* ROM */
1433 }
1434 }
1435 *p_omask = smask & amask;
1436 smask &= ~amask;
1437 size = (~smask) + 1;
1438 config->sizes[reg] = size;
1439 reloc = base;
1440 if (size < min_align)
1441 size = min_align;
1442 reloc = (reloc + size -1) & ~(size - 1);
1443 if (*io_base == base) {
1444 PCI_DPRINTF("changing io_base from 0x%lx to 0x%x\n",
1445 *io_base, reloc + size);
1446 *io_base = reloc + size;
1447 } else {
1448 PCI_DPRINTF("changing mem_base from 0x%lx to 0x%x\n",
1449 *mem_base, reloc + size);
1450 *mem_base = reloc + size;
1451 }
1452 PCI_DPRINTF("Configuring BARs for %s: reloc 0x%x omask 0x%x "
1453 "io_base 0x%lx mem_base 0x%lx size 0x%x\n",
1454 config->path, reloc, *p_omask, *io_base, *mem_base, size);
1455 pci_config_write32(addr, config_addr, reloc | *p_omask);
1456 config->assigned[reg] = reloc | *p_omask;
1457 }
1458
ob_pci_configure_irq(pci_addr addr,pci_config_t * config)1459 static void ob_pci_configure_irq(pci_addr addr, pci_config_t *config)
1460 {
1461 uint8_t irq_pin, irq_line;
1462
1463 irq_pin = pci_config_read8(addr, PCI_INTERRUPT_PIN);
1464 if (irq_pin) {
1465 config->irq_pin = irq_pin;
1466 irq_pin = (((config->dev >> 11) & 0x1F) + irq_pin - 1) & 3;
1467 irq_line = arch->irqs[irq_pin];
1468 pci_config_write8(addr, PCI_INTERRUPT_LINE, irq_line);
1469 config->irq_line = irq_line;
1470 } else
1471 config->irq_line = -1;
1472 }
1473
1474 static void
ob_pci_configure(pci_addr addr,pci_config_t * config,int num_regs,int rom_bar,unsigned long * mem_base,unsigned long * io_base)1475 ob_pci_configure(pci_addr addr, pci_config_t *config, int num_regs, int rom_bar,
1476 unsigned long *mem_base, unsigned long *io_base)
1477
1478 {
1479 uint32_t omask, mask;
1480 uint16_t cmd;
1481 int reg, flags, space_code;
1482 pci_addr config_addr;
1483
1484 ob_pci_configure_irq(addr, config);
1485
1486 omask = 0x00000000;
1487 for (reg = 0; reg < num_regs; ++reg) {
1488 config_addr = PCI_BASE_ADDR_0 + reg * 4;
1489
1490 ob_pci_configure_bar(addr, config, reg, config_addr,
1491 &omask, mem_base,
1492 io_base);
1493
1494 /* Ignore 64-bit BAR MSBs (always map in 32-bit space) */
1495 pci_decode_pci_addr(config->assigned[reg],
1496 &flags, &space_code, &mask);
1497
1498 if (space_code == MEMORY_SPACE_64) {
1499 reg++;
1500 }
1501 }
1502
1503 if (rom_bar) {
1504 config_addr = rom_bar;
1505 ob_pci_configure_bar(addr, config, reg, config_addr,
1506 &omask, mem_base, io_base);
1507 }
1508 cmd = pci_config_read16(addr, PCI_COMMAND);
1509 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
1510 pci_config_write16(addr, PCI_COMMAND, cmd);
1511 }
1512
1513 static phandle_t ob_configure_pci_device(const char* parent_path,
1514 int *bus_num, unsigned long *mem_base, unsigned long *io_base,
1515 int bus, int devnum, int fn, int *p_is_multi);
1516
ob_scan_pci_bus(int * bus_num,unsigned long * mem_base,unsigned long * io_base,const char * path,int bus)1517 static void ob_scan_pci_bus(int *bus_num, unsigned long *mem_base,
1518 unsigned long *io_base, const char *path,
1519 int bus)
1520 {
1521 int devnum, fn, is_multi;
1522
1523 PCI_DPRINTF("\nScanning bus %d at %s...\n", bus, path);
1524
1525 for (devnum = 0; devnum < 32; devnum++) {
1526 is_multi = 0;
1527 for (fn = 0; fn==0 || (is_multi && fn<8); fn++) {
1528 ob_configure_pci_device(path, bus_num, mem_base, io_base,
1529 bus, devnum, fn, &is_multi);
1530
1531 }
1532 }
1533 }
1534
1535 #if defined(CONFIG_SPARC64)
1536
1537 /* Convert device/irq pin to interrupt property */
1538 #define SUN4U_PCIAINTERRUPT(dev, irq_pin) \
1539 ((((dev >> 11) << 2) + irq_pin - 1) & 0x1f)
1540
1541 #define SUN4U_PCIBINTERRUPT(dev, irq_pin) \
1542 ((0x10 + (((dev >> 11) << 2) + irq_pin - 1)) & 0x1f)
1543
ob_pci_simbaB_bus_interrupt(ucell dnode,u32 * props,int * ncells,u32 addr,u32 intno)1544 static void ob_pci_simbaB_bus_interrupt(ucell dnode, u32 *props, int *ncells, u32 addr, u32 intno)
1545 {
1546 *ncells += pci_encode_phys_addr(props + *ncells, 0, 0, addr, 0, 0);
1547 props[(*ncells)++] = intno;
1548 props[(*ncells)++] = dnode;
1549 props[(*ncells)++] = SUN4U_PCIBINTERRUPT(addr, intno);
1550 }
1551
1552 static void ob_pci_bus_set_interrupt_map(phandle_t pcibus, phandle_t dnode,
1553 void (*func)(ucell dnode, u32 *props, int *ncells, u32 addr, u32 intno));
1554
ob_scan_sabre_pci_bus(int * bus_num,unsigned long * mem_base,unsigned long * io_base,const char * path,int bus)1555 static void ob_scan_sabre_pci_bus(int *bus_num, unsigned long *mem_base,
1556 unsigned long *io_base, const char *path,
1557 int bus)
1558 {
1559 int devnum, fn, is_multi;
1560 phandle_t ph;
1561
1562 PCI_DPRINTF("\nScanning sabre bus %d at %s...\n", bus, path);
1563
1564 /* Horrible sabre hack: the PCI bridge with the on-board devices
1565 is located at devfn (1,1) so if we use the standard scan function
1566 we end up with our ioports not mapped at io_base == 0x0 which
1567 breaks many assumptions in OpenBIOS. Hence do a custom scan for
1568 sabre which does things in the right order. */
1569 for (devnum = 0; devnum < 32; devnum++) {
1570 is_multi = 0;
1571
1572 if (devnum == 1) {
1573 /* Force io_base/mem_base to match the pciA simba range */
1574 *io_base = 0x0; /* because of arch->iobase */
1575 *mem_base = 0x20000000;
1576
1577 ob_configure_pci_device(path, bus_num, mem_base, io_base,
1578 bus, 1, 1, &is_multi);
1579
1580 /* Force io_base/mem_base to match the pciB simba range */
1581 *io_base = 0x800000; /* because of arch->iobase */
1582 *mem_base = 0x60000000;
1583
1584 ph = ob_configure_pci_device(path, bus_num, mem_base, io_base,
1585 bus, 1, 0, &is_multi);
1586
1587 /* Set up pciB interrupt map */
1588 ob_pci_bus_set_interrupt_map(ph, find_dev("/pci"), ob_pci_simbaB_bus_interrupt);
1589 } else {
1590 for (fn = 0; fn==0 || (is_multi && fn<8); fn++) {
1591 ob_configure_pci_device(path, bus_num, mem_base, io_base,
1592 bus, devnum, fn, &is_multi);
1593 }
1594 }
1595 }
1596 }
1597 #endif
1598
ob_configure_pci_bridge(pci_addr addr,int * bus_num,unsigned long * mem_base,unsigned long * io_base,int primary_bus,pci_config_t * config)1599 static void ob_configure_pci_bridge(pci_addr addr,
1600 int *bus_num, unsigned long *mem_base,
1601 unsigned long *io_base,
1602 int primary_bus, pci_config_t *config)
1603 {
1604 unsigned long old_mem_base, old_io_base, io_scan_limit;
1605 uint16_t cmd;
1606 phandle_t ph;
1607
1608 config->primary_bus = primary_bus;
1609 pci_config_write8(addr, PCI_PRIMARY_BUS, config->primary_bus);
1610
1611 config->secondary_bus = *bus_num;
1612 pci_config_write8(addr, PCI_SECONDARY_BUS, config->secondary_bus);
1613
1614 config->subordinate_bus = 0xff;
1615 pci_config_write8(addr, PCI_SUBORDINATE_BUS, config->subordinate_bus);
1616
1617 PCI_DPRINTF("scanning new pci bus %u under bridge %s\n",
1618 config->secondary_bus, config->path);
1619
1620 /* Temporarily add bus-range property to allow the secondary bus to
1621 determine its bus num */
1622 ph = find_dev(config->path);
1623 set_int_property(ph, "bus-range", *bus_num);
1624
1625 /* Always expose the legacy ioports on the first PCI bridge. If we
1626 must have legacy devices behind a PCI bridge then they must be
1627 on the first one discovered to ensure that the ioports will work. */
1628 if (primary_bus > 0 && *io_base < 0x1000) {
1629 *io_base = 0x0;
1630 }
1631
1632 /* Align mem_base up to nearest MB, io_base up to nearest 4K */
1633 old_mem_base = (*mem_base + 0xfffff - 1) & ~(0xfffff - 1);
1634 *mem_base = old_mem_base;
1635 old_io_base = (*io_base + 0xfff - 1) & ~(0xfff - 1);
1636 *io_base = old_io_base;
1637
1638 /* Set the base limit registers */
1639 pci_config_write16(addr, PCI_MEMORY_BASE, ((*mem_base >> 16) & ~(0xf)));
1640 pci_config_write16(addr, PCI_IO_BASE_UPPER, (*io_base >> 16));
1641 pci_config_write8(addr, PCI_IO_BASE, ((*io_base >> 8) & ~(0xf)));
1642
1643 /* Always ensure legacy ioports are accessible during enumeration.
1644 Some drivers (e.g. IDE) will attempt ioport access as part of
1645 the configuration process, so we allow them during the secondary
1646 bus scan and then set the correct IO limit below. */
1647 io_scan_limit = *io_base + 0xffff;
1648 pci_config_write16(addr, PCI_IO_LIMIT_UPPER, (io_scan_limit >> 16));
1649 pci_config_write8(addr, PCI_IO_LIMIT, (io_scan_limit >> 8) & ~(0xf));
1650
1651 /* make pci bridge parent device, prepare for recursion */
1652
1653 #if defined(CONFIG_SPARC64)
1654 /* Horrible hack for sabre */
1655 int vid = pci_config_read16(addr, PCI_VENDOR_ID);
1656 int did = pci_config_read16(addr, PCI_DEVICE_ID);
1657
1658 if (vid == PCI_VENDOR_ID_SUN && did == PCI_DEVICE_ID_SUN_SABRE) {
1659 ob_scan_sabre_pci_bus(bus_num, mem_base, io_base,
1660 config->path, config->secondary_bus);
1661 } else {
1662 ob_scan_pci_bus(bus_num, mem_base, io_base,
1663 config->path, config->secondary_bus);
1664 }
1665 #else
1666 ob_scan_pci_bus(bus_num, mem_base, io_base,
1667 config->path, config->secondary_bus);
1668 #endif
1669 /* bus scan updates *bus_num to last revealed pci bus number */
1670 config->subordinate_bus = *bus_num;
1671 pci_config_write8(addr, PCI_SUBORDINATE_BUS, config->subordinate_bus);
1672
1673 PCI_DPRINTF("bridge %s PCI bus primary=%d secondary=%d subordinate=%d\n",
1674 config->path, config->primary_bus, config->secondary_bus,
1675 config->subordinate_bus);
1676
1677 /* Align mem_base up to nearest MB, io_base up to nearest 4K */
1678 *mem_base = (*mem_base + 0xfffff - 1) & ~(0xfffff - 1);
1679 *io_base = (*io_base + 0xfff - 1) & ~(0xfff - 1);
1680
1681 /* Set the limit registers */
1682 pci_config_write16(addr, PCI_MEMORY_LIMIT, (((*mem_base - 1) >> 16) & ~(0xf)));
1683 pci_config_write16(addr, PCI_IO_LIMIT_UPPER, ((*io_base - 1) >> 16));
1684 pci_config_write8(addr, PCI_IO_LIMIT, (((*io_base - 1) >> 8) & ~(0xf)));
1685
1686 /* Disable unused address spaces */
1687 cmd = pci_config_read16(addr, PCI_COMMAND);
1688 if (*mem_base == old_mem_base) {
1689 pci_config_write16(addr, PCI_COMMAND, (cmd & ~PCI_COMMAND_MEMORY));
1690 }
1691
1692 if (*io_base == old_io_base) {
1693 pci_config_write16(addr, PCI_COMMAND, (cmd & ~PCI_COMMAND_IO));
1694 }
1695
1696 pci_set_bus_range(config);
1697 }
1698
ob_pci_read_identification(int bus,int devnum,int fn,int * p_vid,int * p_did,uint8_t * p_class,uint8_t * p_subclass)1699 static int ob_pci_read_identification(int bus, int devnum, int fn,
1700 int *p_vid, int *p_did,
1701 uint8_t *p_class, uint8_t *p_subclass)
1702 {
1703 int vid, did;
1704 uint32_t ccode;
1705 pci_addr addr;
1706
1707 #ifdef CONFIG_XBOX
1708 if (pci_xbox_blacklisted (bus, devnum, fn))
1709 return;
1710 #endif
1711 addr = PCI_ADDR(bus, devnum, fn);
1712 vid = pci_config_read16(addr, PCI_VENDOR_ID);
1713 did = pci_config_read16(addr, PCI_DEVICE_ID);
1714
1715 if (vid==0xffff || vid==0) {
1716 return 0;
1717 }
1718
1719 if (p_vid) {
1720 *p_vid = vid;
1721 }
1722
1723 if (p_did) {
1724 *p_did = did;
1725 }
1726
1727 ccode = pci_config_read16(addr, PCI_CLASS_DEVICE);
1728
1729 if (p_class) {
1730 *p_class = ccode >> 8;
1731 }
1732
1733 if (p_subclass) {
1734 *p_subclass = ccode;
1735 }
1736
1737 return 1;
1738 }
1739
ob_configure_pci_device(const char * parent_path,int * bus_num,unsigned long * mem_base,unsigned long * io_base,int bus,int devnum,int fn,int * p_is_multi)1740 static phandle_t ob_configure_pci_device(const char* parent_path,
1741 int *bus_num, unsigned long *mem_base, unsigned long *io_base,
1742 int bus, int devnum, int fn, int *p_is_multi)
1743 {
1744 int vid, did;
1745 unsigned int htype;
1746 pci_addr addr;
1747 pci_config_t config = {};
1748 const pci_dev_t *pci_dev;
1749 uint8_t class, subclass, iface;
1750 int num_bars, rom_bar;
1751 uint32_t props[3];
1752 char *unit_str;
1753
1754 phandle_t phandle = 0, t;
1755 int is_host_bridge = 0;
1756
1757 if (!ob_pci_read_identification(bus, devnum, fn, &vid, &did, &class, &subclass)) {
1758 return 0;
1759 }
1760
1761 addr = PCI_ADDR(bus, devnum, fn);
1762 iface = pci_config_read8(addr, PCI_CLASS_PROG);
1763
1764 pci_dev = pci_find_device(class, subclass, iface,
1765 vid, did);
1766
1767 PCI_DPRINTF("%x:%x.%x - %x:%x - ", bus, devnum, fn,
1768 vid, did);
1769
1770 htype = pci_config_read8(addr, PCI_HEADER_TYPE);
1771
1772 if (fn == 0) {
1773 if (p_is_multi) {
1774 *p_is_multi = htype & 0x80;
1775 }
1776 }
1777
1778 if (class == PCI_BASE_CLASS_BRIDGE &&
1779 subclass == PCI_SUBCLASS_BRIDGE_HOST) {
1780 is_host_bridge = 1;
1781 }
1782
1783 /* stop adding host bridge accessible from it's primary bus
1784 PCI host bridge is to be added by host code
1785 */
1786 if (is_host_bridge) {
1787 /* reuse device tree node */
1788 PCI_DPRINTF("host bridge found - ");
1789
1790 t = find_dev(parent_path);
1791 if (get_property(t, "vendor-id", NULL)) {
1792 PCI_DPRINTF("host bridge already configured\n");
1793 return 0;
1794 }
1795 } else if (pci_dev == NULL || pci_dev->name == NULL) {
1796 snprintf(config.path, sizeof(config.path),
1797 "%s/pci%x,%x", parent_path, vid, did);
1798 } else {
1799 snprintf(config.path, sizeof(config.path),
1800 "%s/%s", parent_path, pci_dev->name);
1801 }
1802
1803 fword("new-device");
1804
1805 PCI_DPRINTF("%s - ", config.path);
1806
1807 config.dev = addr & 0x00FFFFFF;
1808
1809 if (!is_host_bridge) {
1810 /* Get encoded address for set-args */
1811 pci_encode_phys_addr(props, 0, CONFIGURATION_SPACE, config.dev, 0, 0);
1812 PUSH(props[2]);
1813 PUSH(props[1]);
1814 PUSH(props[0]);
1815 call_parent_method("encode-unit");
1816
1817 unit_str = pop_fstr_copy();
1818
1819 /* Call set-args to set up my-space and my-address */
1820 PUSH(0);
1821 PUSH(0);
1822 push_str(unit_str);
1823 fword("set-args");
1824
1825 free(unit_str);
1826 }
1827
1828 phandle = get_cur_dev();
1829
1830 switch (class) {
1831 case PCI_BASE_CLASS_BRIDGE:
1832 if (subclass != PCI_SUBCLASS_BRIDGE_HOST) {
1833 BIND_NODE_METHODS(phandle, ob_pci_bridge_node);
1834 } else {
1835 BIND_NODE_METHODS(phandle, ob_pci_bus_node);
1836 }
1837 break;
1838 }
1839
1840 if (htype & PCI_HEADER_TYPE_BRIDGE) {
1841 num_bars = 2;
1842 rom_bar = PCI_ROM_ADDRESS1;
1843 } else {
1844 num_bars = 6;
1845 rom_bar = PCI_ROM_ADDRESS;
1846 }
1847
1848 ob_pci_configure(addr, &config, num_bars, rom_bar,
1849 mem_base, io_base);
1850
1851 ob_pci_add_properties(phandle, addr, pci_dev, &config, num_bars);
1852
1853 if (!is_host_bridge) {
1854 pci_set_reg(phandle, &config, num_bars);
1855 } else {
1856 pci_host_set_reg(phandle, &config);
1857 }
1858
1859 /* call device-specific configuration callback */
1860 if (pci_dev && pci_dev->config_cb) {
1861 //activate_device(config.path);
1862 pci_dev->config_cb(&config);
1863 }
1864
1865 /* if devices haven't supplied open/close words then supply them with simple defaults */
1866 if (!find_package_method("open", phandle) && !find_package_method("close", phandle)) {
1867 BIND_NODE_METHODS(phandle, ob_pci_simple_node);
1868 }
1869
1870 /* scan bus behind bridge device */
1871 //if (htype & PCI_HEADER_TYPE_BRIDGE && class == PCI_BASE_CLASS_BRIDGE) {
1872 if ( class == PCI_BASE_CLASS_BRIDGE &&
1873 ( subclass == PCI_SUBCLASS_BRIDGE_PCI ||
1874 subclass == PCI_SUBCLASS_BRIDGE_HOST ) ) {
1875
1876 if (subclass == PCI_SUBCLASS_BRIDGE_PCI) {
1877 /* reserve next pci bus number for this PCI bridge */
1878 ++(*bus_num);
1879 }
1880
1881 ob_configure_pci_bridge(addr, bus_num, mem_base, io_base, bus, &config);
1882 }
1883
1884 fword("finish-device");
1885
1886 return phandle;
1887 }
1888
ob_pci_set_available(phandle_t host,unsigned long mem_base,unsigned long io_base)1889 static void ob_pci_set_available(phandle_t host, unsigned long mem_base, unsigned long io_base)
1890 {
1891 /* Create an available property for both memory and IO space */
1892 uint32_t props[10];
1893 int ncells;
1894
1895 ncells = 0;
1896 ncells += pci_encode_phys_addr(props + ncells, 0, MEMORY_SPACE_32, 0, 0, mem_base);
1897 ncells += pci_encode_size(props + ncells, arch->mem_len - mem_base);
1898 ncells += pci_encode_phys_addr(props + ncells, 0, IO_SPACE, 0, 0, io_base);
1899 ncells += pci_encode_size(props + ncells, arch->io_len - io_base);
1900
1901 set_property(host, "available", (char *)props, ncells * sizeof(props[0]));
1902 }
1903
1904 #if defined(CONFIG_PPC)
ob_pci_host_set_interrupt_map(phandle_t host)1905 static phandle_t ob_pci_host_set_interrupt_map(phandle_t host)
1906 {
1907 /* Set the host bridge interrupt map, returning the phandle
1908 of the interrupt controller */
1909 phandle_t dnode, target_node;
1910 char *path, buf[256];
1911
1912 /* Oldworld macs do interrupt maps differently */
1913 if (is_oldworld()) {
1914 return 0;
1915 }
1916
1917 PCI_DPRINTF("setting up interrupt map for host %x\n", host);
1918 dnode = dt_iterate_type(0, "open-pic");
1919 path = get_path_from_ph(host);
1920 if (dnode && path) {
1921 /* patch in openpic interrupt-parent properties */
1922 snprintf(buf, sizeof(buf), "%s/mac-io", path);
1923 target_node = find_dev(buf);
1924 set_int_property(target_node, "interrupt-parent", dnode);
1925
1926 snprintf(buf, sizeof(buf), "%s/mac-io/escc/ch-a", path);
1927 target_node = find_dev(buf);
1928 set_int_property(target_node, "interrupt-parent", dnode);
1929
1930 snprintf(buf, sizeof(buf), "%s/mac-io/escc/ch-b", path);
1931 target_node = find_dev(buf);
1932 set_int_property(target_node, "interrupt-parent", dnode);
1933
1934 snprintf(buf, sizeof(buf), "%s/mac-io/escc-legacy/ch-a", path);
1935 target_node = find_dev(buf);
1936 set_int_property(target_node, "interrupt-parent", dnode);
1937
1938 snprintf(buf, sizeof(buf), "%s/mac-io/escc-legacy/ch-b", path);
1939 target_node = find_dev(buf);
1940 set_int_property(target_node, "interrupt-parent", dnode);
1941
1942 /* QEMU only emulates 2 of the 3 ata buses currently */
1943 /* On a new world Mac these are not numbered but named by the
1944 * ATA version they support. Thus we have: ata-3, ata-3, ata-4
1945 * On g3beige they all called just ide.
1946 * We take 2 x ata-3 buses which seems to work for
1947 * at least the clients we care about */
1948 snprintf(buf, sizeof(buf), "%s/mac-io/ata-3@20000", path);
1949 target_node = find_dev(buf);
1950 set_int_property(target_node, "interrupt-parent", dnode);
1951
1952 snprintf(buf, sizeof(buf), "%s/mac-io/ata-3@21000", path);
1953 target_node = find_dev(buf);
1954 set_int_property(target_node, "interrupt-parent", dnode);
1955
1956 snprintf(buf, sizeof(buf), "%s/mac-io/via-cuda", path);
1957 target_node = find_dev(buf);
1958 set_int_property(target_node, "interrupt-parent", dnode);
1959
1960 snprintf(buf, sizeof(buf), "%s/mac-io/via-pmu", path);
1961 target_node = find_dev(buf);
1962 if (target_node) {
1963 set_int_property(target_node, "interrupt-parent", dnode);
1964 }
1965
1966 snprintf(buf, sizeof(buf), "%s/mac-io/gpio/extint-gpio1", path);
1967 target_node = find_dev(buf);
1968 if (target_node) {
1969 set_int_property(target_node, "interrupt-parent", dnode);
1970 }
1971
1972 snprintf(buf, sizeof(buf), "%s/mac-io/gpio/programmer-switch", path);
1973 target_node = find_dev(buf);
1974 if (target_node) {
1975 set_int_property(target_node, "interrupt-parent", dnode);
1976 }
1977
1978 target_node = find_dev(path);
1979 set_int_property(target_node, "interrupt-parent", dnode);
1980
1981 return dnode;
1982 }
1983
1984 return host;
1985 }
1986
ob_pci_host_bus_interrupt(ucell dnode,u32 * props,int * ncells,u32 addr,u32 intno)1987 static void ob_pci_host_bus_interrupt(ucell dnode, u32 *props, int *ncells, u32 addr, u32 intno)
1988 {
1989 *ncells += pci_encode_phys_addr(props + *ncells, 0, 0, addr, 0, 0);
1990
1991 if (is_oldworld() || is_newworld()) {
1992 /* Mac machines */
1993 props[(*ncells)++] = intno;
1994 props[(*ncells)++] = dnode;
1995 props[(*ncells)++] = arch->irqs[((intno - 1) + (addr >> 11)) & 3];
1996 props[(*ncells)++] = 1;
1997 } else {
1998 /* PReP machines */
1999 props[(*ncells)++] = intno;
2000 props[(*ncells)++] = dnode;
2001
2002 if (PCI_DEV(addr) == 1 && PCI_FN(addr) == 0) {
2003 /* LSI SCSI has fixed routing to IRQ 13 */
2004 props[(*ncells)++] = 13;
2005 } else {
2006 /* Use the same "physical" routing as QEMU's raven_map_irq() although
2007 ultimately all 4 PCI interrupts are ORd to IRQ 15 as indicated
2008 by the PReP specification */
2009 props[(*ncells)++] = arch->irqs[((intno - 1) + (addr >> 11)) & 1];
2010 }
2011 props[(*ncells)++] = 1;
2012 }
2013 }
2014
2015 #elif defined(CONFIG_SPARC64)
2016
ob_pci_host_set_interrupt_map(phandle_t host)2017 static phandle_t ob_pci_host_set_interrupt_map(phandle_t host)
2018 {
2019 return host;
2020 }
2021
ob_pci_host_bus_interrupt(ucell dnode,u32 * props,int * ncells,u32 addr,u32 intno)2022 static void ob_pci_host_bus_interrupt(ucell dnode, u32 *props, int *ncells, u32 addr, u32 intno)
2023 {
2024 /* Note: this is invalid when the Simba bridges are in place
2025 as it is impossible to physically plug hardware into the PCI
2026 root bus (and no hardware support for mapping these interrupts
2027 either) */
2028 return;
2029 }
2030
2031 #else
2032
ob_pci_host_set_interrupt_map(phandle_t host)2033 static phandle_t ob_pci_host_set_interrupt_map(phandle_t host)
2034 {
2035 return host;
2036 }
2037
ob_pci_host_bus_interrupt(ucell dnode,u32 * props,int * ncells,u32 addr,u32 intno)2038 static void ob_pci_host_bus_interrupt(ucell dnode, u32 *props, int *ncells, u32 addr, u32 intno)
2039 {
2040 return;
2041 }
2042 #endif
2043
ob_pci_bus_set_interrupt_map(phandle_t pcibus,phandle_t dnode,void (* func)(ucell dnode,u32 * props,int * ncells,u32 addr,u32 intno))2044 static void ob_pci_bus_set_interrupt_map(phandle_t pcibus, phandle_t dnode,
2045 void (*func)(ucell dnode, u32 *props, int *ncells, u32 addr, u32 intno))
2046 {
2047 /* Set interrupt-map for PCI devices with an interrupt pin present */
2048 phandle_t pci_childnode = 0;
2049 u32 props[128], intno;
2050 int i, ncells = 0, len;
2051 u32 *val, addr;
2052 char *reg;
2053
2054 /* If no destination node specified, do nothing */
2055 if (dnode == 0) {
2056 return;
2057 }
2058
2059 PUSH(pcibus);
2060 fword("child");
2061 pci_childnode = POP();
2062 while (pci_childnode) {
2063 intno = get_int_property(pci_childnode, "interrupts", &len);
2064 if (len && intno) {
2065 reg = get_property(pci_childnode, "reg", &len);
2066 if (len && reg) {
2067 val = (u32 *)reg;
2068
2069 for (i = 0; i < (len / sizeof(u32)); i += 5) {
2070 addr = val[i];
2071
2072 /* Device address is in 1st 32-bit word of encoded PCI address for config space */
2073 if ((addr & PCI_RANGE_TYPE_MASK) == PCI_RANGE_CONFIG) {
2074 (*func)(dnode, props, &ncells, addr, intno);
2075 }
2076 }
2077 }
2078 }
2079
2080 PUSH(pci_childnode);
2081 fword("peer");
2082 pci_childnode = POP();
2083 }
2084
2085 if (ncells) {
2086 set_property(pcibus, "interrupt-map", (char *)props, ncells * sizeof(props[0]));
2087
2088 props[0] = 0x00fff800;
2089 props[1] = 0x0;
2090 props[2] = 0x0;
2091 props[3] = 0x7;
2092 set_property(pcibus, "interrupt-map-mask", (char *)props, 4 * sizeof(props[0]));
2093 }
2094 }
2095
ob_pci_init(void)2096 int ob_pci_init(void)
2097 {
2098 int bus, devnum, fn;
2099 uint8_t class, subclass;
2100 unsigned long mem_base, io_base;
2101
2102 pci_config_t config = {}; /* host bridge */
2103 phandle_t phandle_host = 0, intc;
2104
2105 PCI_DPRINTF("Initializing PCI host bridge...\n");
2106
2107 /* Find all PCI bridges */
2108
2109 mem_base = arch->pci_mem_base;
2110 /* I/O ports under 0x400 are used by devices mapped at fixed
2111 location. */
2112 io_base = 0x400;
2113
2114 bus = 0;
2115
2116 for (devnum = 0; devnum < 32; devnum++) {
2117 /* scan only fn 0 */
2118 fn = 0;
2119
2120 if (!ob_pci_read_identification(bus, devnum, fn,
2121 0, 0, &class, &subclass)) {
2122 continue;
2123 }
2124
2125 if (class != PCI_BASE_CLASS_BRIDGE || subclass != PCI_SUBCLASS_BRIDGE_HOST) {
2126 continue;
2127 }
2128
2129 /* create root node for host PCI bridge */
2130
2131 /* configure */
2132 strncpy(config.path, "", sizeof(config.path));
2133
2134 phandle_host = ob_configure_pci_device(config.path, &bus, &mem_base, &io_base,
2135 bus, devnum, fn, 0);
2136
2137 /* we expect single host PCI bridge
2138 but this may be machine-specific */
2139 break;
2140 }
2141
2142 /* create available attributes for the PCI bridge */
2143 ob_pci_set_available(phandle_host, mem_base, io_base);
2144
2145 /* configure the host bridge interrupt map */
2146 intc = ob_pci_host_set_interrupt_map(phandle_host);
2147 ob_pci_bus_set_interrupt_map(phandle_host, intc, ob_pci_host_bus_interrupt);
2148
2149 return 0;
2150 }
2151