1 /* Copyright 2013-2014 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 /* Handle ChipTOD chip & configure core and CAPP timebases */
18
19 #define pr_fmt(fmt) "CHIPTOD: " fmt
20
21 #include <skiboot.h>
22 #include <xscom.h>
23 #include <pci.h>
24 #include <chiptod.h>
25 #include <chip.h>
26 #include <io.h>
27 #include <cpu.h>
28 #include <timebase.h>
29 #include <opal-api.h>
30
31 /* TOD chip XSCOM addresses */
32 #define TOD_MASTER_PATH_CTRL 0x00040000 /* Master Path ctrl reg */
33 #define TOD_PRI_PORT0_CTRL 0x00040001 /* Primary port0 ctrl reg */
34 #define TOD_PRI_PORT1_CTRL 0x00040002 /* Primary port1 ctrl reg */
35 #define TOD_SEC_PORT0_CTRL 0x00040003 /* Secondary p0 ctrl reg */
36 #define TOD_SEC_PORT1_CTRL 0x00040004 /* Secondary p1 ctrl reg */
37 #define TOD_SLAVE_PATH_CTRL 0x00040005 /* Slave Path ctrl reg */
38 #define TOD_INTERNAL_PATH_CTRL 0x00040006 /* Internal Path ctrl reg */
39
40 /* -- TOD primary/secondary master/slave control register -- */
41 #define TOD_PSMS_CTRL 0x00040007
42 #define TOD_PSMSC_PM_TOD_SELECT PPC_BIT(1) /* Primary Master TOD */
43 #define TOD_PSMSC_PM_DRAW_SELECT PPC_BIT(2) /* Primary Master Drawer */
44 #define TOD_PSMSC_SM_TOD_SELECT PPC_BIT(9) /* Secondary Master TOD */
45 #define TOD_PSMSC_SM_DRAW_SELECT PPC_BIT(10) /* Secondary Master Draw */
46
47 /* -- TOD primary/secondary master/slave status register -- */
48 #define TOD_STATUS 0x00040008
49 #define TOD_ST_TOPOLOGY_SELECT PPC_BITMASK(0, 2)
50 #define TOD_ST_MPATH0_STEP_VALID PPC_BIT(6) /* MasterPath0 step valid */
51 #define TOD_ST_MPATH1_STEP_VALID PPC_BIT(7) /* MasterPath1 step valid */
52 #define TOD_ST_SPATH0_STEP_VALID PPC_BIT(8) /* SlavePath0 step valid */
53 #define TOD_ST_SPATH1_STEP_VALID PPC_BIT(10) /* SlavePath1 step valid */
54 /* Primary master/slave path select (0 = PATH_0, 1 = PATH_1) */
55 #define TOD_ST_PRI_MPATH_SELECT PPC_BIT(12) /* Primary MPath Select */
56 #define TOD_ST_PRI_SPATH_SELECT PPC_BIT(15) /* Primary SPath Select */
57 /* Secondary master/slave path select (0 = PATH_0, 1 = PATH_1) */
58 #define TOD_ST_SEC_MPATH_SELECT PPC_BIT(16) /* Secondary MPath Select */
59 #define TOD_ST_SEC_SPATH_SELECT PPC_BIT(19) /* Secondary SPath Select */
60 #define TOD_ST_ACTIVE_MASTER PPC_BIT(23)
61 #define TOD_ST_BACKUP_MASTER PPC_BIT(24)
62
63 /* TOD chip XSCOM addresses */
64 #define TOD_CHIP_CTRL 0x00040010 /* Chip control register */
65 #define TOD_TTYPE_0 0x00040011
66 #define TOD_TTYPE_1 0x00040012 /* PSS switch */
67 #define TOD_TTYPE_2 0x00040013 /* Enable step checkers */
68 #define TOD_TTYPE_3 0x00040014 /* Request TOD */
69 #define TOD_TTYPE_4 0x00040015 /* Send TOD */
70 #define TOD_TTYPE_5 0x00040016 /* Invalidate TOD */
71 #define TOD_CHIPTOD_TO_TB 0x00040017
72 #define TOD_LOAD_TOD_MOD 0x00040018
73 #define TOD_CHIPTOD_VALUE 0x00040020
74 #define TOD_CHIPTOD_LOAD_TB 0x00040021
75 #define TOD_CHIPTOD_FSM 0x00040024
76
77 /* -- TOD PIB Master reg -- */
78 #define TOD_PIB_MASTER 0x00040027
79 #define TOD_PIBM_ADDR_CFG_MCAST PPC_BIT(25)
80 #define TOD_PIBM_ADDR_CFG_SLADDR PPC_BITMASK(26, 31)
81 #define TOD_PIBM_TTYPE4_SEND_MODE PPC_BIT(32)
82 #define TOD_PIBM_TTYPE4_SEND_ENBL PPC_BIT(33)
83
84 /* -- TOD Error interrupt register -- */
85 #define TOD_ERROR 0x00040030
86 /* SYNC errors */
87 #define TOD_ERR_CRMO_PARITY PPC_BIT(0)
88 #define TOD_ERR_OSC0_PARITY PPC_BIT(1)
89 #define TOD_ERR_OSC1_PARITY PPC_BIT(2)
90 #define TOD_ERR_PPORT0_CREG_PARITY PPC_BIT(3)
91 #define TOD_ERR_PPORT1_CREG_PARITY PPC_BIT(4)
92 #define TOD_ERR_SPORT0_CREG_PARITY PPC_BIT(5)
93 #define TOD_ERR_SPORT1_CREG_PARITY PPC_BIT(6)
94 #define TOD_ERR_SPATH_CREG_PARITY PPC_BIT(7)
95 #define TOD_ERR_IPATH_CREG_PARITY PPC_BIT(8)
96 #define TOD_ERR_PSMS_CREG_PARITY PPC_BIT(9)
97 #define TOD_ERR_CRITC_PARITY PPC_BIT(13)
98 #define TOD_ERR_MP0_STEP_CHECK PPC_BIT(14)
99 #define TOD_ERR_MP1_STEP_CHECK PPC_BIT(15)
100 #define TOD_ERR_PSS_HAMMING_DISTANCE PPC_BIT(18)
101 #define TOD_ERR_DELAY_COMPL_PARITY PPC_BIT(22)
102 /* CNTR errors */
103 #define TOD_ERR_CTCR_PARITY PPC_BIT(32)
104 #define TOD_ERR_TOD_SYNC_CHECK PPC_BIT(33)
105 #define TOD_ERR_TOD_FSM_PARITY PPC_BIT(34)
106 #define TOD_ERR_TOD_REGISTER_PARITY PPC_BIT(35)
107 #define TOD_ERR_OVERFLOW_YR2042 PPC_BIT(36)
108 #define TOD_ERR_TOD_WOF_LSTEP_PARITY PPC_BIT(37)
109 #define TOD_ERR_TTYPE0_RECVD PPC_BIT(38)
110 #define TOD_ERR_TTYPE1_RECVD PPC_BIT(39)
111 #define TOD_ERR_TTYPE2_RECVD PPC_BIT(40)
112 #define TOD_ERR_TTYPE3_RECVD PPC_BIT(41)
113 #define TOD_ERR_TTYPE4_RECVD PPC_BIT(42)
114 #define TOD_ERR_TTYPE5_RECVD PPC_BIT(43)
115
116 /* -- TOD Error interrupt register -- */
117 #define TOD_ERROR_INJECT 0x00040031
118
119 /* Local FIR EH.TPCHIP.TPC.LOCAL_FIR */
120 #define LOCAL_CORE_FIR 0x0104000C
121 #define LFIR_SWITCH_COMPLETE PPC_BIT(18)
122
123 /* Number of iterations for the various timeouts */
124 #define TIMEOUT_LOOPS 20000000
125
126 /* TOD active Primary/secondary configuration */
127 #define TOD_PRI_CONF_IN_USE 0 /* Tod using primary topology*/
128 #define TOD_SEC_CONF_IN_USE 7 /* Tod using secondary topo */
129
130 /* Timebase State Machine error state */
131 #define TBST_STATE_ERROR 9
132
133 static enum chiptod_type {
134 chiptod_unknown,
135 chiptod_p8,
136 chiptod_p9
137 } chiptod_type;
138
139 enum chiptod_chip_role {
140 chiptod_chip_role_UNKNOWN = -1,
141 chiptod_chip_role_MDMT = 0, /* Master Drawer Master TOD */
142 chiptod_chip_role_MDST, /* Master Drawer Slave TOD */
143 chiptod_chip_role_SDMT, /* Slave Drawer Master TOD */
144 chiptod_chip_role_SDST, /* Slave Drawer Slave TOD */
145 };
146
147 enum chiptod_chip_status {
148 chiptod_active_master = 0, /* Chip TOD is Active master */
149 chiptod_backup_master = 1, /* Chip TOD is backup master */
150 chiptod_backup_disabled, /* Chip TOD is backup but disabled */
151 };
152
153 struct chiptod_chip_config_info {
154 int32_t id; /* chip id */
155 enum chiptod_chip_role role; /* Chip role */
156 enum chiptod_chip_status status; /* active/backup/disabled */
157 };
158
159 static int32_t chiptod_primary = -1;
160 static int32_t chiptod_secondary = -1;
161 static enum chiptod_topology current_topology = chiptod_topo_unknown;
162
163 /*
164 * chiptod_topology_info holds primary/secondary chip configuration info.
165 * This info is initialized during chiptod_init(). This is an array of two:
166 * [0] = [chiptod_topo_primary] = Primary topology config info
167 * [1] = [chiptod_topo_secondary] = Secondary topology config info
168 */
169 static struct chiptod_chip_config_info chiptod_topology_info[2];
170
171 /*
172 * Array of TOD control registers that holds last known valid values.
173 *
174 * Cache chiptod control register values at following instances:
175 * 1. Chiptod initialization
176 * 2. After topology switch is complete.
177 * 3. Upon receiving enable/disable topology request from FSP.
178 *
179 * Cache following chip TOD control registers:
180 * - Master Path control register (0x00040000)
181 * - Primary Port-0 control register (0x00040001)
182 * - Primary Port-1 control register (0x00040002)
183 * - Secondary Port-0 control register (0x00040003)
184 * - Secondary Port-1 control register (0x00040004)
185 * - Slave Path control register (0x00040005)
186 * - Internal Path control register (0x00040006)
187 * - Primary/secondary master/slave control register (0x00040007)
188 * - Chip control register (0x00040010)
189 *
190 * This data is used for restoring respective TOD registers to sane values
191 * whenever parity errors are reported on these registers (through HMI).
192 * The error_bit maps to corresponding bit from TOD error register that
193 * reports parity error on respective TOD registers.
194 */
195 static struct chiptod_tod_regs {
196 /* error bit from TOD Error reg */
197 const uint64_t error_bit;
198
199 /* xscom address of TOD register to be restored. */
200 const uint64_t xscom_addr;
201 /* per chip cached value of TOD control registers to be restored. */
202 struct {
203 uint64_t data;
204 bool valid;
205 } val[MAX_CHIPS];
206 } chiptod_tod_regs[] = {
207 { TOD_ERR_CRMO_PARITY, TOD_MASTER_PATH_CTRL, { } },
208 { TOD_ERR_PPORT0_CREG_PARITY, TOD_PRI_PORT0_CTRL, { } },
209 { TOD_ERR_PPORT1_CREG_PARITY, TOD_PRI_PORT1_CTRL, { } },
210 { TOD_ERR_SPORT0_CREG_PARITY, TOD_SEC_PORT0_CTRL, { } },
211 { TOD_ERR_SPORT1_CREG_PARITY, TOD_SEC_PORT1_CTRL, { } },
212 { TOD_ERR_SPATH_CREG_PARITY, TOD_SLAVE_PATH_CTRL, { } },
213 { TOD_ERR_IPATH_CREG_PARITY, TOD_INTERNAL_PATH_CTRL, { } },
214 { TOD_ERR_PSMS_CREG_PARITY, TOD_PSMS_CTRL, { } },
215 { TOD_ERR_CTCR_PARITY, TOD_CHIP_CTRL, { } },
216 };
217
218 /* The base TFMR value is the same for the whole machine
219 * for now as far as I can tell
220 */
221 static uint64_t base_tfmr;
222
223 /*
224 * For now, we use a global lock for runtime chiptod operations,
225 * eventually make this a per-core lock for wakeup rsync and
226 * take all of them for RAS cases.
227 */
228 static struct lock chiptod_lock = LOCK_UNLOCKED;
229 static bool chiptod_unrecoverable;
230
_chiptod_cache_tod_regs(int32_t chip_id)231 static void _chiptod_cache_tod_regs(int32_t chip_id)
232 {
233 int i;
234
235 for (i = 0; i < ARRAY_SIZE(chiptod_tod_regs); i++) {
236 if (xscom_read(chip_id, chiptod_tod_regs[i].xscom_addr,
237 &(chiptod_tod_regs[i].val[chip_id].data))) {
238 prerror("XSCOM error reading 0x%08llx reg.\n",
239 chiptod_tod_regs[i].xscom_addr);
240 /* Invalidate this record and continue */
241 chiptod_tod_regs[i].val[chip_id].valid = 0;
242 continue;
243 }
244 chiptod_tod_regs[i].val[chip_id].valid = 1;
245 }
246 }
247
chiptod_cache_tod_registers(void)248 static void chiptod_cache_tod_registers(void)
249 {
250 struct proc_chip *chip;
251
252 for_each_chip(chip)
253 _chiptod_cache_tod_regs(chip->id);
254 }
255
print_topo_info(enum chiptod_topology topo)256 static void print_topo_info(enum chiptod_topology topo)
257 {
258 const char *role[] = { "Unknown", "MDMT", "MDST", "SDMT", "SDST" };
259 const char *status[] = { "Unknown",
260 "Active Master", "Backup Master", "Backup Master Disabled" };
261
262 prlog(PR_DEBUG, " Chip id: %d, Role: %s, Status: %s\n",
263 chiptod_topology_info[topo].id,
264 role[chiptod_topology_info[topo].role + 1],
265 status[chiptod_topology_info[topo].status + 1]);
266 }
267
print_topology_info(void)268 static void print_topology_info(void)
269 {
270 const char *topo[] = { "Unknown", "Primary", "Secondary" };
271
272 if (current_topology < 0)
273 return;
274
275 prlog(PR_DEBUG, "TOD Topology in Use: %s\n",
276 topo[current_topology+1]);
277 prlog(PR_DEBUG, " Primary configuration:\n");
278 print_topo_info(chiptod_topo_primary);
279 prlog(PR_DEBUG, " Secondary configuration:\n");
280 print_topo_info(chiptod_topo_secondary);
281 }
282
query_current_topology(void)283 static enum chiptod_topology query_current_topology(void)
284 {
285 uint64_t tod_status;
286
287 if (xscom_readme(TOD_STATUS, &tod_status)) {
288 prerror("XSCOM error reading TOD_STATUS reg\n");
289 return chiptod_topo_unknown;
290 }
291
292 /*
293 * Tod status register bit [0-2] tells configuration in use.
294 * 000 <= primary configuration in use
295 * 111 <= secondary configuration in use
296 */
297 if ((tod_status & TOD_ST_TOPOLOGY_SELECT) == TOD_PRI_CONF_IN_USE)
298 return chiptod_topo_primary;
299 else
300 return chiptod_topo_secondary;
301 }
302
303 static enum chiptod_chip_role
chiptod_get_chip_role(enum chiptod_topology topology,int32_t chip_id)304 chiptod_get_chip_role(enum chiptod_topology topology, int32_t chip_id)
305 {
306 uint64_t tod_ctrl;
307 enum chiptod_chip_role role = chiptod_chip_role_UNKNOWN;
308
309 if (chip_id < 0)
310 return role;
311
312 if (xscom_read(chip_id, TOD_PSMS_CTRL, &tod_ctrl)) {
313 prerror("XSCOM error reading TOD_PSMS_CTRL\n");
314 return chiptod_chip_role_UNKNOWN;
315 }
316
317 switch (topology) {
318 case chiptod_topo_primary:
319 if (tod_ctrl & TOD_PSMSC_PM_DRAW_SELECT) {
320 if (tod_ctrl & TOD_PSMSC_PM_TOD_SELECT)
321 role = chiptod_chip_role_MDMT;
322 else
323 role = chiptod_chip_role_MDST;
324 } else {
325 if (tod_ctrl & TOD_PSMSC_PM_TOD_SELECT)
326 role = chiptod_chip_role_SDMT;
327 else
328 role = chiptod_chip_role_SDST;
329 }
330 break;
331 case chiptod_topo_secondary:
332 if (tod_ctrl & TOD_PSMSC_SM_DRAW_SELECT) {
333 if (tod_ctrl & TOD_PSMSC_SM_TOD_SELECT)
334 role = chiptod_chip_role_MDMT;
335 else
336 role = chiptod_chip_role_MDST;
337 } else {
338 if (tod_ctrl & TOD_PSMSC_SM_TOD_SELECT)
339 role = chiptod_chip_role_SDMT;
340 else
341 role = chiptod_chip_role_SDST;
342 }
343 break;
344 case chiptod_topo_unknown:
345 default:
346 break;
347 }
348 return role;
349 }
350
351 /*
352 * Check and return the status of sync step network for a given
353 * topology configuration.
354 * Return values:
355 * true: Sync Step network is running
356 * false: Sync Step network is not running
357 */
chiptod_sync_step_check_running(enum chiptod_topology topology)358 static bool chiptod_sync_step_check_running(enum chiptod_topology topology)
359 {
360 uint64_t tod_status;
361 enum chiptod_chip_role role;
362 bool running = false;
363 int32_t chip_id = chiptod_topology_info[topology].id;
364
365 /* Sanity check */
366 if (chip_id < 0)
367 return false;
368
369 if (xscom_read(chip_id, TOD_STATUS, &tod_status)) {
370 prerror("XSCOM error reading TOD_STATUS reg\n");
371 return false;
372 }
373
374 switch (topology) {
375 case chiptod_topo_primary:
376 /* Primary configuration */
377 role = chiptod_topology_info[topology].role;
378 if (role == chiptod_chip_role_MDMT) {
379 /*
380 * Chip is using Master path.
381 * Check if it is using path_0/path_1 and then
382 * validity of that path.
383 *
384 * TOD_STATUS[12]: 0 = PATH_0, 1 = PATH_1
385 */
386 if (tod_status & TOD_ST_PRI_MPATH_SELECT) {
387 if (tod_status & TOD_ST_MPATH1_STEP_VALID)
388 running = true;
389 } else {
390 if (tod_status & TOD_ST_MPATH0_STEP_VALID)
391 running = true;
392 }
393 } else {
394 /*
395 * Chip is using Slave path.
396 *
397 * TOD_STATUS[15]: 0 = PATH_0, 1 = PATH_1
398 */
399 if (tod_status & TOD_ST_PRI_SPATH_SELECT) {
400 if (tod_status & TOD_ST_SPATH1_STEP_VALID)
401 running = true;
402 } else {
403 if (tod_status & TOD_ST_SPATH0_STEP_VALID)
404 running = true;
405 }
406 }
407 break;
408 case chiptod_topo_secondary:
409 /* Secondary configuration */
410 role = chiptod_topology_info[topology].role;
411 if (role == chiptod_chip_role_MDMT) {
412 /*
413 * Chip is using Master path.
414 * Check if it is using path_0/path_1 and then
415 * validity of that path.
416 *
417 * TOD_STATUS[12]: 0 = PATH_0, 1 = PATH_1
418 */
419 if (tod_status & TOD_ST_SEC_MPATH_SELECT) {
420 if (tod_status & TOD_ST_MPATH1_STEP_VALID)
421 running = true;
422 } else {
423 if (tod_status & TOD_ST_MPATH0_STEP_VALID)
424 running = true;
425 }
426 } else {
427 /*
428 * Chip is using Slave path.
429 *
430 * TOD_STATUS[15]: 0 = PATH_0, 1 = PATH_1
431 */
432 if (tod_status & TOD_ST_SEC_SPATH_SELECT) {
433 if (tod_status & TOD_ST_SPATH1_STEP_VALID)
434 running = true;
435 } else {
436 if (tod_status & TOD_ST_SPATH0_STEP_VALID)
437 running = true;
438 }
439 }
440 break;
441 default:
442 break;
443 }
444 return running;
445 }
446
_chiptod_get_chip_status(int32_t chip_id)447 static enum chiptod_chip_status _chiptod_get_chip_status(int32_t chip_id)
448 {
449 uint64_t tod_status;
450 enum chiptod_chip_status status = -1;
451
452 if (chip_id < 0)
453 return chiptod_backup_disabled;
454
455 if (xscom_read(chip_id, TOD_STATUS, &tod_status)) {
456 prerror("XSCOM error reading TOD_STATUS reg\n");
457 return status;
458 }
459
460 if (tod_status & TOD_ST_ACTIVE_MASTER)
461 status = chiptod_active_master;
462 else if (tod_status & TOD_ST_BACKUP_MASTER)
463 status = chiptod_backup_master;
464
465 return status;
466 }
467
468 static enum chiptod_chip_status
chiptod_get_chip_status(enum chiptod_topology topology)469 chiptod_get_chip_status(enum chiptod_topology topology)
470 {
471 return _chiptod_get_chip_status(chiptod_topology_info[topology].id);
472 }
473
chiptod_update_topology(enum chiptod_topology topo)474 static void chiptod_update_topology(enum chiptod_topology topo)
475 {
476 int32_t chip_id = chiptod_topology_info[topo].id;
477
478 if (chip_id < 0)
479 return;
480
481 chiptod_topology_info[topo].role = chiptod_get_chip_role(topo, chip_id);
482 chiptod_topology_info[topo].status = chiptod_get_chip_status(topo);
483
484 /*
485 * If chip TOD on this topology is a backup master then check if
486 * sync/step network is running on this topology. If not,
487 * then mark status as backup not valid.
488 */
489 if ((chiptod_topology_info[topo].status == chiptod_backup_master) &&
490 !chiptod_sync_step_check_running(topo))
491 chiptod_topology_info[topo].status = chiptod_backup_disabled;
492 }
493
chiptod_setup_base_tfmr(void)494 static void chiptod_setup_base_tfmr(void)
495 {
496 struct dt_node *cpu = this_cpu()->node;
497 uint64_t core_freq, tod_freq;
498 uint64_t mcbs;
499
500 base_tfmr = SPR_TFMR_TB_ECLIPZ;
501
502 /* Get CPU and TOD freqs in Hz */
503 if (dt_has_node_property(cpu, "ibm,extended-clock-frequency", NULL))
504 core_freq = dt_prop_get_u64(cpu, "ibm,extended-clock-frequency");
505 else
506 core_freq = dt_prop_get_u32(cpu, "clock-frequency");
507 tod_freq = 32000000;
508
509 /* Calculate the "Max Cycles Between Steps" value according
510 * to the magic formula:
511 *
512 * mcbs = (core_freq * max_jitter_factor) / (4 * tod_freq) / 100;
513 *
514 * The max jitter factor is set to 240 based on what pHyp uses.
515 */
516 mcbs = (core_freq * 240) / (4 * tod_freq) / 100;
517 prlog(PR_INFO, "Calculated MCBS is 0x%llx"
518 " (Cfreq=%lld Tfreq=%lld)\n",
519 mcbs, core_freq, tod_freq);
520
521 /* Bake that all into TFMR */
522 base_tfmr = SETFIELD(SPR_TFMR_MAX_CYC_BET_STEPS, base_tfmr, mcbs);
523 base_tfmr = SETFIELD(SPR_TFMR_N_CLKS_PER_STEP, base_tfmr, 0);
524 base_tfmr = SETFIELD(SPR_TFMR_SYNC_BIT_SEL, base_tfmr, 4);
525 }
526
chiptod_mod_tb(void)527 static bool chiptod_mod_tb(void)
528 {
529 uint64_t tfmr = base_tfmr;
530 uint64_t timeout = 0;
531
532 /* Switch timebase to "Not Set" state */
533 mtspr(SPR_TFMR, tfmr | SPR_TFMR_LOAD_TOD_MOD);
534 do {
535 if (++timeout >= (TIMEOUT_LOOPS*2)) {
536 prerror("TB \"Not Set\" timeout\n");
537 return false;
538 }
539 tfmr = mfspr(SPR_TFMR);
540 if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
541 prerror("TB \"Not Set\" TFMR corrupt\n");
542 return false;
543 }
544 if (GETFIELD(SPR_TFMR_TBST_ENCODED, tfmr) == 9) {
545 prerror("TB \"Not Set\" TOD in error state\n");
546 return false;
547 }
548 } while (tfmr & SPR_TFMR_LOAD_TOD_MOD);
549
550 return true;
551 }
552
chiptod_interrupt_check(void)553 static bool chiptod_interrupt_check(void)
554 {
555 uint64_t tfmr;
556 uint64_t timeout = 0;
557
558 do {
559 if (++timeout >= TIMEOUT_LOOPS) {
560 prerror("Interrupt check fail\n");
561 return false;
562 }
563 tfmr = mfspr(SPR_TFMR);
564 if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
565 prerror("Interrupt check TFMR corrupt !\n");
566 return false;
567 }
568 } while (tfmr & SPR_TFMR_CHIP_TOD_INTERRUPT);
569
570 return true;
571 }
572
chiptod_running_check(uint32_t chip_id)573 static bool chiptod_running_check(uint32_t chip_id)
574 {
575 uint64_t tval;
576
577 if (xscom_read(chip_id, TOD_CHIPTOD_FSM, &tval)) {
578 prerror("XSCOM error polling run\n");
579 return false;
580 }
581 if (tval & 0x0800000000000000UL)
582 return true;
583 else
584 return false;
585 }
586
chiptod_poll_running(void)587 static bool chiptod_poll_running(void)
588 {
589 uint64_t timeout = 0;
590 uint64_t tval;
591
592 /* Chip TOD running check */
593 do {
594 if (++timeout >= TIMEOUT_LOOPS) {
595 prerror("Running check fail timeout\n");
596 return false;
597 }
598 if (xscom_readme(TOD_CHIPTOD_FSM, &tval)) {
599 prerror("XSCOM error polling run\n");
600 return false;
601 }
602 } while (!(tval & 0x0800000000000000UL));
603
604 return true;
605 }
606
chiptod_to_tb(void)607 static bool chiptod_to_tb(void)
608 {
609 uint64_t tval, tfmr, tvbits;
610 uint64_t timeout = 0;
611
612 /* Tell the ChipTOD about our fabric address
613 *
614 * The pib_master value is calculated from the CPU core ID, given in
615 * the PIR. Because we have different core/thread arrangements in the
616 * PIR between p7 and p8, we need to do the calculation differently.
617 *
618 * p7: 0b00001 || 3-bit core id
619 * p8: 0b0001 || 4-bit core id
620 */
621
622 if (xscom_readme(TOD_PIB_MASTER, &tval)) {
623 prerror("XSCOM error reading PIB_MASTER\n");
624 return false;
625 }
626 if (chiptod_type == chiptod_p9) {
627 tvbits = (this_cpu()->pir >> 2) & 0x1f;
628 tvbits |= 0x20;
629 } else if (chiptod_type == chiptod_p8) {
630 tvbits = (this_cpu()->pir >> 3) & 0xf;
631 tvbits |= 0x10;
632 } else {
633 tvbits = (this_cpu()->pir >> 2) & 0x7;
634 tvbits |= 0x08;
635 }
636 tval &= ~TOD_PIBM_ADDR_CFG_MCAST;
637 tval = SETFIELD(TOD_PIBM_ADDR_CFG_SLADDR, tval, tvbits);
638 if (xscom_writeme(TOD_PIB_MASTER, tval)) {
639 prerror("XSCOM error writing PIB_MASTER\n");
640 return false;
641 }
642
643 /* Make us ready to get the TB from the chipTOD */
644 mtspr(SPR_TFMR, base_tfmr | SPR_TFMR_MOVE_CHIP_TOD_TO_TB);
645
646 /* Tell the ChipTOD to send it */
647 if (xscom_writeme(TOD_CHIPTOD_TO_TB, PPC_BIT(0))) {
648 prerror("XSCOM error writing CHIPTOD_TO_TB\n");
649 return false;
650 }
651
652 /* Wait for it to complete */
653 timeout = 0;
654 do {
655 if (++timeout >= TIMEOUT_LOOPS) {
656 prerror("Chip to TB timeout\n");
657 return false;
658 }
659 tfmr = mfspr(SPR_TFMR);
660 if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
661 prerror("MoveToTB: corrupt TFMR !\n");
662 return false;
663 }
664 } while (tfmr & SPR_TFMR_MOVE_CHIP_TOD_TO_TB);
665
666 return true;
667 }
668
chiptod_check_tb_running(void)669 static bool chiptod_check_tb_running(void)
670 {
671 /* We used to wait for two SYNC pulses in TFMR but that
672 * doesn't seem to occur in sim, so instead we use a
673 * method similar to what pHyp does which is to check for
674 * TFMR SPR_TFMR_TB_VALID and not SPR_TFMR_TFMR_CORRUPT
675 */
676 #if 0
677 uint64_t tfmr, timeout;
678 unsigned int i;
679
680 for (i = 0; i < 2; i++) {
681 tfmr = mfspr(SPR_TFMR);
682 tfmr &= ~SPR_TFMR_TB_SYNC_OCCURED;
683 mtspr(SPR_TFMR, tfmr);
684 timeout = 0;
685 do {
686 if (++timeout >= TIMEOUT_LOOPS) {
687 prerror("CHIPTOD: No sync pulses\n");
688 return false;
689 }
690 tfmr = mfspr(SPR_TFMR);
691 } while (!(tfmr & SPR_TFMR_TB_SYNC_OCCURED));
692 }
693 #else
694 uint64_t tfmr = mfspr(SPR_TFMR);
695
696 return (tfmr & SPR_TFMR_TB_VALID) &&
697 !(tfmr & SPR_TFMR_TFMR_CORRUPT);
698 #endif
699 return true;
700 }
701
chiptod_reset_tb_errors(void)702 static bool chiptod_reset_tb_errors(void)
703 {
704 uint64_t tfmr;
705 unsigned long timeout = 0;
706
707 /* Ask for automatic clear of errors */
708 tfmr = base_tfmr | SPR_TFMR_CLEAR_TB_ERRORS;
709
710 /* Additionally pHyp sets these (write-1-to-clear ?) */
711 tfmr |= SPR_TFMR_TB_MISSING_SYNC;
712 tfmr |= SPR_TFMR_TB_MISSING_STEP;
713 tfmr |= SPR_TFMR_TB_RESIDUE_ERR;
714 mtspr(SPR_TFMR, tfmr);
715
716 /* We have to write "Clear TB Errors" again */
717 tfmr = base_tfmr | SPR_TFMR_CLEAR_TB_ERRORS;
718 mtspr(SPR_TFMR, tfmr);
719
720 do {
721 if (++timeout >= TIMEOUT_LOOPS) {
722 /* Don't actually do anything on error for
723 * now ... not much we can do, panic maybe ?
724 */
725 prerror("TB error reset timeout !\n");
726 return false;
727 }
728 tfmr = mfspr(SPR_TFMR);
729 if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
730 prerror("TB error reset: corrupt TFMR !\n");
731 return false;
732 }
733 } while (tfmr & SPR_TFMR_CLEAR_TB_ERRORS);
734 return true;
735 }
736
chiptod_cleanup_thread_tfmr(void)737 static void chiptod_cleanup_thread_tfmr(void)
738 {
739 uint64_t tfmr = base_tfmr;
740
741 tfmr |= SPR_TFMR_PURR_PARITY_ERR;
742 tfmr |= SPR_TFMR_SPURR_PARITY_ERR;
743 tfmr |= SPR_TFMR_DEC_PARITY_ERR;
744 tfmr |= SPR_TFMR_TFMR_CORRUPT;
745 tfmr |= SPR_TFMR_PURR_OVERFLOW;
746 tfmr |= SPR_TFMR_SPURR_OVERFLOW;
747 mtspr(SPR_TFMR, tfmr);
748 }
749
chiptod_reset_tod_errors(void)750 static void chiptod_reset_tod_errors(void)
751 {
752 uint64_t terr;
753
754 /*
755 * At boot, we clear the errors that the firmware is
756 * supposed to handle. List provided by the pHyp folks.
757 */
758
759 terr = TOD_ERR_CRITC_PARITY;
760 terr |= TOD_ERR_PSS_HAMMING_DISTANCE;
761 terr |= TOD_ERR_DELAY_COMPL_PARITY;
762 terr |= TOD_ERR_CTCR_PARITY;
763 terr |= TOD_ERR_TOD_SYNC_CHECK;
764 terr |= TOD_ERR_TOD_FSM_PARITY;
765 terr |= TOD_ERR_TOD_REGISTER_PARITY;
766
767 if (xscom_writeme(TOD_ERROR, terr)) {
768 prerror("XSCOM error writing TOD_ERROR !\n");
769 /* Not much we can do here ... abort ? */
770 }
771 }
772
chiptod_sync_master(void * data)773 static void chiptod_sync_master(void *data)
774 {
775 uint64_t initial_tb_value;
776 bool *result = data;
777
778 prlog(PR_DEBUG, "Master sync on CPU PIR 0x%04x...\n",
779 this_cpu()->pir);
780
781 /* Apply base tfmr */
782 mtspr(SPR_TFMR, base_tfmr);
783
784 /* From recipe provided by pHyp folks, reset various errors
785 * before attempting the sync
786 */
787 chiptod_reset_tb_errors();
788
789 /* Cleanup thread tfmr bits */
790 chiptod_cleanup_thread_tfmr();
791
792 /* Reset errors in the chiptod itself */
793 chiptod_reset_tod_errors();
794
795 /* Switch timebase to "Not Set" state */
796 if (!chiptod_mod_tb())
797 goto error;
798 prlog(PR_INSANE, "SYNC MASTER Step 2 TFMR=0x%016lx\n", mfspr(SPR_TFMR));
799
800 /* Chip TOD step checkers enable */
801 if (xscom_writeme(TOD_TTYPE_2, PPC_BIT(0))) {
802 prerror("XSCOM error enabling steppers\n");
803 goto error;
804 }
805
806 prlog(PR_INSANE, "SYNC MASTER Step 3 TFMR=0x%016lx\n", mfspr(SPR_TFMR));
807
808 /* Chip TOD interrupt check */
809 if (!chiptod_interrupt_check())
810 goto error;
811 prlog(PR_INSANE, "SYNC MASTER Step 4 TFMR=0x%016lx\n", mfspr(SPR_TFMR));
812
813 /* Switch local chiptod to "Not Set" state */
814 if (xscom_writeme(TOD_LOAD_TOD_MOD, PPC_BIT(0))) {
815 prerror("XSCOM error sending LOAD_TOD_MOD\n");
816 goto error;
817 }
818
819 /* Switch all remote chiptod to "Not Set" state */
820 if (xscom_writeme(TOD_TTYPE_5, PPC_BIT(0))) {
821 prerror("XSCOM error sending TTYPE_5\n");
822 goto error;
823 }
824
825 /*
826 * Load the master's current timebase value into the Chip TOD
827 * network. This is so we have sane timestamps across the whole
828 * IPL process. The Chip TOD documentation says that the loaded
829 * value needs to be one STEP before a SYNC. In other words,
830 * set the low bits to 0x1ff0.
831 */
832 initial_tb_value = (mftb() & ~0x1fff) | 0x1ff0;
833
834 /* Chip TOD load initial value */
835 if (xscom_writeme(TOD_CHIPTOD_LOAD_TB, initial_tb_value)) {
836 prerror("XSCOM error setting init TB\n");
837 goto error;
838 }
839
840 prlog(PR_INSANE, "SYNC MASTER Step 5 TFMR=0x%016lx\n", mfspr(SPR_TFMR));
841
842 if (!chiptod_poll_running())
843 goto error;
844 prlog(PR_INSANE, "SYNC MASTER Step 6 TFMR=0x%016lx\n", mfspr(SPR_TFMR));
845
846 /* Move chiptod value to core TB */
847 if (!chiptod_to_tb())
848 goto error;
849 prlog(PR_INSANE, "SYNC MASTER Step 7 TFMR=0x%016lx\n", mfspr(SPR_TFMR));
850
851 /* Send local chip TOD to all chips TOD */
852 if (xscom_writeme(TOD_TTYPE_4, PPC_BIT(0))) {
853 prerror("XSCOM error sending TTYPE_4\n");
854 goto error;
855 }
856
857 /* Check if TB is running */
858 if (!chiptod_check_tb_running())
859 goto error;
860
861 prlog(PR_INSANE, "Master sync completed, TB=%lx\n", mfspr(SPR_TBRL));
862
863 /*
864 * A little delay to make sure the remote chips get up to
865 * speed before we start syncing them.
866 *
867 * We have to do it here because we know our TB is running
868 * while the boot thread TB might not yet.
869 */
870 time_wait_ms(1);
871
872 *result = true;
873 return;
874 error:
875 prerror("Master sync failed! TFMR=0x%016lx\n", mfspr(SPR_TFMR));
876 *result = false;
877 }
878
chiptod_sync_slave(void * data)879 static void chiptod_sync_slave(void *data)
880 {
881 bool *result = data;
882
883 /* Only get primaries, not threads */
884 if (this_cpu()->is_secondary) {
885 /* On secondaries we just cleanup the TFMR */
886 chiptod_cleanup_thread_tfmr();
887 *result = true;
888 return;
889 }
890
891 prlog(PR_DEBUG, "Slave sync on CPU PIR 0x%04x...\n",
892 this_cpu()->pir);
893
894 /* Apply base tfmr */
895 mtspr(SPR_TFMR, base_tfmr);
896
897 /* From recipe provided by pHyp folks, reset various errors
898 * before attempting the sync
899 */
900 chiptod_reset_tb_errors();
901
902 /* Cleanup thread tfmr bits */
903 chiptod_cleanup_thread_tfmr();
904
905 /* Switch timebase to "Not Set" state */
906 if (!chiptod_mod_tb())
907 goto error;
908 prlog(PR_INSANE, "SYNC SLAVE Step 2 TFMR=0x%016lx\n", mfspr(SPR_TFMR));
909
910 /* Chip TOD running check */
911 if (!chiptod_poll_running())
912 goto error;
913 prlog(PR_INSANE, "SYNC SLAVE Step 3 TFMR=0x%016lx\n", mfspr(SPR_TFMR));
914
915 /* Chip TOD interrupt check */
916 if (!chiptod_interrupt_check())
917 goto error;
918 prlog(PR_INSANE, "SYNC SLAVE Step 4 TFMR=0x%016lx\n", mfspr(SPR_TFMR));
919
920 /* Move chiptod value to core TB */
921 if (!chiptod_to_tb())
922 goto error;
923 prlog(PR_INSANE, "SYNC SLAVE Step 5 TFMR=0x%016lx\n", mfspr(SPR_TFMR));
924
925 /* Check if TB is running */
926 if (!chiptod_check_tb_running())
927 goto error;
928
929 prlog(PR_INSANE, "Slave sync completed, TB=%lx\n", mfspr(SPR_TBRL));
930
931 *result = true;
932 return;
933 error:
934 prerror("Slave sync failed ! TFMR=0x%016lx\n", mfspr(SPR_TFMR));
935 *result = false;
936 }
937
chiptod_wakeup_resync(void)938 bool chiptod_wakeup_resync(void)
939 {
940 if (chiptod_primary < 0)
941 return 0;
942
943 lock(&chiptod_lock);
944
945 /* Apply base tfmr */
946 mtspr(SPR_TFMR, base_tfmr);
947
948 /* From recipe provided by pHyp folks, reset various errors
949 * before attempting the sync
950 */
951 chiptod_reset_tb_errors();
952
953 /* Cleanup thread tfmr bits */
954 chiptod_cleanup_thread_tfmr();
955
956 /* Switch timebase to "Not Set" state */
957 if (!chiptod_mod_tb())
958 goto error;
959
960 /* Move chiptod value to core TB */
961 if (!chiptod_to_tb())
962 goto error;
963
964 unlock(&chiptod_lock);
965
966 return true;
967 error:
968 prerror("Resync failed ! TFMR=0x%16lx\n", mfspr(SPR_TFMR));
969 unlock(&chiptod_lock);
970 return false;
971 }
972
__chiptod_recover_tod_errors(void)973 static int __chiptod_recover_tod_errors(void)
974 {
975 uint64_t terr;
976 uint64_t treset = 0;
977 int i, rc = -1;
978 int32_t chip_id = this_cpu()->chip_id;
979
980 /* Read TOD error register */
981 if (xscom_readme(TOD_ERROR, &terr)) {
982 prerror("XSCOM error reading TOD_ERROR reg\n");
983 return 0;
984 }
985 /* Check for sync check error and recover */
986 if ((terr & TOD_ERR_TOD_SYNC_CHECK) ||
987 (terr & TOD_ERR_TOD_FSM_PARITY) ||
988 (terr & TOD_ERR_CTCR_PARITY) ||
989 (terr & TOD_ERR_PSS_HAMMING_DISTANCE) ||
990 (terr & TOD_ERR_DELAY_COMPL_PARITY) ||
991 (terr & TOD_ERR_TOD_REGISTER_PARITY)) {
992 chiptod_reset_tod_errors();
993 rc = 1;
994 }
995
996 /*
997 * Check for TOD control register parity errors and restore those
998 * registers with last saved valid values.
999 */
1000 for (i = 0; i < ARRAY_SIZE(chiptod_tod_regs); i++) {
1001 if (!(terr & chiptod_tod_regs[i].error_bit))
1002 continue;
1003
1004 /* Check if we have valid last saved register value. */
1005 if (!chiptod_tod_regs[i].val[chip_id].valid) {
1006 prerror("Failed to restore TOD register: %08llx",
1007 chiptod_tod_regs[i].xscom_addr);
1008 return 0;
1009 }
1010
1011 prlog(PR_DEBUG, "Parity error, Restoring TOD register: "
1012 "%08llx\n", chiptod_tod_regs[i].xscom_addr);
1013 if (xscom_writeme(chiptod_tod_regs[i].xscom_addr,
1014 chiptod_tod_regs[i].val[chip_id].data)) {
1015 prerror("XSCOM error writing 0x%08llx reg.\n",
1016 chiptod_tod_regs[i].xscom_addr);
1017 return 0;
1018 }
1019 treset |= chiptod_tod_regs[i].error_bit;
1020 }
1021
1022 if (treset && (xscom_writeme(TOD_ERROR, treset))) {
1023 prerror("XSCOM error writing TOD_ERROR !\n");
1024 return 0;
1025 }
1026 /* We have handled all the TOD errors routed to hypervisor */
1027 if (treset)
1028 rc = 1;
1029 return rc;
1030 }
1031
chiptod_recover_tod_errors(void)1032 int chiptod_recover_tod_errors(void)
1033 {
1034 int rc;
1035
1036 lock(&chiptod_lock);
1037 rc = __chiptod_recover_tod_errors();
1038 unlock(&chiptod_lock);
1039 return rc;
1040 }
1041
chiptod_get_active_master(void)1042 static int32_t chiptod_get_active_master(void)
1043 {
1044 if (current_topology < 0)
1045 return -1;
1046
1047 if (chiptod_topology_info[current_topology].status ==
1048 chiptod_active_master)
1049 return chiptod_topology_info[current_topology].id;
1050 return -1;
1051 }
1052
1053 /* Return true if Active master TOD is running. */
chiptod_master_running(void)1054 static bool chiptod_master_running(void)
1055 {
1056 int32_t active_master_chip;
1057
1058 active_master_chip = chiptod_get_active_master();
1059 if (active_master_chip != -1) {
1060 if (chiptod_running_check(active_master_chip))
1061 return true;
1062 }
1063 return false;
1064 }
1065
chiptod_set_ttype4_mode(struct proc_chip * chip,bool enable)1066 static bool chiptod_set_ttype4_mode(struct proc_chip *chip, bool enable)
1067 {
1068 uint64_t tval;
1069
1070 /* Sanity check */
1071 if (!chip)
1072 return false;
1073
1074 if (xscom_read(chip->id, TOD_PIB_MASTER, &tval)) {
1075 prerror("XSCOM error reading PIB_MASTER\n");
1076 return false;
1077 }
1078
1079 if (enable) {
1080 /*
1081 * Enable TTYPE4 send mode. This allows TOD to respond to
1082 * TTYPE3 request.
1083 */
1084 tval |= TOD_PIBM_TTYPE4_SEND_MODE;
1085 tval |= TOD_PIBM_TTYPE4_SEND_ENBL;
1086 } else {
1087 /* Disable TTYPE4 send mode. */
1088 tval &= ~TOD_PIBM_TTYPE4_SEND_MODE;
1089 tval &= ~TOD_PIBM_TTYPE4_SEND_ENBL;
1090 }
1091
1092 if (xscom_write(chip->id, TOD_PIB_MASTER, tval)) {
1093 prerror("XSCOM error writing PIB_MASTER\n");
1094 return false;
1095 }
1096 return true;
1097 }
1098
1099 /* Stop TODs on slave chips in backup topology. */
chiptod_stop_slave_tods(void)1100 static void chiptod_stop_slave_tods(void)
1101 {
1102 struct proc_chip *chip = NULL;
1103 enum chiptod_topology backup_topo;
1104 uint64_t terr = 0;
1105
1106 /* Inject TOD sync check error on salve TODs to stop them. */
1107 terr |= TOD_ERR_TOD_SYNC_CHECK;
1108
1109 if (current_topology == chiptod_topo_primary)
1110 backup_topo = chiptod_topo_secondary;
1111 else
1112 backup_topo = chiptod_topo_primary;
1113
1114 for_each_chip(chip) {
1115 enum chiptod_chip_role role;
1116
1117 /* Current chip TOD is already in stooped state */
1118 if (chip->id == this_cpu()->chip_id)
1119 continue;
1120
1121 role = chiptod_get_chip_role(backup_topo, chip->id);
1122
1123 /* Skip backup master chip TOD. */
1124 if (role == chiptod_chip_role_MDMT)
1125 continue;
1126
1127 if (xscom_write(chip->id, TOD_ERROR_INJECT, terr))
1128 prerror("XSCOM error writing TOD_ERROR_INJ\n");
1129
1130 if (chiptod_running_check(chip->id)) {
1131 prlog(PR_DEBUG,
1132 "Failed to stop TOD on slave CHIP [%d]\n",
1133 chip->id);
1134 }
1135 }
1136 }
1137
is_topology_switch_required(void)1138 static bool is_topology_switch_required(void)
1139 {
1140 int32_t active_master_chip;
1141 uint64_t tod_error;
1142
1143 active_master_chip = chiptod_get_active_master();
1144
1145 /* Check if TOD is running on Active master. */
1146 if (chiptod_master_running())
1147 return false;
1148
1149 /*
1150 * Check if sync/step network is running.
1151 *
1152 * If sync/step network is not running on current active topology
1153 * then we need switch topology to recover from TOD error.
1154 */
1155 if (!chiptod_sync_step_check_running(current_topology)) {
1156 prlog(PR_DEBUG, "Sync/Step network not running\n");
1157 return true;
1158 }
1159
1160 /*
1161 * Check if there is a step check error reported on
1162 * Active master.
1163 */
1164 if (xscom_read(active_master_chip, TOD_ERROR, &tod_error)) {
1165 prerror("XSCOM error reading TOD_ERROR reg\n");
1166 /*
1167 * Can't do anything here. But we already found that
1168 * sync/step network is running. Hence return false.
1169 */
1170 return false;
1171 }
1172
1173 if (tod_error & TOD_ERR_MP0_STEP_CHECK) {
1174 prlog(PR_DEBUG, "TOD step check error\n");
1175 return true;
1176 }
1177
1178 return false;
1179 }
1180
chiptod_backup_valid(void)1181 static bool chiptod_backup_valid(void)
1182 {
1183 enum chiptod_topology backup_topo;
1184
1185 if (current_topology < 0)
1186 return false;
1187
1188 if (current_topology == chiptod_topo_primary)
1189 backup_topo = chiptod_topo_secondary;
1190 else
1191 backup_topo = chiptod_topo_primary;
1192
1193 if (chiptod_topology_info[backup_topo].status == chiptod_backup_master)
1194 return chiptod_sync_step_check_running(backup_topo);
1195
1196 return false;
1197 }
1198
chiptod_topology_switch_complete(void)1199 static void chiptod_topology_switch_complete(void)
1200 {
1201 /*
1202 * After the topology switch, we may have a non-functional backup
1203 * topology, and we won't be able to recover from future TOD errors
1204 * that requires topology switch. Someone needs to either fix it OR
1205 * configure new functional backup topology.
1206 *
1207 * Bit 18 of the Pervasive FIR is used to signal that TOD error
1208 * analysis needs to be performed. This allows FSP/PRD to
1209 * investigate and re-configure new backup topology if required.
1210 * Once new backup topology is configured and ready, FSP sends a
1211 * mailbox command xE6, s/c 0x06, mod 0, to enable the backup
1212 * topology.
1213 *
1214 * This isn't documented anywhere. This info is provided by FSP
1215 * folks.
1216 */
1217 if (xscom_writeme(LOCAL_CORE_FIR, LFIR_SWITCH_COMPLETE)) {
1218 prerror("XSCOM error writing LOCAL_CORE_FIR\n");
1219 return;
1220 }
1221
1222 /* Save TOD control registers values. */
1223 chiptod_cache_tod_registers();
1224
1225 prlog(PR_DEBUG, "Topology switch complete\n");
1226 print_topology_info();
1227 }
1228
1229 /*
1230 * Sync up TOD with other chips and get TOD in running state.
1231 * Check if current topology is active and running. If not, then
1232 * trigger a topology switch.
1233 */
chiptod_start_tod(void)1234 static int chiptod_start_tod(void)
1235 {
1236 struct proc_chip *chip = NULL;
1237
1238 /* Do a topology switch if required. */
1239 if (is_topology_switch_required()) {
1240 int32_t mchip = chiptod_get_active_master();
1241
1242 prlog(PR_DEBUG, "Need topology switch to recover\n");
1243 /*
1244 * There is a failure in StepSync network in current
1245 * active topology. TOD is not running on active master chip.
1246 * We need to sync with backup master chip TOD.
1247 * But before we do that we need to switch topology to make
1248 * backup master as the new active master. Once we switch the
1249 * topology we can then request TOD value from new active
1250 * master. But make sure we move local chiptod to Not Set
1251 * before requesting TOD value.
1252 *
1253 * Before triggering a topology switch, check if backup
1254 * is valid and stop all slave TODs in backup topology.
1255 */
1256 if (!chiptod_backup_valid()) {
1257 prerror("Backup master is not enabled. "
1258 "Can not do a topology switch.\n");
1259 goto error_out;
1260 }
1261
1262 chiptod_stop_slave_tods();
1263
1264 if (xscom_write(mchip, TOD_TTYPE_1, PPC_BIT(0))) {
1265 prerror("XSCOM error switching primary/secondary\n");
1266 goto error_out;
1267 }
1268
1269 /* Update topology info. */
1270 current_topology = query_current_topology();
1271 chiptod_update_topology(chiptod_topo_primary);
1272 chiptod_update_topology(chiptod_topo_secondary);
1273
1274 /*
1275 * We just switched topologies to recover.
1276 * Check if new master TOD is running.
1277 */
1278 if (!chiptod_master_running()) {
1279 prerror("TOD is not running on new master.\n");
1280 goto error_out;
1281 }
1282
1283 /*
1284 * Enable step checkers on all Chip TODs
1285 *
1286 * During topology switch, step checkers are disabled
1287 * on all Chip TODs by default. Enable them.
1288 */
1289 if (xscom_writeme(TOD_TTYPE_2, PPC_BIT(0))) {
1290 prerror("XSCOM error enabling steppers\n");
1291 goto error_out;
1292 }
1293
1294 chiptod_topology_switch_complete();
1295 }
1296
1297 if (!chiptod_master_running()) {
1298 /*
1299 * Active Master TOD is not running, which means it won't
1300 * respond to TTYPE_3 request.
1301 *
1302 * Find a chip that has TOD in running state and configure
1303 * it to respond to TTYPE_3 request.
1304 */
1305 for_each_chip(chip) {
1306 if (chiptod_running_check(chip->id)) {
1307 if (chiptod_set_ttype4_mode(chip, true))
1308 break;
1309 }
1310 }
1311 }
1312
1313 /* Switch local chiptod to "Not Set" state */
1314 if (xscom_writeme(TOD_LOAD_TOD_MOD, PPC_BIT(0))) {
1315 prerror("XSCOM error sending LOAD_TOD_MOD\n");
1316 goto error_out;
1317 }
1318
1319 /*
1320 * Request the current TOD value from another chip.
1321 * This will move TOD in running state
1322 */
1323 if (xscom_writeme(TOD_TTYPE_3, PPC_BIT(0))) {
1324 prerror("XSCOM error sending TTYPE_3\n");
1325 goto error_out;
1326 }
1327
1328 /* Check if chip TOD is running. */
1329 if (!chiptod_poll_running())
1330 goto error_out;
1331
1332 /* Restore the ttype4_mode. */
1333 chiptod_set_ttype4_mode(chip, false);
1334 return 1;
1335
1336 error_out:
1337 chiptod_unrecoverable = true;
1338 return 0;
1339 }
1340
tfmr_recover_tb_errors(uint64_t tfmr)1341 static bool tfmr_recover_tb_errors(uint64_t tfmr)
1342 {
1343 uint64_t tfmr_reset_error;
1344 unsigned long timeout = 0;
1345
1346 /* Ask for automatic clear of errors */
1347 tfmr_reset_error = base_tfmr | SPR_TFMR_CLEAR_TB_ERRORS;
1348
1349 /* Additionally pHyp sets these (write-1-to-clear ?) */
1350 if (tfmr & SPR_TFMR_TB_MISSING_SYNC)
1351 tfmr_reset_error |= SPR_TFMR_TB_MISSING_SYNC;
1352
1353 if (tfmr & SPR_TFMR_TB_MISSING_STEP)
1354 tfmr_reset_error |= SPR_TFMR_TB_MISSING_STEP;
1355
1356 /*
1357 * write 1 to bit 45 to clear TB residue the error.
1358 * TB register has already been reset to zero as part pre-recovery.
1359 */
1360 if (tfmr & SPR_TFMR_TB_RESIDUE_ERR)
1361 tfmr_reset_error |= SPR_TFMR_TB_RESIDUE_ERR;
1362
1363 if (tfmr & SPR_TFMR_FW_CONTROL_ERR)
1364 tfmr_reset_error |= SPR_TFMR_FW_CONTROL_ERR;
1365
1366 if (tfmr & SPR_TFMR_TBST_CORRUPT)
1367 tfmr_reset_error |= SPR_TFMR_TBST_CORRUPT;
1368
1369 mtspr(SPR_TFMR, tfmr_reset_error);
1370
1371 /* We have to write "Clear TB Errors" again */
1372 tfmr_reset_error = base_tfmr | SPR_TFMR_CLEAR_TB_ERRORS;
1373 mtspr(SPR_TFMR, tfmr_reset_error);
1374
1375 do {
1376 if (++timeout >= TIMEOUT_LOOPS) {
1377 prerror("TB error reset timeout !\n");
1378 return false;
1379 }
1380 tfmr = mfspr(SPR_TFMR);
1381 if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
1382 prerror("TB error reset: corrupt TFMR !\n");
1383 return false;
1384 }
1385 } while (tfmr & SPR_TFMR_CLEAR_TB_ERRORS);
1386 return true;
1387 }
1388
tfmr_recover_local_errors(uint64_t tfmr)1389 bool tfmr_recover_local_errors(uint64_t tfmr)
1390 {
1391 uint64_t tfmr_reset_errors = 0;
1392
1393 if (tfmr & SPR_TFMR_DEC_PARITY_ERR) {
1394 /* Set DEC with all ones */
1395 mtspr(SPR_DEC, ~0);
1396
1397 /* set bit 59 to clear TFMR DEC parity error. */
1398 tfmr_reset_errors |= SPR_TFMR_DEC_PARITY_ERR;
1399 }
1400
1401 /*
1402 * Reset PURR/SPURR to recover. We also need help from KVM
1403 * layer to handle this change in PURR/SPURR. That needs
1404 * to be handled in kernel KVM layer. For now, to recover just
1405 * reset it.
1406 */
1407 if (tfmr & SPR_TFMR_PURR_PARITY_ERR) {
1408 /* set PURR register with sane value or reset it. */
1409 mtspr(SPR_PURR, 0);
1410
1411 /* set bit 57 to clear TFMR PURR parity error. */
1412 tfmr_reset_errors |= SPR_TFMR_PURR_PARITY_ERR;
1413 }
1414
1415 if (tfmr & SPR_TFMR_SPURR_PARITY_ERR) {
1416 /* set PURR register with sane value or reset it. */
1417 mtspr(SPR_SPURR, 0);
1418
1419 /* set bit 58 to clear TFMR PURR parity error. */
1420 tfmr_reset_errors |= SPR_TFMR_SPURR_PARITY_ERR;
1421 }
1422
1423 /* Write TFMR twice to clear the error */
1424 mtspr(SPR_TFMR, base_tfmr | tfmr_reset_errors);
1425 mtspr(SPR_TFMR, base_tfmr | tfmr_reset_errors);
1426
1427 /* Get fresh copy of TFMR */
1428 tfmr = mfspr(SPR_TFMR);
1429
1430 /* Check if TFMR non-TB errors still present. */
1431 if (tfmr & tfmr_reset_errors) {
1432 prerror("TFMR non-TB error recovery failed! "
1433 "TFMR=0x%016lx\n", mfspr(SPR_TFMR));
1434 return false;
1435 }
1436 return true;
1437 }
1438
1439 /*
1440 * TFMR parity error recovery as per pc_workbook:
1441 * MT(TFMR) bits 11 and 60 are b’1’
1442 * MT(HMER) all bits 1 except for bits 4,5
1443 */
recover_corrupt_tfmr(void)1444 bool recover_corrupt_tfmr(void)
1445 {
1446 uint64_t tfmr;
1447
1448 /* Get the base TFMR */
1449 tfmr = base_tfmr;
1450
1451 /* Set bit 60 to clear TFMR parity error. */
1452 tfmr |= SPR_TFMR_TFMR_CORRUPT;
1453 mtspr(SPR_TFMR, tfmr);
1454
1455 /* Write twice to clear the error */
1456 mtspr(SPR_TFMR, tfmr);
1457
1458 /* Get fresh copy of TFMR */
1459 tfmr = mfspr(SPR_TFMR);
1460
1461 /* Check if TFMR parity error still present. */
1462 if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
1463 prerror("TFMR error recovery: corrupt TFMR !\n");
1464 return false;
1465 }
1466
1467 /*
1468 * Now that we have sane value in TFMR, check if Timebase machine
1469 * state is in ERROR state. If yes, clear TB errors so that
1470 * Timebase machine state changes to RESET state. Once in RESET state
1471 * then we can then load TB with TOD value.
1472 */
1473 if (GETFIELD(SPR_TFMR_TBST_ENCODED, tfmr) == TBST_STATE_ERROR) {
1474 if (!chiptod_reset_tb_errors())
1475 return false;
1476 }
1477 return true;
1478 }
1479
tfmr_cleanup_core_errors(uint64_t tfmr)1480 void tfmr_cleanup_core_errors(uint64_t tfmr)
1481 {
1482 /* If HDEC is bad, clean it on all threads before we clear the
1483 * error condition.
1484 */
1485 if (tfmr & SPR_TFMR_HDEC_PARITY_ERROR)
1486 mtspr(SPR_HDEC, 0);
1487
1488 /* If TB is invalid, clean it on all threads as well, it will be
1489 * restored after the next rendez-vous
1490 */
1491 if (!(tfmr & SPR_TFMR_TB_VALID)) {
1492 mtspr(SPR_TBWU, 0);
1493 mtspr(SPR_TBWU, 0);
1494 }
1495 }
1496
tfmr_clear_core_errors(uint64_t tfmr)1497 int tfmr_clear_core_errors(uint64_t tfmr)
1498 {
1499 uint64_t tfmr_reset_errors = 0;
1500
1501 /* return -1 if there is nothing to be fixed. */
1502 if (!(tfmr & SPR_TFMR_HDEC_PARITY_ERROR))
1503 return -1;
1504
1505 tfmr_reset_errors |= SPR_TFMR_HDEC_PARITY_ERROR;
1506
1507 /* Write TFMR twice to clear the error */
1508 mtspr(SPR_TFMR, base_tfmr | tfmr_reset_errors);
1509 mtspr(SPR_TFMR, base_tfmr | tfmr_reset_errors);
1510
1511 return 1;
1512 }
1513
1514 /*
1515 * Recover from TB and TOD errors.
1516 * Timebase register is per core and first thread that gets chance to
1517 * handle interrupt would fix actual TFAC errors and rest of the threads
1518 * from same core would see no errors. Return -1 if no errors have been
1519 * found. The caller (handle_hmi_exception) of this function would not
1520 * send an HMI event to host if return value is -1.
1521 *
1522 * Return values:
1523 * 0 <= Failed to recover from errors
1524 * 1 <= Successfully recovered from errors
1525 * -1 <= No errors found. Errors are already been fixed.
1526 */
chiptod_recover_tb_errors(bool * out_resynced)1527 int chiptod_recover_tb_errors(bool *out_resynced)
1528 {
1529 uint64_t tfmr;
1530 int rc = -1;
1531
1532 *out_resynced = false;
1533
1534 if (chiptod_primary < 0)
1535 return 0;
1536
1537 lock(&chiptod_lock);
1538
1539 /*
1540 * Return if TOD is unrecoverable.
1541 * The previous attempt to recover TOD has been failed.
1542 */
1543 if (chiptod_unrecoverable) {
1544 rc = 0;
1545 goto error_out;
1546 }
1547
1548 /* Get fresh copy of TFMR */
1549 tfmr = mfspr(SPR_TFMR);
1550
1551 /*
1552 * Check for TB errors.
1553 * On Sync check error, bit 44 of TFMR is set. Check for it and
1554 * clear it.
1555 *
1556 * In some rare situations we may have all TB errors already cleared,
1557 * but TB stuck in waiting for new value from TOD with TFMR bit 18
1558 * set to '1'. This uncertain state of TB would fail the process
1559 * of getting TB back into running state. Get TB in clean initial
1560 * state by clearing TB errors if TFMR[18] is set.
1561 */
1562 if ((tfmr & SPR_TFMR_TB_MISSING_STEP) ||
1563 (tfmr & SPR_TFMR_TB_RESIDUE_ERR) ||
1564 (tfmr & SPR_TFMR_FW_CONTROL_ERR) ||
1565 (tfmr & SPR_TFMR_TBST_CORRUPT) ||
1566 (tfmr & SPR_TFMR_MOVE_CHIP_TOD_TO_TB) ||
1567 (tfmr & SPR_TFMR_TB_MISSING_SYNC)) {
1568 if (!tfmr_recover_tb_errors(tfmr)) {
1569 rc = 0;
1570 goto error_out;
1571 }
1572 }
1573
1574 /*
1575 * Check for TOD sync check error.
1576 * On TOD errors, bit 51 of TFMR is set. If this bit is on then we
1577 * need to fetch TOD error register and recover from TOD errors.
1578 * Bit 33 of TOD error register indicates sync check error.
1579 */
1580 if (tfmr & SPR_TFMR_CHIP_TOD_INTERRUPT)
1581 rc = __chiptod_recover_tod_errors();
1582
1583 /* Check if TB is running. If not then we need to get it running. */
1584 if (!(tfmr & SPR_TFMR_TB_VALID)) {
1585 rc = 0;
1586
1587 /* Place TB in Notset state. */
1588 if (!chiptod_mod_tb())
1589 goto error_out;
1590
1591 /*
1592 * Before we move TOD to core TB check if TOD is running.
1593 * If not, then get TOD in running state.
1594 */
1595 if (!chiptod_running_check(this_cpu()->chip_id))
1596 if (!chiptod_start_tod())
1597 goto error_out;
1598
1599 /* Move chiptod value to core TB */
1600 if (!chiptod_to_tb())
1601 goto error_out;
1602
1603 *out_resynced = true;
1604
1605 /* We have successfully able to get TB running. */
1606 rc = 1;
1607 }
1608
1609 error_out:
1610 unlock(&chiptod_lock);
1611 return rc;
1612 }
1613
opal_resync_timebase(void)1614 static int64_t opal_resync_timebase(void)
1615 {
1616 /* Mambo and qemu doesn't simulate the chiptod */
1617 if (chip_quirk(QUIRK_NO_CHIPTOD))
1618 return OPAL_SUCCESS;
1619
1620 if (!chiptod_wakeup_resync()) {
1621 prerror("OPAL: Resync timebase failed on CPU 0x%04x\n",
1622 this_cpu()->pir);
1623 return OPAL_HARDWARE;
1624 }
1625 return OPAL_SUCCESS;
1626 }
1627 opal_call(OPAL_RESYNC_TIMEBASE, opal_resync_timebase, 0);
1628
chiptod_print_tb(void * data __unused)1629 static void chiptod_print_tb(void *data __unused)
1630 {
1631 prlog(PR_DEBUG, "PIR 0x%04x TB=%lx\n", this_cpu()->pir,
1632 mfspr(SPR_TBRL));
1633 }
1634
chiptod_probe(void)1635 static bool chiptod_probe(void)
1636 {
1637 struct dt_node *np;
1638
1639 dt_for_each_compatible(dt_root, np, "ibm,power-chiptod") {
1640 uint32_t chip;
1641
1642 /* Old DT has chip-id in chiptod node, newer only in the
1643 * parent xscom bridge
1644 */
1645 chip = dt_get_chip_id(np);
1646
1647 if (dt_has_node_property(np, "primary", NULL)) {
1648 chiptod_primary = chip;
1649 if (dt_node_is_compatible(np, "ibm,power8-chiptod"))
1650 chiptod_type = chiptod_p8;
1651 if (dt_node_is_compatible(np, "ibm,power9-chiptod"))
1652 chiptod_type = chiptod_p9;
1653 }
1654
1655 if (dt_has_node_property(np, "secondary", NULL))
1656 chiptod_secondary = chip;
1657
1658 }
1659
1660 if (chiptod_type == chiptod_unknown) {
1661 prerror("Unknown TOD type !\n");
1662 return false;
1663 }
1664
1665 return true;
1666 }
1667
chiptod_discover_new_backup(enum chiptod_topology topo)1668 static void chiptod_discover_new_backup(enum chiptod_topology topo)
1669 {
1670 struct proc_chip *chip = NULL;
1671
1672 /* Scan through available chips to find new backup master chip */
1673 for_each_chip(chip) {
1674 if (_chiptod_get_chip_status(chip->id) == chiptod_backup_master)
1675 break;
1676 }
1677
1678 /* Found new backup master chip. Update the topology info */
1679 if (chip) {
1680 prlog(PR_DEBUG, "New backup master: CHIP [%d]\n",
1681 chip->id);
1682
1683 if (topo == chiptod_topo_primary)
1684 chiptod_primary = chip->id;
1685 else
1686 chiptod_secondary = chip->id;
1687 chiptod_topology_info[topo].id = chip->id;
1688 chiptod_update_topology(topo);
1689
1690 prlog(PR_DEBUG,
1691 "Backup topology configuration changed.\n");
1692 print_topology_info();
1693 }
1694
1695 /*
1696 * Topology configuration has changed. Save TOD control registers
1697 * values.
1698 */
1699 chiptod_cache_tod_registers();
1700 }
1701
1702 /*
1703 * Enable/disable backup topology.
1704 * If request is to enable topology, then discover new backup master
1705 * chip and update the topology configuration info. If the request is
1706 * to disable topology, then mark the current backup topology as disabled.
1707 * Return error (-1) if the action is requested on currenlty active
1708 * topology.
1709 *
1710 * Return values:
1711 * true <= Success
1712 * false <= Topology is active and in use.
1713 */
chiptod_adjust_topology(enum chiptod_topology topo,bool enable)1714 bool chiptod_adjust_topology(enum chiptod_topology topo, bool enable)
1715 {
1716 uint8_t rc = true;
1717 /*
1718 * The FSP can only request that the currently inactive topology
1719 * be disabled or enabled. If the requested topology is currently
1720 * the active topology, then fail this request with a -1 (TOD
1721 * topology in use) status as return code.
1722 */
1723 lock(&chiptod_lock);
1724 if (topo == current_topology) {
1725 rc = false;
1726 goto out;
1727 }
1728
1729 if (enable)
1730 chiptod_discover_new_backup(topo);
1731 else
1732 chiptod_topology_info[topo].status = chiptod_backup_disabled;
1733 out:
1734 unlock(&chiptod_lock);
1735 return rc;
1736 }
1737
chiptod_init_topology_info(void)1738 static void chiptod_init_topology_info(void)
1739 {
1740 /* Find and update current topology in use. */
1741 current_topology = query_current_topology();
1742
1743 /* Initialized primary topology chip config info */
1744 chiptod_topology_info[chiptod_topo_primary].id = chiptod_primary;
1745 chiptod_update_topology(chiptod_topo_primary);
1746
1747 /* Initialized secondary topology chip config info */
1748 chiptod_topology_info[chiptod_topo_secondary].id = chiptod_secondary;
1749 chiptod_update_topology(chiptod_topo_secondary);
1750
1751 /* Cache TOD control registers values. */
1752 chiptod_cache_tod_registers();
1753 print_topology_info();
1754 }
1755
chiptod_init(void)1756 void chiptod_init(void)
1757 {
1758 struct cpu_thread *cpu0, *cpu;
1759 bool sres;
1760
1761 /* Mambo and qemu doesn't simulate the chiptod */
1762 if (chip_quirk(QUIRK_NO_CHIPTOD))
1763 return;
1764
1765 op_display(OP_LOG, OP_MOD_CHIPTOD, 0);
1766
1767 if (!chiptod_probe()) {
1768 prerror("Failed ChipTOD detection !\n");
1769 op_display(OP_FATAL, OP_MOD_CHIPTOD, 0);
1770 abort();
1771 }
1772
1773 op_display(OP_LOG, OP_MOD_CHIPTOD, 1);
1774
1775 /* Pick somebody on the primary */
1776 cpu0 = find_cpu_by_chip_id(chiptod_primary);
1777
1778 /* Calculate the base TFMR value used for everybody */
1779 chiptod_setup_base_tfmr();
1780
1781 prlog(PR_DEBUG, "Base TFMR=0x%016llx\n", base_tfmr);
1782
1783 /* Schedule master sync */
1784 sres = false;
1785 cpu_wait_job(cpu_queue_job(cpu0, "chiptod_sync_master",
1786 chiptod_sync_master, &sres), true);
1787 if (!sres) {
1788 op_display(OP_FATAL, OP_MOD_CHIPTOD, 2);
1789 abort();
1790 }
1791
1792 op_display(OP_LOG, OP_MOD_CHIPTOD, 2);
1793
1794 /* Schedule slave sync */
1795 for_each_available_cpu(cpu) {
1796 /* Skip master */
1797 if (cpu == cpu0)
1798 continue;
1799
1800 /* Queue job */
1801 sres = false;
1802 cpu_wait_job(cpu_queue_job(cpu, "chiptod_sync_slave",
1803 chiptod_sync_slave, &sres),
1804 true);
1805 if (!sres) {
1806 op_display(OP_WARN, OP_MOD_CHIPTOD, 3|(cpu->pir << 8));
1807
1808 /* Disable threads */
1809 cpu_disable_all_threads(cpu);
1810 }
1811 op_display(OP_LOG, OP_MOD_CHIPTOD, 3|(cpu->pir << 8));
1812 }
1813
1814 /* Display TBs */
1815 for_each_available_cpu(cpu) {
1816 /* Only do primaries, not threads */
1817 if (cpu->is_secondary)
1818 continue;
1819 cpu_wait_job(cpu_queue_job(cpu, "chiptod_print_tb",
1820 chiptod_print_tb, NULL), true);
1821 }
1822
1823 chiptod_init_topology_info();
1824 op_display(OP_LOG, OP_MOD_CHIPTOD, 4);
1825 }
1826
1827 /* CAPP timebase sync */
1828
chiptod_capp_reset_tb_errors(uint32_t chip_id,uint32_t tfmr_addr,uint32_t offset)1829 static bool chiptod_capp_reset_tb_errors(uint32_t chip_id,
1830 uint32_t tfmr_addr,
1831 uint32_t offset)
1832 {
1833 uint64_t tfmr;
1834 unsigned long timeout = 0;
1835
1836 /* Ask for automatic clear of errors */
1837 tfmr = base_tfmr | SPR_TFMR_CLEAR_TB_ERRORS;
1838
1839 /* Additionally pHyp sets these (write-1-to-clear ?) */
1840 tfmr |= SPR_TFMR_TB_MISSING_SYNC;
1841 tfmr |= SPR_TFMR_TB_MISSING_STEP;
1842 tfmr |= SPR_TFMR_TB_RESIDUE_ERR;
1843 tfmr |= SPR_TFMR_TBST_CORRUPT;
1844 tfmr |= SPR_TFMR_TFMR_CORRUPT;
1845
1846 /* Write CAPP TFMR */
1847 xscom_write(chip_id, tfmr_addr + offset, tfmr);
1848
1849 /* We have to write "Clear TB Errors" again */
1850 tfmr = base_tfmr | SPR_TFMR_CLEAR_TB_ERRORS;
1851 /* Write CAPP TFMR */
1852 xscom_write(chip_id, tfmr_addr + offset, tfmr);
1853
1854 do {
1855 if (++timeout >= TIMEOUT_LOOPS) {
1856 prerror("CAPP: TB error reset timeout !\n");
1857 return false;
1858 }
1859 /* Read CAPP TFMR */
1860 xscom_read(chip_id, tfmr_addr + offset, &tfmr);
1861 if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
1862 prerror("CAPP: TB error reset: corrupt TFMR!\n");
1863 return false;
1864 }
1865 } while (tfmr & SPR_TFMR_CLEAR_TB_ERRORS);
1866 return true;
1867 }
1868
chiptod_capp_mod_tb(uint32_t chip_id,uint32_t tfmr_addr,uint32_t offset)1869 static bool chiptod_capp_mod_tb(uint32_t chip_id, uint32_t tfmr_addr,
1870 uint32_t offset)
1871 {
1872 uint64_t timeout = 0;
1873 uint64_t tfmr;
1874
1875 /* Switch CAPP timebase to "Not Set" state */
1876 tfmr = base_tfmr | SPR_TFMR_LOAD_TOD_MOD;
1877 xscom_write(chip_id, tfmr_addr + offset, tfmr);
1878 do {
1879 if (++timeout >= (TIMEOUT_LOOPS*2)) {
1880 prerror("CAPP: TB \"Not Set\" timeout\n");
1881 return false;
1882 }
1883 xscom_read(chip_id, tfmr_addr + offset, &tfmr);
1884 if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
1885 prerror("CAPP: TB \"Not Set\" TFMR corrupt\n");
1886 return false;
1887 }
1888 if (GETFIELD(SPR_TFMR_TBST_ENCODED, tfmr) == 9) {
1889 prerror("CAPP: TB \"Not Set\" TOD in error state\n");
1890 return false;
1891 }
1892 } while (tfmr & SPR_TFMR_LOAD_TOD_MOD);
1893
1894 return true;
1895 }
1896
chiptod_wait_for_chip_sync(void)1897 static bool chiptod_wait_for_chip_sync(void)
1898 {
1899 uint64_t tfmr;
1900 uint64_t timeout = 0;
1901
1902 /* Read core TFMR, mask bit 42, write core TFMR back */
1903 tfmr = mfspr(SPR_TFMR);
1904 tfmr &= ~SPR_TFMR_TB_SYNC_OCCURED;
1905 mtspr(SPR_TFMR, tfmr);
1906
1907 /* Read core TFMR until the TB sync occurred */
1908 do {
1909 if (++timeout >= TIMEOUT_LOOPS) {
1910 prerror("No sync pulses\n");
1911 return false;
1912 }
1913 tfmr = mfspr(SPR_TFMR);
1914 } while (!(tfmr & SPR_TFMR_TB_SYNC_OCCURED));
1915 return true;
1916 }
1917
chiptod_capp_check_tb_running(uint32_t chip_id,uint32_t tfmr_addr,uint32_t offset)1918 static bool chiptod_capp_check_tb_running(uint32_t chip_id,
1919 uint32_t tfmr_addr,
1920 uint32_t offset)
1921 {
1922 uint64_t tfmr;
1923 uint64_t timeout = 0;
1924
1925 /* Read CAPP TFMR until TB becomes valid */
1926 do {
1927 if (++timeout >= (TIMEOUT_LOOPS*2)) {
1928 prerror("CAPP: TB Invalid!\n");
1929 return false;
1930 }
1931 xscom_read(chip_id, tfmr_addr + offset, &tfmr);
1932 if (tfmr & SPR_TFMR_TFMR_CORRUPT) {
1933 prerror("CAPP: TFMR corrupt!\n");
1934 return false;
1935 }
1936 } while (!(tfmr & SPR_TFMR_TB_VALID));
1937 return true;
1938 }
1939
chiptod_capp_timebase_sync(unsigned int chip_id,uint32_t tfmr_addr,uint32_t tb_addr,uint32_t offset)1940 bool chiptod_capp_timebase_sync(unsigned int chip_id, uint32_t tfmr_addr,
1941 uint32_t tb_addr, uint32_t offset)
1942 {
1943 uint64_t tfmr;
1944 uint64_t capp_tb;
1945 int64_t delta;
1946 unsigned int retry = 0;
1947
1948 /* Set CAPP TFMR to base tfmr value */
1949 xscom_write(chip_id, tfmr_addr + offset, base_tfmr);
1950
1951 /* Reset CAPP TB errors before attempting the sync */
1952 if (!chiptod_capp_reset_tb_errors(chip_id, tfmr_addr, offset))
1953 return false;
1954
1955 /* Switch CAPP TB to "Not Set" state */
1956 if (!chiptod_capp_mod_tb(chip_id, tfmr_addr, offset))
1957 return false;
1958
1959 /* Sync CAPP TB with core TB, retry while difference > 16usecs */
1960 do {
1961 if (retry++ > 5) {
1962 prerror("CAPP: TB sync: giving up!\n");
1963 return false;
1964 }
1965
1966 /* Make CAPP ready to get the TB, wait for chip sync */
1967 tfmr = base_tfmr | SPR_TFMR_MOVE_CHIP_TOD_TO_TB;
1968 xscom_write(chip_id, tfmr_addr + offset, tfmr);
1969 if (!chiptod_wait_for_chip_sync())
1970 return false;
1971
1972 /* Set CAPP TB from core TB */
1973 xscom_write(chip_id, tb_addr + offset, mftb());
1974
1975 /* Wait for CAPP TFMR tb_valid bit */
1976 if (!chiptod_capp_check_tb_running(chip_id, tfmr_addr, offset))
1977 return false;
1978
1979 /* Read CAPP TB, read core TB, compare */
1980 xscom_read(chip_id, tb_addr + offset, &capp_tb);
1981 delta = mftb() - capp_tb;
1982 if (delta < 0)
1983 delta = -delta;
1984 } while (tb_to_usecs(delta) > 16);
1985
1986 return true;
1987 }
1988