1 /* Copyright 2013-2014 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17
18 /*
19 * IBM System P FSP (Flexible Service Processor)
20 */
21 #ifndef __FSP_H
22 #define __FSP_H
23
24 #include <skiboot.h>
25 #include <psi.h>
26
27 /* Current max number of FSPs
28 * one primary and one secondary is all we support
29 */
30 #define FSP_MAX 2
31
32 /* Command protocol.
33 *
34 * Commands have a byte class and a byte subcommand. With the exception
35 * of some HMC related commands (class 0xe0) which we don't support,
36 * only one outstanding command is allowed for a given class.
37 *
38 * Note: 0xCE and 0xCF fall into the same class, ie, only one of them can
39 * be outstanding.
40 *
41 * A command is outstanding until it has been acknowledged. This doesn't
42 * imply a response, the response can come later.
43 */
44
45 /* Protocol status error codes used by the protocol */
46 #define FSP_STATUS_SUCCESS 0x00 /* Command successful */
47 #define FSP_STATUS_MORE_DATA 0x02 /* Success, EOF not reached */
48 #define FSP_STATUS_DATA_INLINE 0x11 /* Data inline in mbox */
49 #define FSP_STATUS_INVALID_SUBCMD 0x20
50 #define FSP_STATUS_INVALID_MOD 0x21
51 #define FSP_STATUS_INVALID_DATA 0x22
52 #define FSP_STATUS_INVALID_DPOSTATE 0x23
53 #define FSP_STATUS_DMA_ERROR 0x24
54 #define FSP_STATUS_INVALID_CMD 0x2c
55 #define FSP_STATUS_SEQ_ERROR 0x2d
56 #define FSP_STATUS_BAD_STATE 0x2e
57 #define FSP_STATUS_NOT_SUPPORTED 0x2f
58 #define FSP_STATUS_FILE_TOO_LARGE 0x43
59 #define FSP_STATUS_FLASH_INPROGRESS 0x61
60 #define FSP_STATUS_FLASH_NOPROGRESS 0x62
61 #define FSP_STATUS_FLASH_INVALID_SIDE 0x63
62 #define FSP_STATUS_GENERIC_ERROR 0xfe
63 #define FSP_STATUS_EOF_ERROR 0x02
64 #define FSP_STATUS_DMA_ERROR 0x24
65 #define FSP_STATUS_BUSY 0x3e
66 #define FSP_STATUS_FLASH_BUSY 0x3f
67 #define FSP_STATUS_INVALID_SUBID 0x41
68 #define FSP_STATUS_LENGTH_ERROR 0x42
69 #define FSP_STAUS_INVALID_HMC_ID 0x51
70 #define FSP_STATUS_SPCN_ERROR 0xA8 /* SPCN error */
71 #define FSP_STATUS_INVALID_LC 0xC0 /* Invalid location code */
72 #define FSP_STATUS_ENCL_IND_RESET 0xC2 /* Enclosure Indicator cannot be reset */
73 #define FSP_STATUS_TOD_RESET 0xA9 /* TOD reset due to invalid state at POR */
74 #define FSP_STATUS_TOD_PERMANENT_ERROR 0xAF /* Permanent error in TOD */
75 #define FSP_STATUS_I2C_TRANS_ERROR 0xE4 /* I2C device / transmission error */
76 #define FSP_STATUS_IND_PARTIAL_SUCCESS 0xE5 /* Indicator partial success */
77 #define FSP_STATUS_GENERIC_FAILURE 0xEF /* Generic Failure in execution */
78
79 /*
80 * FSP registers
81 *
82 * All of the below register definitions come from the FSP0 "Black Widow" spec
83 * They are the same for FSP1 except they are presented big-endian vs
84 * little-endian for FSP0 -- which used PCI
85 * all regs are 4 bytes wide, and we read the larger data areas in 4 byte
86 * granularity as well
87 *
88 * there are actually two defined sets of MBX registers
89 * MBX2 can't generate interrupts to the host and only MBX1 is currently
90 * used by firmware running on the FSP, so we're mostly ignoring MBX2
91 */
92
93 /* Device Reset Control Register */
94 #define FSP_DRCR_REG 0x00
95 #define FSP_DRCR_CLR_REG 0x04
96
97 /* Bit masks for DRCR */
98 #define FSP_DRCR_CMD_VALID PPC_BIT32(16)
99 #define FSP_DRCR_TERMINATE PPC_BIT32(17)
100 #define FSP_DRCR_PREP_FOR_RESET PPC_BIT32(23)
101 #define FSP_DRCR_CLEAR_DISR PPC_BIT32(30)
102
103 /* DRCR commands need the CMD_VALID bit set */
104 #define FSP_PREP_FOR_RESET_CMD (FSP_DRCR_CMD_VALID | \
105 FSP_DRCR_PREP_FOR_RESET)
106 #define FSP_DRCR_ACK_MASK (0xff << 8)
107
108 /* Device Immediate Status Register */
109 #define FSP_DISR_REG 0x08
110 #define FSP_DISR_CLR_REG 0x0C
111
112 /* Bit masks for DISR */
113 #define FSP_DISR_FSP_UNIT_CHECK PPC_BIT32(16)
114 #define FSP_DISR_FSP_RUNTIME_TERM PPC_BIT32(21)
115 #define FSP_DISR_FSP_RR_COMPLETE PPC_BIT32(22)
116 #define FSP_DISR_FSP_FLASH_TERM PPC_BIT32(23)
117 #define FSP_DISR_RUNTIME_STATE_SYNCD PPC_BIT32(24)
118 #define FSP_DISR_DBG_IN_PROGRESS PPC_BIT32(25)
119 #define FSP_DISR_FSP_IN_RR PPC_BIT32(26)
120 #define FSP_DISR_FSP_REBOOT_IN_PROGRESS PPC_BIT32(27)
121 #define FSP_DISR_CRIT_OP_IN_PROGRESS PPC_BIT32(28)
122 #define FSP_DISR_STATUS_ACK_RXD PPC_BIT32(31)
123
124 #define FSP_DISR_HIR_TRIGGER_MASK (FSP_DISR_FSP_UNIT_CHECK | \
125 FSP_DISR_FSP_RUNTIME_TERM | \
126 FSP_DISR_FSP_FLASH_TERM)
127
128 /* The host version of the control register shares bits with the FSP's
129 * control reg. Those bits are defined such that one side can set
130 * a bit and the other side can clear it
131 */
132 #define FSP_MBX1_HCTL_REG 0x080 /* AKA DSCR1 */
133 #define FSP_MBX1_FCTL_REG 0x090
134 #define FSP_MBX2_HCTL_REG 0x0a0 /* AKA DSCR2 */
135 #define FSP_MBX2_FCTL_REG 0x0b0
136
137 /* Bits in the control reg */
138 #define FSP_MBX_CTL_PTS (1 << 31)
139 #define FSP_MBX_CTL_ABORT (1 << 30)
140 #define FSP_MBX_CTL_SPPEND (1 << 29)
141 #define FSP_MBX_CTL_HPEND (1 << 28)
142 #define FSP_MBX_CTL_XDN (1 << 26)
143 #define FSP_MBX_CTL_XUP (1 << 25)
144 #define FSP_MBX_CTL_HCHOST_MASK (0xf << 20)
145 #define FSP_MBX_CTL_HCHOST_SHIFT 20
146 #define FSP_MBX_CTL_DCHOST_MASK (0xff << 12)
147 #define FSP_MBX_CTL_DCHOST_SHIFT 12
148 #define FSP_MBX_CTL_HCSP_MASK (0xf << 8)
149 #define FSP_MBX_CTL_HCSP_SHIFT 8
150 #define FSP_MBX_CTL_DCSP_MASK (0xff)
151 #define FSP_MBX_CTL_DCSP_SHIFT 0
152
153 /* Three header registers owned by the host */
154 #define FSP_MBX1_HHDR0_REG 0x84
155 #define FSP_MBX1_HHDR1_REG 0x88
156 #define FSP_MBX1_HHDR2_REG 0x8C
157 #define FSP_MBX2_HHDR0_REG 0xa4
158 #define FSP_MBX2_HHDR1_REG 0xa8
159 #define FSP_MBX2_HHDR2_REG 0xaC
160
161 /* SP Doorbell Error Status register */
162 #define FSP_SDES_REG 0xc0
163
164 /* Host Doorbell Error Status register */
165 #define FSP_HDES_REG 0xc4
166
167 /* Bit definitions for both SDES and HDES
168 *
169 * Notes:
170 *
171 * - CLR: is written to clear the status and always reads
172 * as 0. It can be used to detect an error state (a HB
173 * freeze will return all 1's)
174 * - ILLEGAL: illegal operation such as host trying to write
175 * to an FSP only register etc...
176 * - WFULL: set if host tried to write to the SP doorbell while
177 * the pending bit is still set
178 * - REMPTY: tried to read while host pending bit not set
179 * - PAR: SP RAM parity error
180 */
181 #define FSP_DBERRSTAT_ILLEGAL1 (1 << 27)
182 #define FSP_DBERRSTAT_WFULL1 (1 << 26)
183 #define FSP_DBERRSTAT_REMPTY1 (1 << 25)
184 #define FSP_DBERRSTAT_PAR1 (1 << 24)
185 #define FSP_DBERRSTAT_CLR1 (1 << 16)
186 #define FSP_DBERRSTAT_ILLEGAL2 (1 << 11)
187 #define FSP_DBERRSTAT_WFULL2 (1 << 10)
188 #define FSP_DBERRSTAT_REMPTY2 (1 << 9)
189 #define FSP_DBERRSTAT_PAR2 (1 << 8)
190 #define FSP_DBERRSTAT_CLR2 (1 << 0)
191
192 /* Host Doorbell Interrupt Register and mask
193 *
194 * Note that while HDIR has bits for MBX2, only
195 * MBX1 can actually generate interrupts. Thus only the
196 * MBX1 bits are implemented in the mask register.
197 */
198 #define FSP_HDIR_REG 0xc8
199 #define FSP_HDIM_SET_REG 0xcc
200 #define FSP_HDIM_CLR_REG 0xd0
201 #define FSP_DBIRQ_ERROR2 (1 << 10)
202 #define FSP_DBIRQ_XUP2 (1 << 9)
203 #define FSP_DBIRQ_HPEND2 (1 << 8)
204 #define FSP_DBIRQ_ERROR1 (1 << 2)
205 #define FSP_DBIRQ_XUP1 (1 << 1)
206 #define FSP_DBIRQ_HPEND1 (1 << 0)
207 #define FSP_DBIRQ_MBOX1 (FSP_DBIRQ_ERROR1 | FSP_DBIRQ_XUP1 | \
208 FSP_DBIRQ_HPEND1)
209 #define FSP_DBIRQ_MBOX2 (FSP_DBIRQ_ERROR2 | FSP_DBIRQ_XUP2 | \
210 FSP_DBIRQ_HPEND2)
211 #define FSP_DBIRQ_ALL (FSP_DBIRQ_MBOX1 | FSP_DBIRQ_MBOX2)
212
213 /* Doorbell Interrupt Register (FSP internal interrupt latch
214 * read-only on host side
215 */
216 #define FSP_PDIR_REG 0xd4
217 /* And associated mask */
218 #define FSP_PDIM_SET_REG 0xd8
219 #define FSP_PDIM_CLR_REG 0xdc
220
221 /* Bits for the above */
222 #define FSP_PDIRQ_ABORT2 (1 << 7)
223 #define FSP_PDIRQ_ABORT1 (1 << 6)
224 #define FSP_PDIRQ_ERROR2 (1 << 5)
225 #define FSP_PDIRQ_ERROR1 (1 << 4)
226 #define FSP_PDIRQ_XDN2 (1 << 3)
227 #define FSP_PDIRQ_XDN1 (1 << 2)
228 #define FSP_PDIRQ_SPPEND2 (1 << 1)
229 #define FSP_PDIRQ_SPPEND1 (1 << 0)
230
231 /* FSP owned headers */
232 #define FSP_MBX1_FHDR0_REG 0x094
233 #define FSP_MBX1_FHDR1_REG 0x098
234 #define FSP_MBX1_FHDR2_REG 0x09C
235 #define FSP_MBX2_FHDR0_REG 0x0b4
236 #define FSP_MBX2_FHDR1_REG 0x0b8
237 #define FSP_MBX2_FHDR2_REG 0x0bC
238
239 /* Data areas, we can only write to host data, and read from FSP data
240 *
241 * Each area is 0x140 bytes long
242 */
243 #define FSP_MBX1_HDATA_AREA 0x100
244 #define FSP_MBX1_FDATA_AREA 0x200
245 #define FSP_MBX2_HDATA_AREA 0x300
246 #define FSP_MBX2_FDATA_AREA 0x400
247
248 /* These are scratch registers */
249 #define FSP_SCRATCH0_REG 0xe0
250 #define FSP_SCRATCH1_REG 0xe4
251 #define FSP_SCRATCH2_REG 0xe8
252 #define FSP_SCRATCH3_REG 0xec
253
254 /* This is what the cmd_sub_mod will have for FSP_MCLASS_RR_EVENT */
255 #define FSP_RESET_START 0x1
256 #define FSP_RELOAD_COMPLETE 0x2
257
258 /*
259 * Message classes
260 */
261
262 /* The FSP_MCLASS_RR_EVENT is a special message class that doesn't
263 * participate in mbox event related activities. Its relevant only
264 * for hypervisor internal use. So, handle it specially for command
265 * class extraction too.
266 */
267 #define FSP_MCLASS_RR_EVENT 0xaa /* see FSP_R/R defines above */
268 #define FSP_MCLASS_FIRST 0xce
269 #define FSP_MCLASS_SERVICE 0xce
270 #define FSP_MCLASS_IPL 0xcf
271 #define FSP_MCLASS_PCTRL_MSG 0xd0
272 #define FSP_MCLASS_PCTRL_ABORTS 0xd1
273 #define FSP_MCLASS_ERR_LOG 0xd2
274 #define FSP_MCLASS_CODE_UPDATE 0xd3
275 #define FSP_MCLASS_FETCH_SPDATA 0xd4
276 #define FSP_MCLASS_FETCH_HVDATA 0xd5
277 #define FSP_MCLASS_NVRAM 0xd6
278 #define FSP_MCLASS_MBOX_SURV 0xd7
279 #define FSP_MCLASS_RTC 0xd8
280 #define FSP_MCLASS_SMART_CHIP 0xd9
281 #define FSP_MCLASS_INDICATOR 0xda
282 #define FSP_MCLASS_HMC_INTFMSG 0xe0
283 #define FSP_MCLASS_HMC_VT 0xe1
284 #define FSP_MCLASS_HMC_BUFFERS 0xe2
285 #define FSP_MCLASS_SHARK 0xe3
286 #define FSP_MCLASS_MEMORY_ERR 0xe4
287 #define FSP_MCLASS_CUOD_EVENT 0xe5
288 #define FSP_MCLASS_HW_MAINT 0xe6
289 #define FSP_MCLASS_VIO 0xe7
290 #define FSP_MCLASS_SRC_MSG 0xe8
291 #define FSP_MCLASS_DATA_COPY 0xe9
292 #define FSP_MCLASS_TONE 0xea
293 #define FSP_MCLASS_VIRTUAL_NVRAM 0xeb
294 #define FSP_MCLASS_TORRENT 0xec
295 #define FSP_MCLASS_NODE_PDOWN 0xed
296 #define FSP_MCLASS_DIAG 0xee
297 #define FSP_MCLASS_PCIE_LINK_TOPO 0xef
298 #define FSP_MCLASS_OCC 0xf0
299 #define FSP_MCLASS_TRUSTED_BOOT 0xf1
300 #define FSP_MCLASS_HBRT 0xf2
301 #define FSP_MCLASS_LAST 0xf2
302
303 /*
304 * Commands are provided in rxxyyzz form where:
305 *
306 * - r is 0: no response or 1: response expected
307 * - xx is class
308 * - yy is subcommand
309 * - zz is mod
310 *
311 * WARNING: We only set the r bit for HV->FSP commands
312 * long run, we want to remove use of that bit
313 * and instead have a table of all commands in
314 * the FSP driver indicating which ones take a
315 * response...
316 */
317
318 /*
319 * Class 0xCF
320 */
321 #define FSP_CMD_OPL 0x0cf7100 /* HV->FSP: Operational Load Compl. */
322 #define FSP_CMD_HV_STATE_CHG 0x0cf0200 /* FSP->HV: Request HV state change */
323 #define FSP_RSP_HV_STATE_CHG 0x0cf8200
324 #define FSP_CMD_SP_NEW_ROLE 0x0cf0700 /* FSP->HV: FSP assuming a new role */
325 #define FSP_RSP_SP_NEW_ROLE 0x0cf8700
326 #define FSP_CMD_SP_RELOAD_COMP 0x0cf0102 /* FSP->HV: FSP reload complete */
327
328
329 /*
330 * Class 0xCE
331 */
332 #define FSP_CMD_ACK_DUMP 0x1ce0200 /* HV->FSP: Dump ack */
333 #define FSP_CMD_HV_QUERY_CAPS 0x1ce0400 /* HV->FSP: Query capabilities */
334 #define FSP_RSP_HV_QUERY_CAPS 0x1ce8400
335 #define FSP_CMD_SP_QUERY_CAPS 0x0ce0501 /* FSP->HV */
336 #define FSP_RSP_SP_QUERY_CAPS 0x0ce8500
337 #define FSP_CMD_GET_IPL_SIDE 0x1ce0600 /* HV->FSP: Get IPL side and speed */
338 #define FSP_CMD_SET_IPL_SIDE 0x1ce0780 /* HV->FSP: Set next IPL side */
339 #define FSP_CMD_ERRLOG_PHYP_ACK 0x1ce0800 /* HV->FSP */
340 #define FSP_RSP_ERRLOG_PHYP_ACK 0x0ce8800 /* FSP->HV */
341 #define FSP_CMD_ERRLOG_GET_PLID 0x0ce0900 /* FSP->HV: Get PLID */
342 #define FSP_RSP_ERRLOG_GET_PLID 0x0ce8900 /* HV->FSP */
343 #define FSP_CMD_SA_INDICATOR 0x1ce1000 /* HV->FSP: read/update SAI */
344 #define FSP_RSP_SA_INDICATOR 0x0ce9000 /* FSP->HV */
345 #define FSP_CMD_QUERY_SPARM 0x1ce1200 /* HV->FSP: System parameter query */
346 #define FSP_RSP_QUERY_SPARM 0x0ce9200 /* FSP->HV: System parameter resp */
347 #define FSP_CMD_SET_SPARM_1 0x1ce1301 /* HV->FSP: Set system parameter */
348 #define FSP_CMD_SET_SPARM_2 0x1ce1302 /* HV->FSP: Set system parameter TCE */
349 #define FSP_RSP_SET_SPARM 0x0ce9300 /* FSP->HV: Set system parameter resp */
350 #define FSP_CMD_SP_SPARM_UPD_0 0x0ce1600 /* FSP->HV: Sysparm updated no data */
351 #define FSP_CMD_SP_SPARM_UPD_1 0x0ce1601 /* FSP->HV: Sysparm updated data */
352 #define FSP_CMD_HYP_MDST_TABLE 0x1ce2600 /* HV->FSP: Sapphire MDST table */
353 #define FSP_CMD_TPO_READ 0x1ce4201 /* FSP->HV */
354 #define FSP_CMD_TPO_WRITE 0x1ce4301 /* HV->FSP */
355 #define FSP_CMD_TPO_DISABLE 0x1ce4400 /* HV->FSP */
356 #define FSP_CMD_STATUS_REQ 0x1ce4800 /* HV->FSP: Request normal panel status */
357 #define FSP_CMD_STATUS_EX1_REQ 0x1ce4802 /* HV->FSP: Request extended 1 panel status */
358 #define FSP_CMD_STATUS_EX2_REQ 0x1ce4803 /* HV->FSP: Request extended 2 panel status */
359 #define FSP_CMD_CONTINUE_ACK 0x0ce5700 /* HV->FSP: HV acks CONTINUE IPL */
360 #define FSP_CMD_HV_FUNCTNAL 0x1ce5707 /* HV->FSP: Set HV functional state */
361 #define FSP_CMD_FSP_FUNCTNAL 0x0ce5708 /* FSP->HV: FSP functional state */
362 #define FSP_CMD_CONTINUE_IPL 0x0ce7000 /* FSP->HV: HV has control */
363 #define FSP_RSP_SYS_DUMP_OLD 0x0ce7800 /* FSP->HV: Sys Dump Available */
364 #define FSP_RSP_SYS_DUMP 0x0ce7802 /* FSP->HV: Sys Dump Available */
365 #define FSP_RSP_RES_DUMP 0x0ce7807 /* FSP->HV: Resource Dump Available */
366 #define FSP_CMD_PCI_POWER_CONF 0x1ce1b00 /* HV->FSP: Send PCIe list to FSP */
367 #define FSP_CMD_POWERDOWN_NORM 0x1ce4d00 /* HV->FSP: Normal power down */
368 #define FSP_CMD_POWERDOWN_QUICK 0x1ce4d01 /* HV->FSP: Quick power down */
369 #define FSP_CMD_POWERDOWN_PCIRS 0x1ce4d02 /* HV->FSP: PCI cfg reset power dwn */
370 #define FSP_CMD_REBOOT 0x1ce4e00 /* HV->FSP: Standard IPL */
371 #define FSP_CMD_DEEP_REBOOT 0x1ce4e04 /* HV->FSP: Deep IPL */
372 #define FSP_CMD_INIT_DPO 0x0ce5b00 /* FSP->HV: Initialize Delayed Power Off */
373 #define FSP_RSP_INIT_DPO 0x0cedb00 /* HV->FSP: Response for DPO init command */
374 #define FSP_CMD_GET_HIR_PLID 0x0ce0900 /* FSP->HV: Get Platform Log ID with
375 * reason for Host Initiated Reset.
376 */
377 #define FSP_RSP_GET_HIR_PLID 0x0ce8900 /* HV->FSP: Reply with PLID */
378 #define FSP_CMD_PANELSTATUS 0x0ce5c00 /* FSP->HV */
379 #define FSP_CMD_PANELSTATUS_EX1 0x0ce5c02 /* FSP->HV */
380 #define FSP_CMD_PANELSTATUS_EX2 0x0ce5c03 /* FSP->HV */
381
382 /* SAI read/update sub commands */
383 #define FSP_LED_RESET_REAL_SAI 0x00
384 #define FSP_LED_READ_REAL_SAI 0x02
385 #define FSP_LED_RESET_PARTITION_SAI 0x80
386 #define FSP_LED_SET_PARTITION_SAI 0x81
387 #define FSP_LED_READ_PARTITION_SAI 0x82
388 #define FSP_LED_READ_PLAT_SAI 0x83
389 #define FSP_LED_RESET_PLAT_SAI 0x84
390 #define FSP_LED_SET_PLAT_SAI 0x85
391
392 /*
393 * Class 0xD2
394 */
395 #define FSP_CMD_CREATE_ERRLOG 0x1d21000 /* HV->FSP */
396 #define FSP_RSP_CREATE_ERRLOG 0x0d29000 /* FSP->HV */
397 #define FSP_CMD_ERRLOG_NOTIFICATION 0x0d25a00 /* FSP->HV */
398 #define FSP_RSP_ERRLOG_NOTIFICATION 0x0d2da00 /* HV->FSP */
399 #define FSP_RSP_ELOG_NOTIFICATION_ERROR 0x1d2dafe /* HV->FSP */
400 #define FSP_CMD_FSP_DUMP_INIT 0x1d21200 /* HV->FSP: FSP dump init */
401
402 /*
403 * Class 0xD0
404 */
405 #define FSP_CMD_SPCN_PASSTHRU 0x1d05400 /* HV->FSP */
406 #define FSP_RSP_SPCN_PASSTHRU 0x0d0d400 /* FSP->HV */
407
408 /*
409 * Class 0xD3
410 */
411 #define FSP_CMD_FLASH_START 0x01d30101 /* HV->FSP: Code update start */
412 #define FSP_CMD_FLASH_COMPLETE 0x01d30201 /* HV->FSP: Code update complete */
413 #define FSP_CMD_FLASH_ABORT 0x01d302ff /* HV->FSP: Code update complete */
414 #define FSP_CMD_FLASH_WRITE 0x01d30300 /* HV->FSP: Write LID */
415 #define FSP_CMD_FLASH_DEL 0x01d30500 /* HV->FSP: Delete LID */
416 #define FSP_CMD_FLASH_NORMAL 0x01d30401 /* HV->FSP: Commit (T -> P) */
417 #define FSP_CMD_FLASH_REMOVE 0x01d30402 /* HV->FSP: Reject (P -> T) */
418 #define FSP_CMD_FLASH_SWAP 0x01d30403 /* HV->FSP: Swap */
419 #define FSP_CMD_FLASH_OUTC 0x00d30601 /* FSP->HV: Out of band commit */
420 #define FSP_CMD_FLASH_OUTR 0x00d30602 /* FSP->HV: Out of band reject */
421 #define FSP_CMD_FLASH_OUTS 0x00d30603 /* FSP->HV: Out of band swap */
422 #define FSP_CMD_FLASH_OUT_RSP 0x00d38600 /* HV->FSP: Out of band Resp */
423 #define FSP_CMD_FLASH_CACHE 0x00d30700 /* FSP->HV: Update LID cache */
424 #define FSP_CMD_FLASH_CACHE_RSP 0x00d38700 /* HV->FSP: Update LID cache Resp */
425
426 /*
427 * Class 0xD4
428 */
429 #define FSP_CMD_FETCH_SP_DATA 0x1d40101 /* HV->FSP: Fetch & DMA data */
430 #define FSP_CMD_WRITE_SP_DATA 0x1d40201 /* HV->FSP: Fetch & DMA data */
431 #define FSP_CMD_FETCH_PLAT_DATA 0x1d40500 /* HV->FSP: Platform function data */
432 #define FSP_CMD_SEND_PLAT_DATA 0x0d40501 /* FSP->HV */
433 #define FSP_RSP_PLAT_DATA 0x0d48500 /* HV->FSP */
434
435 /* Data set IDs for SP data commands */
436 #define FSP_DATASET_SP_DUMP 0x01
437 #define FSP_DATASET_HW_DUMP 0x02
438 #define FSP_DATASET_ERRLOG 0x03 /* error log entry */
439 #define FSP_DATASET_MASTER_LID 0x04
440 #define FSP_DATASET_NONSP_LID 0x05
441 #define FSP_DATASET_ELID_RDATA 0x06
442 #define FSP_DATASET_BLADE_PARM 0x07
443 #define FSP_DATASET_LOC_PORTMAP 0x08
444 #define FSP_DATASET_SYSIND_CAP 0x09
445 #define FSP_DATASET_FSP_RSRCDMP 0x0a
446 #define FSP_DATASET_HBRT_BLOB 0x0b
447
448 /* Adjustment to get T side LIDs */
449 #define ADJUST_T_SIDE_LID_NO 0x8000
450
451 /*
452 * Class 0xD5
453 */
454 #define FSP_CMD_ALLOC_INBOUND 0x0d50400 /* FSP->HV: Allocate inbound buf. */
455 #define FSP_RSP_ALLOC_INBOUND 0x0d58400
456
457 /*
458 * Class 0xD7
459 */
460 #define FSP_CMD_SURV_HBEAT 0x1d70000 /* ? */
461 #define FSP_CMD_SURV_ACK 0x0d78000 /* ? */
462
463 /*
464 * Class 0xD8
465 */
466 #define FSP_CMD_READ_TOD 0x1d82000 /* HV->FSP */
467 #define FSP_CMD_READ_TOD_EXT 0x1d82001 /* HV->FSP */
468 #define FSP_CMD_WRITE_TOD 0x1d82100 /* HV->FSP */
469 #define FSP_CMD_WRITE_TOD_EXT 0x1d82101 /* HV->FSP */
470
471 /*
472 * Class 0xDA
473 */
474 #define FSP_CMD_GET_LED_LIST 0x00da1101 /* Location code information structure */
475 #define FSP_RSP_GET_LED_LIST 0x00da9100
476 #define FSP_CMD_RET_LED_BUFFER 0x00da1102 /* Location code buffer information */
477 #define FSP_RSP_RET_LED_BUFFER 0x00da9100
478 #define FSP_CMD_GET_LED_STATE 0x00da1103 /* Retrieve Indicator State */
479 #define FSP_RSP_GET_LED_STATE 0x00da9100
480 #define FSP_CMD_SET_LED_STATE 0x00da1104 /* Set Service Indicator State */
481 #define FSP_RSP_SET_LED_STATE 0x00da9100
482 #define FSP_CMD_GET_MTMS_LIST 0x00da1105 /* Get MTMS and config ID list */
483 #define FSP_RSP_GET_MTMS_LIST 0x00da9100
484 #define FSP_CMD_SET_ENCL_MTMS 0x00da1106 /* Set MTMS */
485 #define FSP_RSP_SET_ENCL_MTMS 0x00da9100
486 #define FSP_CMD_SET_ENCL_CNFG 0x00da1107 /* Set config ID */
487 #define FSP_RSP_SET_ENCL_CNFG 0x00da9100
488 #define FSP_CMD_CLR_INCT_ENCL 0x00da1108 /* Clear inactive address */
489 #define FSP_RSP_CLR_INCT_ENCL 0x00da9100
490 #define FSP_CMD_RET_MTMS_BUFFER 0x00da1109 /* Return MTMS buffer */
491 #define FSP_RSP_RET_MTMS_BUFFER 0x00da9100
492 #define FSP_CMD_ENCL_MCODE_INIT 0x00da110A /* Mcode update (Initiate download) */
493 #define FSP_RSP_ENCL_MCODE_INIT 0x00da9100
494 #define FSP_CMD_ENCL_MCODE_INTR 0x00da110B /* Mcode update (Interrupt download) */
495 #define FSP_RSP_ENCL_MCODE_INTR 0x00da9100
496 #define FSP_CMD_ENCL_POWR_TRACE 0x00da110D /* Enclosure power network trace */
497 #define FSP_RSP_ENCL_POWR_TRACE 0x00da9100
498 #define FSP_CMD_RET_ENCL_TRACE_BUFFER 0x00da110E /* Return power trace buffer */
499 #define FSP_RSP_RET_ENCL_TRACE_BUFFER 0x00da9100
500 #define FSP_CMD_GET_SPCN_LOOP_STATUS 0x00da110F /* Get SPCN loop status */
501 #define FSP_RSP_GET_SPCN_LOOP_STATUS 0x00da9100
502 #define FSP_CMD_INITIATE_LAMP_TEST 0x00da1300 /* Initiate LAMP test */
503
504 /*
505 * Class 0xE0
506 *
507 * HACK ALERT: We mark E00A01 (associate serial port) as not needing
508 * a response. We need to do that because the FSP will send as a result
509 * an Open Virtual Serial of the same class *and* expect a reply before
510 * it will respond to associate serial port. That breaks our logic of
511 * supporting only one cmd/resp outstanding per class.
512 */
513 #define FSP_CMD_HMC_INTF_QUERY 0x0e00100 /* FSP->HV */
514 #define FSP_RSP_HMC_INTF_QUERY 0x0e08100 /* HV->FSP */
515 #define FSP_CMD_ASSOC_SERIAL 0x0e00a01 /* HV->FSP: Associate with a port */
516 #define FSP_RSP_ASSOC_SERIAL 0x0e08a00 /* FSP->HV */
517 #define FSP_CMD_UNASSOC_SERIAL 0x0e00b01 /* HV->FSP: Deassociate */
518 #define FSP_RSP_UNASSOC_SERIAL 0x0e08b00 /* FSP->HV */
519 #define FSP_CMD_OPEN_VSERIAL 0x0e00601 /* FSP->HV: Open serial session */
520 #define FSP_RSP_OPEN_VSERIAL 0x0e08600 /* HV->FSP */
521 #define FSP_CMD_CLOSE_VSERIAL 0x0e00701 /* FSP->HV: Close serial session */
522 #define FSP_RSP_CLOSE_VSERIAL 0x0e08700 /* HV->FSP */
523 #define FSP_CMD_CLOSE_HMC_INTF 0x0e00300 /* FSP->HV: Close HMC interface */
524 #define FSP_RSP_CLOSE_HMC_INTF 0x0e08300 /* HV->FSP */
525
526 /*
527 * Class E1
528 */
529 #define FSP_CMD_VSERIAL_IN 0x0e10100 /* FSP->HV */
530 #define FSP_CMD_VSERIAL_OUT 0x0e10200 /* HV->FSP */
531
532 /*
533 * Class E6
534 */
535 #define FSP_CMD_TOPO_ENABLE_DISABLE 0x0e60600 /* FSP->HV */
536 #define FSP_RSP_TOPO_ENABLE_DISABLE 0x0e68600 /* HV->FSP */
537
538 /*
539 * Class E8
540 */
541 #define FSP_CMD_READ_SRC 0x1e84a40 /* HV->FSP */
542 #define FSP_CMD_DISP_SRC_INDIR 0x1e84a41 /* HV->FSP */
543 #define FSP_CMD_DISP_SRC_DIRECT 0x1e84a42 /* HV->FSP */
544 #define FSP_CMD_CLEAR_SRC 0x1e84b00 /* HV->FSP */
545 #define FSP_CMD_DIS_SRC_ECHO 0x1e87600 /* HV->FSP */
546
547 /*
548 * Class EB
549 */
550 #define FSP_CMD_GET_VNVRAM_SIZE 0x01eb0100 /* HV->FSP */
551 #define FSP_CMD_OPEN_VNVRAM 0x01eb0200 /* HV->FSP */
552 #define FSP_CMD_READ_VNVRAM 0x01eb0300 /* HV->FSP */
553 #define FSP_CMD_WRITE_VNVRAM 0x01eb0400 /* HV->FSP */
554 #define FSP_CMD_GET_VNV_STATS 0x00eb0500 /* FSP->HV */
555 #define FSP_RSP_GET_VNV_STATS 0x00eb8500
556 #define FSP_CMD_FREE_VNV_STATS 0x00eb0600 /* FSP->HV */
557 #define FSP_RSP_FREE_VNV_STATS 0x00eb8600
558
559 /*
560 * Class 0xEE
561 */
562 #define FSP_RSP_DIAG_LINK_ERROR 0x00ee1100 /* FSP->HV */
563 #define FSP_RSP_DIAG_ACK_TIMEOUT 0x00ee0000 /* FSP->HV */
564
565 /*
566 * Class F0
567 */
568 #define FSP_CMD_LOAD_OCC 0x00f00100 /* FSP->HV */
569 #define FSP_RSP_LOAD_OCC 0x00f08100 /* HV->FSP */
570 #define FSP_CMD_LOAD_OCC_STAT 0x01f00300 /* HV->FSP */
571 #define FSP_CMD_RESET_OCC 0x00f00200 /* FSP->HV */
572 #define FSP_RSP_RESET_OCC 0x00f08200 /* HV->FSP */
573 #define FSP_CMD_RESET_OCC_STAT 0x01f00400 /* HV->FSP */
574
575 /*
576 * Class E4
577 */
578 #define FSP_CMD_MEM_RES_CE 0x00e40300 /* FSP->HV: Memory resilience CE */
579 #define FSP_CMD_MEM_RES_UE 0x00e40301 /* FSP->HV: Memory resilience UE */
580 #define FSP_CMD_MEM_RES_UE_SCRB 0x00e40302 /* FSP->HV: UE detected by scrub */
581 #define FSP_RSP_MEM_RES 0x00e48300 /* HV->FSP */
582 #define FSP_CMD_MEM_DYN_DEALLOC 0x00e40500 /* FSP->HV: Dynamic mem dealloc */
583 #define FSP_RSP_MEM_DYN_DEALLOC 0x00e48500 /* HV->FSP */
584
585 /*
586 * Class F2
587 */
588 #define FSP_CMD_HBRT_TO_FSP 0x1f20100 /* HV->FSP: HBRT message */
589 #define FSP_CMD_FSP_TO_HBRT 0x0f20200 /* FSP->HV: HBRT message */
590 #define FSP_RSP_FSP_TO_HBRT 0x0f28200 /* HV->FSP: HBRT message */
591
592
593 /*
594 * Functions exposed to the rest of skiboot
595 */
596
597 /* An FSP message */
598
599 enum fsp_msg_state {
600 fsp_msg_unused = 0,
601 fsp_msg_queued,
602 fsp_msg_sent,
603 fsp_msg_wresp,
604 fsp_msg_done,
605 fsp_msg_timeout,
606 fsp_msg_incoming,
607 fsp_msg_response,
608 fsp_msg_cancelled,
609 };
610
611 struct fsp_msg {
612 /*
613 * User fields. Don't populate word0.seq (upper 16 bits), this
614 * will be done by fsp_queue_msg()
615 */
616 u8 dlen; /* not including word0/word1 */
617 u32 word0; /* seq << 16 | cmd */
618 u32 word1; /* mod << 8 | sub */
619 union {
620 u32 words[14];
621 u8 bytes[56];
622 } data;
623
624 /* Completion function. Called with no lock held */
625 void (*complete)(struct fsp_msg *msg);
626 void *user_data;
627
628 /*
629 * Driver updated fields
630 */
631
632 /* Current msg state */
633 enum fsp_msg_state state;
634
635 /* Set if the message expects a response */
636 bool response;
637
638 /* Response will be filed by driver when response received */
639 struct fsp_msg *resp;
640
641 /* Internal queuing */
642 struct list_node link;
643 };
644
645 /* This checks if a message is still "in progress" in the FSP driver */
fsp_msg_busy(struct fsp_msg * msg)646 static inline bool fsp_msg_busy(struct fsp_msg *msg)
647 {
648 switch(msg->state) {
649 case fsp_msg_unused:
650 case fsp_msg_done:
651 case fsp_msg_timeout:
652 case fsp_msg_response: /* A response is considered a completed msg */
653 return false;
654 default:
655 break;
656 }
657 return true;
658 }
659
fsp_msg_cmd(const struct fsp_msg * msg)660 static inline u32 fsp_msg_cmd(const struct fsp_msg *msg)
661 {
662 u32 cmd_sub_mod;
663 cmd_sub_mod = (msg->word0 & 0xff) << 16;
664 cmd_sub_mod |= (msg->word1 & 0xff) << 8;
665 cmd_sub_mod |= (msg->word1 & 0xff00) >> 8;
666 return cmd_sub_mod;
667 }
668
669 /* Initialize the FSP mailbox driver */
670 extern void fsp_init(void);
671
672 /* Perform the OPL sequence */
673 extern void fsp_opl(void);
674
675 /* Check if system has an FSP */
676 extern bool fsp_present(void);
677
678 /* Allocate and populate an fsp_msg structure
679 *
680 * WARNING: Do _NOT_ use free() on an fsp_msg, use fsp_freemsg()
681 * instead as we will eventually use pre-allocated message pools
682 */
683 extern struct fsp_msg *fsp_allocmsg(bool alloc_response) __warn_unused_result;
684 extern struct fsp_msg *fsp_mkmsg(u32 cmd_sub_mod, u32 add_words, ...) __warn_unused_result;
685
686 /* Populate a pre-allocated msg */
687 extern void fsp_fillmsg(struct fsp_msg *msg, u32 cmd_sub_mod, u32 add_words, ...);
688
689 /* Free a message
690 *
691 * WARNING: This will also free an attached response if any
692 */
693 extern void fsp_freemsg(struct fsp_msg *msg);
694
695 /* Free a message and not the attached reply */
696 extern void __fsp_freemsg(struct fsp_msg *msg);
697
698 /* Cancel a message from the msg queue
699 *
700 * WARNING: * This is intended for use only in the FSP r/r scenario.
701 * * This will also free an attached response if any
702 */
703 extern void fsp_cancelmsg(struct fsp_msg *msg);
704
705 /* Enqueue it in the appropriate FSP queue
706 *
707 * NOTE: This supports being called with the FSP lock already
708 * held. This is the only function in this module that does so
709 * and is meant to be used that way for sending serial "poke"
710 * commands to the FSP.
711 */
712 extern int fsp_queue_msg(struct fsp_msg *msg,
713 void (*comp)(struct fsp_msg *msg)) __warn_unused_result;
714
715 /* Send a fatal message to FSP
716 *
717 * This will *not* run pollers.
718 * Use only when attempting to get the word out about how we died.
719 */
720 extern int fsp_fatal_msg(struct fsp_msg *msg);
721
722 /* Synchronously send a command. If there's a response, the status is
723 * returned as a positive number. A negative result means an error
724 * sending the message.
725 *
726 * If autofree is set, the message and the reply (if any) are freed
727 * after extracting the status. If not set, you are responsible for
728 * freeing both the message and an eventual response
729 *
730 * NOTE: This will call fsp_queue_msg(msg, NULL), hence clearing the
731 * completion field of the message. No synchronous message is expected
732 * to utilize asynchronous completions.
733 */
734 extern int fsp_sync_msg(struct fsp_msg *msg, bool autofree);
735
736 /* Handle FSP interrupts */
737 extern void fsp_interrupt(void);
738
739 /* An FSP client is interested in messages for a given class */
740 struct fsp_client {
741 /* Return true to "own" the message (you can free it) */
742 bool (*message)(u32 cmd_sub_mod, struct fsp_msg *msg);
743 struct list_node link;
744 };
745
746 /* WARNING: Command class FSP_MCLASS_IPL is aliased to FSP_MCLASS_SERVICE,
747 * thus a client of one will get both types of messages.
748 *
749 * WARNING: Client register/unregister takes *NO* lock. These are expected
750 * to be called early at boot before CPUs are brought up and before
751 * fsp_poll() can race. The client callback is called with no lock held.
752 */
753 extern void fsp_register_client(struct fsp_client *client, u8 msgclass);
754 extern void fsp_unregister_client(struct fsp_client *client, u8 msgclass);
755
756 /* FSP TCE map/unmap functions */
757 extern void fsp_tce_map(u32 offset, void *addr, u32 size);
758 extern void fsp_tce_unmap(u32 offset, u32 size);
759 extern void *fsp_inbound_buf_from_tce(u32 tce_token);
760
761 /* Data fetch helper */
762 extern uint32_t fsp_adjust_lid_side(uint32_t lid_no);
763 extern int fsp_fetch_data(uint8_t flags, uint16_t id, uint32_t sub_id,
764 uint32_t offset, void *buffer, size_t *length);
765 extern int fsp_fetch_data_queue(uint8_t flags, uint16_t id, uint32_t sub_id,
766 uint32_t offset, void *buffer, size_t *length,
767 void (*comp)(struct fsp_msg *msg)) __warn_unused_result;
768 extern int fsp_start_preload_resource(enum resource_id id, uint32_t idx,
769 void *buf, size_t *size);
770 extern int fsp_resource_loaded(enum resource_id id, uint32_t idx);
771 extern int fsp_preload_lid(uint32_t lid_no, char *buf, size_t *size);
772 extern int fsp_wait_lid_loaded(uint32_t lid_no);
773
774 /* FSP console stuff */
775 extern void fsp_console_preinit(void);
776 extern void fsp_console_init(void);
777 extern void fsp_console_add_nodes(void);
778 extern void fsp_console_select_stdout(void);
779 extern void fsp_console_reset(void);
780 extern void fsp_console_poll(void *);
781
782 /* Mark FSP lock */
783 extern void fsp_used_by_console(void);
784
785 /* NVRAM */
786 extern int fsp_nvram_info(uint32_t *total_size);
787 extern int fsp_nvram_start_read(void *dst, uint32_t src, uint32_t len);
788 extern int fsp_nvram_write(uint32_t offset, void *src, uint32_t size);
789
790 /* RTC */
791 extern void fsp_rtc_init(void);
792
793 /* ELOG */
794 extern void fsp_elog_read_init(void);
795 extern void fsp_elog_write_init(void);
796
797 /* Code update */
798 extern void fsp_code_update_init(void);
799 extern void fsp_code_update_wait_vpd(bool is_boot);
800
801 /* Dump */
802 extern void fsp_dump_init(void);
803 extern void fsp_fips_dump_notify(uint32_t dump_id, uint32_t dump_len);
804
805 /* Attention Handler */
806 extern void fsp_attn_init(void);
807
808 /* MDST table */
809 extern void fsp_mdst_table_init(void);
810
811 /* This can be set by the fsp_opal_update_flash so that it can
812 * get called just reboot we reboot shutdown the machine.
813 */
814 extern int (*fsp_flash_term_hook)(void);
815
816 /* Surveillance */
817 extern void fsp_init_surveillance(void);
818 extern void fsp_surv_query(void);
819
820 /* IPMI */
821 extern void fsp_ipmi_init(void);
822
823 /* Reset/Reload */
824 extern void fsp_reinit_fsp(void);
825 extern void fsp_trigger_reset(uint32_t plid);
826 extern void fsp_reset_links(void);
827 extern bool fsp_in_rr(void);
828
829 /* FSP memory errors */
830 extern void fsp_memory_err_init(void);
831
832 /* Sensor */
833 extern void fsp_init_sensor(void);
834 extern int64_t fsp_opal_read_sensor(uint32_t sensor_hndl, int token,
835 uint64_t *sensor_data);
836
837 /* Diagnostic */
838 extern void fsp_init_diag(void);
839
840 /* LED */
841 extern void fsp_led_init(void);
842 extern void create_led_device_nodes(void);
843
844 /* EPOW */
845 extern void fsp_epow_init(void);
846
847 /* DPO */
848 extern void fsp_dpo_init(void);
849
850 /* Chiptod */
851 extern void fsp_chiptod_init(void);
852
853 /* Terminate immediate */
854 extern void __attribute__((noreturn)) ibm_fsp_terminate(const char *msg);
855
856 void fsp_op_display(enum op_severity sev, enum op_module mod, uint16_t code);
857
858 #endif /* __FSP_H */
859