1 /* DO NOT EDIT THIS FILE 2 * Automatically generated by generate-cdef-headers.xsl 3 * DO NOT EDIT THIS FILE 4 */ 5 6 #ifndef __BFIN_CDEF_ADSP_BF522_proc__ 7 #define __BFIN_CDEF_ADSP_BF522_proc__ 8 9 #include "../mach-common/ADSP-EDN-core_cdef.h" 10 11 #include "ADSP-EDN-BF52x-extended_cdef.h" 12 13 #define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ 14 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 15 #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) 16 #define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ 17 #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 19 #define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ 20 #define bfin_read_VR_CTL() bfin_read16(VR_CTL) 21 #define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) 22 #define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ 23 #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 24 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 25 #define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ 26 #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 27 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) 28 #define pCHIPID ((uint32_t volatile *)CHIPID) 29 #define bfin_read_CHIPID() bfin_read32(CHIPID) 30 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) 31 #define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ 32 #define bfin_read_SWRST() bfin_read16(SWRST) 33 #define bfin_write_SWRST(val) bfin_write16(SWRST, val) 34 #define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ 35 #define bfin_read_SYSCR() bfin_read16(SYSCR) 36 #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) 37 #define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ 38 #define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) 39 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) 40 #define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ 41 #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) 42 #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) 43 #define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ 44 #define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) 45 #define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) 46 #define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ 47 #define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) 48 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) 49 #define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ 50 #define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) 51 #define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) 52 #define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ 53 #define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) 54 #define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) 55 #define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ 56 #define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) 57 #define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) 58 #define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ 59 #define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) 60 #define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) 61 #define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ 62 #define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) 63 #define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) 64 #define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ 65 #define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) 66 #define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) 67 #define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ 68 #define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) 69 #define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) 70 #define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ 71 #define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) 72 #define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) 73 #define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ 74 #define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) 75 #define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) 76 #define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ 77 #define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) 78 #define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) 79 #define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ 80 #define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) 81 #define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) 82 #define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ 83 #define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) 84 #define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) 85 #define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ 86 #define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) 87 #define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) 88 #define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ 89 #define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) 90 #define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) 91 #define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ 92 #define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) 93 #define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) 94 #define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ 95 #define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) 96 #define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) 97 #define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ 98 #define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) 99 #define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) 100 #define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ 101 #define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) 102 #define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) 103 #define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ 104 #define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) 105 #define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) 106 #define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ 107 #define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) 108 #define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) 109 #define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ 110 #define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) 111 #define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) 112 #define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ 113 #define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) 114 #define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) 115 #define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ 116 #define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) 117 #define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) 118 #define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ 119 #define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) 120 #define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) 121 #define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ 122 #define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) 123 #define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) 124 #define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ 125 #define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) 126 #define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) 127 #define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ 128 #define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) 129 #define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) 130 #define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ 131 #define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) 132 #define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) 133 #define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ 134 #define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) 135 #define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) 136 #define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ 137 #define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) 138 #define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) 139 #define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ 140 #define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) 141 #define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) 142 #define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ 143 #define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) 144 #define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) 145 #define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ 146 #define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) 147 #define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) 148 #define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ 149 #define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) 150 #define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) 151 #define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ 152 #define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) 153 #define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) 154 #define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ 155 #define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) 156 #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) 157 #define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ 158 #define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) 159 #define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) 160 #define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ 161 #define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) 162 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) 163 #define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ 164 #define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) 165 #define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) 166 #define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ 167 #define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) 168 #define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) 169 #define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ 170 #define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) 171 #define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) 172 #define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ 173 #define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) 174 #define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) 175 #define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ 176 #define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) 177 #define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) 178 #define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ 179 #define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) 180 #define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) 181 #define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ 182 #define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) 183 #define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) 184 #define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ 185 #define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) 186 #define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) 187 #define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ 188 #define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) 189 #define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) 190 #define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ 191 #define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) 192 #define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) 193 #define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ 194 #define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) 195 #define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) 196 #define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ 197 #define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) 198 #define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) 199 #define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ 200 #define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) 201 #define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) 202 #define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ 203 #define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) 204 #define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) 205 #define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ 206 #define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) 207 #define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) 208 #define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ 209 #define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) 210 #define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) 211 #define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ 212 #define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) 213 #define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) 214 #define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ 215 #define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) 216 #define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) 217 #define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ 218 #define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) 219 #define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) 220 #define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ 221 #define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) 222 #define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) 223 #define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ 224 #define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) 225 #define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) 226 #define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ 227 #define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) 228 #define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) 229 #define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ 230 #define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) 231 #define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) 232 #define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ 233 #define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) 234 #define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) 235 #define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ 236 #define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) 237 #define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) 238 #define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ 239 #define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) 240 #define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) 241 #define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ 242 #define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) 243 #define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) 244 #define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ 245 #define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) 246 #define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) 247 #define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ 248 #define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) 249 #define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) 250 #define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ 251 #define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) 252 #define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) 253 #define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ 254 #define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) 255 #define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) 256 #define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ 257 #define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) 258 #define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) 259 #define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ 260 #define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) 261 #define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) 262 #define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ 263 #define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) 264 #define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) 265 #define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ 266 #define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) 267 #define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) 268 #define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ 269 #define bfin_read_EVT0() bfin_readPTR(EVT0) 270 #define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) 271 #define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ 272 #define bfin_read_EVT1() bfin_readPTR(EVT1) 273 #define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) 274 #define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ 275 #define bfin_read_EVT2() bfin_readPTR(EVT2) 276 #define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) 277 #define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ 278 #define bfin_read_EVT3() bfin_readPTR(EVT3) 279 #define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) 280 #define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ 281 #define bfin_read_EVT4() bfin_readPTR(EVT4) 282 #define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) 283 #define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ 284 #define bfin_read_EVT5() bfin_readPTR(EVT5) 285 #define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) 286 #define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ 287 #define bfin_read_EVT6() bfin_readPTR(EVT6) 288 #define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) 289 #define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ 290 #define bfin_read_EVT7() bfin_readPTR(EVT7) 291 #define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) 292 #define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ 293 #define bfin_read_EVT8() bfin_readPTR(EVT8) 294 #define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) 295 #define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ 296 #define bfin_read_EVT9() bfin_readPTR(EVT9) 297 #define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) 298 #define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ 299 #define bfin_read_EVT10() bfin_readPTR(EVT10) 300 #define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) 301 #define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ 302 #define bfin_read_EVT11() bfin_readPTR(EVT11) 303 #define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) 304 #define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ 305 #define bfin_read_EVT12() bfin_readPTR(EVT12) 306 #define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) 307 #define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ 308 #define bfin_read_EVT13() bfin_readPTR(EVT13) 309 #define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) 310 #define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ 311 #define bfin_read_EVT14() bfin_readPTR(EVT14) 312 #define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) 313 #define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ 314 #define bfin_read_EVT15() bfin_readPTR(EVT15) 315 #define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) 316 #define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ 317 #define bfin_read_ILAT() bfin_read32(ILAT) 318 #define bfin_write_ILAT(val) bfin_write32(ILAT, val) 319 #define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ 320 #define bfin_read_IMASK() bfin_read32(IMASK) 321 #define bfin_write_IMASK(val) bfin_write32(IMASK, val) 322 #define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ 323 #define bfin_read_IPEND() bfin_read32(IPEND) 324 #define bfin_write_IPEND(val) bfin_write32(IPEND, val) 325 #define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ 326 #define bfin_read_IPRIO() bfin_read32(IPRIO) 327 #define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) 328 #define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ 329 #define bfin_read_TCNTL() bfin_read32(TCNTL) 330 #define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) 331 #define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ 332 #define bfin_read_TPERIOD() bfin_read32(TPERIOD) 333 #define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) 334 #define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ 335 #define bfin_read_TSCALE() bfin_read32(TSCALE) 336 #define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) 337 #define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ 338 #define bfin_read_TCOUNT() bfin_read32(TCOUNT) 339 #define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) 340 341 #endif /* __BFIN_CDEF_ADSP_BF522_proc__ */ 342