1 /* 2 * (C) Copyright 2005 3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * board/config.h - configuration options, board specific 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36 #define CONFIG_405GP 1 /* This is a PPC405 CPU */ 37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */ 38 39 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ 40 41 #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ 42 43 #define CONFIG_BAUDRATE 9600 44 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 45 46 #undef CONFIG_BOOTARGS 47 #undef CONFIG_BOOTCOMMAND 48 49 #define CONFIG_PREBOOT /* enable preboot variable */ 50 51 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 52 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 53 54 #define CONFIG_MII 1 /* MII PHY management */ 55 #define CONFIG_PHY_ADDR 0 /* PHY address */ 56 57 /* 58 * BOOTP options 59 */ 60 #define CONFIG_BOOTP_BOOTFILESIZE 61 #define CONFIG_BOOTP_BOOTPATH 62 #define CONFIG_BOOTP_GATEWAY 63 #define CONFIG_BOOTP_HOSTNAME 64 65 66 /* 67 * Command line configuration. 68 */ 69 #include <config_cmd_default.h> 70 71 #define CONFIG_CMD_PCI 72 #define CONFIG_CMD_IRQ 73 #define CONFIG_CMD_ELF 74 #define CONFIG_CMD_I2C 75 #define CONFIG_CMD_BSP 76 #define CONFIG_CMD_EEPROM 77 78 #undef CONFIG_CMD_NET 79 80 81 #undef CONFIG_WATCHDOG /* watchdog disabled */ 82 83 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 84 85 /* 86 * Miscellaneous configurable options 87 */ 88 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 89 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 90 91 #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 92 #ifdef CONFIG_SYS_HUSH_PARSER 93 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 94 #endif 95 96 #if defined(CONFIG_CMD_KGDB) 97 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 98 #else 99 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 100 #endif 101 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 102 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 103 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 104 105 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 106 107 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 108 109 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 110 111 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 112 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 113 114 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ 115 #define CONFIG_SYS_BASE_BAUD 691200 116 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ 117 118 /* The following table includes the supported baudrates */ 119 #define CONFIG_SYS_BAUDRATE_TABLE \ 120 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 121 57600, 115200, 230400, 460800, 921600 } 122 123 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 124 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 125 126 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 127 128 #define CONFIG_LOOPW 1 /* enable loopw command */ 129 130 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 131 132 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ 133 134 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ 135 136 /*----------------------------------------------------------------------- 137 * PCI stuff 138 *----------------------------------------------------------------------- 139 */ 140 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ 141 #define PCI_HOST_FORCE 1 /* configure as pci host */ 142 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 143 144 #define CONFIG_PCI /* include pci support */ 145 #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ 146 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 147 /* resource configuration */ 148 149 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ 150 151 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ 152 153 #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ 154 155 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ 156 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */ 157 #define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ 158 159 #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ 160 #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ 161 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 162 #define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */ 163 #define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */ 164 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ 165 166 /*----------------------------------------------------------------------- 167 * Start addresses for the final memory configuration 168 * (Set up by the startup code) 169 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 170 */ 171 #define CONFIG_SYS_SDRAM_BASE 0x00000000 172 #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 173 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 174 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ 175 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ 176 177 /* 178 * For booting Linux, the board info and command line data 179 * have to be in the first 8 MB of memory, since this is 180 * the maximum mapped by the Linux kernel during initialization. 181 */ 182 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 183 /*----------------------------------------------------------------------- 184 * FLASH organization 185 */ 186 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 187 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 188 189 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 190 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 191 192 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 193 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 194 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 195 196 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 197 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 198 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 199 200 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 201 202 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 203 #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ 204 #define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ 205 206 /*----------------------------------------------------------------------- 207 * I2C EEPROM (CAT24WC16) for environment 208 */ 209 #define CONFIG_HARD_I2C /* I2c with hardware support */ 210 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ 211 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 212 #define CONFIG_SYS_I2C_SLAVE 0x7F 213 214 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 215 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 216 /* mask of address bits that overflow into the "EEPROM chip address" */ 217 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 218 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ 219 /* 16 byte page write mode using*/ 220 /* last 4 bits of the address */ 221 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 222 223 #define CONFIG_SYS_EEPROM_WREN 1 224 225 /* 226 * Init Memory Controller: 227 * 228 * BR0/1 and OR0/1 (FLASH) 229 */ 230 #define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ 231 #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ 232 233 /*----------------------------------------------------------------------- 234 * External Bus Controller (EBC) Setup 235 */ 236 237 /* Memory Bank 0 (Flash Bank 0) initialization */ 238 #define CONFIG_SYS_EBC_PB0AP 0x92015480 239 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ 240 241 /* Memory Bank 2 (PB0) initialization */ 242 #define CONFIG_SYS_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ 243 #define CONFIG_SYS_EBC_PB2CR 0xEF018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 244 245 /* Memory Bank 3 (PB1) initialization */ 246 #define CONFIG_SYS_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ 247 #define CONFIG_SYS_EBC_PB3CR 0xEF118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ 248 249 /*----------------------------------------------------------------------- 250 * Definitions for initial stack pointer and data area (in data cache) 251 */ 252 #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ 253 254 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ 255 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ 256 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 257 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 258 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 259 260 /*----------------------------------------------------------------------- 261 * GPIO definitions 262 */ 263 #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */ 264 #define CONFIG_SYS_SELF_RST (0x80000000 >> 14) /* GPIO14 */ 265 #define CONFIG_SYS_PB_LED (0x80000000 >> 16) /* GPIO16 */ 266 #define CONFIG_SYS_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */ 267 268 /* 269 * Internal Definitions 270 * 271 * Boot Flags 272 */ 273 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 274 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 275 276 #endif /* __CONFIG_H */ 277