1From 02eecf3f85ad03f12babab3067f2c1bcfff35ed3 Mon Sep 17 00:00:00 2001 2From: fanfuqiang <feqin1023@gmail.com> 3Date: Thu, 28 Feb 2019 01:50:13 +0800 4Subject: [PATCH] clear old patchs 5 6--- 7 ...apstone-generate-GenRegisterInfo.inc.patch | 338 ------------- 8 ...pstone-generate-GenSubtargetInfo.inc.patch | 86 ---- 9 ...3-capstone-generate-GenInstrInfo.inc.patch | 130 ----- 10 ...e-generate-GenDisassemblerTables.inc.patch | 472 ------------------ 11 ...5-capstone-generate-GenAsmWriter.inc.patch | 225 --------- 12 ...06-capstone-generate-MappingInsn.inc.patch | 174 ------- 13 ...apstone-generate-GenInsnNameMaps.inc.patch | 110 ---- 14 7 files changed, 1535 deletions(-) 15 delete mode 100644 llvm/0001-capstone-generate-GenRegisterInfo.inc.patch 16 delete mode 100644 llvm/0002-capstone-generate-GenSubtargetInfo.inc.patch 17 delete mode 100644 llvm/0003-capstone-generate-GenInstrInfo.inc.patch 18 delete mode 100644 llvm/0004-capstone-generate-GenDisassemblerTables.inc.patch 19 delete mode 100644 llvm/0005-capstone-generate-GenAsmWriter.inc.patch 20 delete mode 100644 llvm/0006-capstone-generate-MappingInsn.inc.patch 21 delete mode 100644 llvm/0007-capstone-generate-GenInsnNameMaps.inc.patch 22 23diff --git a/llvm/0001-capstone-generate-GenRegisterInfo.inc.patch b/llvm/0001-capstone-generate-GenRegisterInfo.inc.patch 24deleted file mode 100644 25index b51aa515a..000000000 26--- a/llvm/0001-capstone-generate-GenRegisterInfo.inc.patch 27+++ /dev/null 28@@ -1,338 +0,0 @@ 29-From 5d631cb16e7ba5dd0380ff1ee9dda192b1cdad18 Mon Sep 17 00:00:00 2001 30-From: mephi42 <mephi42@gmail.com> 31-Date: Tue, 7 Aug 2018 17:02:40 +0200 32-Subject: [PATCH 1/7] capstone: generate *GenRegisterInfo.inc 33- 34---- 35- utils/TableGen/RegisterInfoEmitter.cpp | 130 ++++++++++++++++++++++--- 36- 1 file changed, 115 insertions(+), 15 deletions(-) 37- 38-diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp 39-index 49016cca799..6ebb7148b1b 100644 40---- a/utils/TableGen/RegisterInfoEmitter.cpp 41-+++ b/utils/TableGen/RegisterInfoEmitter.cpp 42-@@ -99,6 +99,12 @@ private: 43- 44- } // end anonymous namespace 45- 46-+#ifdef CAPSTONE 47-+#define NAME_PREFIX Target.getName() << "_" << 48-+#else 49-+#define NAME_PREFIX 50-+#endif 51-+ 52- // runEnums - Print out enum values for all of the registers. 53- void RegisterInfoEmitter::runEnums(raw_ostream &OS, 54- CodeGenTarget &Target, CodeGenRegBank &Bank) { 55-@@ -107,13 +113,22 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, 56- // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 57- assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 58- 59-+#ifndef CAPSTONE 60- StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); 61-+#endif 62- 63- emitSourceFileHeader("Target Register Enum Values", OS); 64- 65-+#ifdef CAPSTONE 66-+ OS << "/* Capstone Disassembly Engine */\n" 67-+ "/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */\n" 68-+ "\n"; 69-+#endif 70-+ 71- OS << "\n#ifdef GET_REGINFO_ENUM\n"; 72- OS << "#undef GET_REGINFO_ENUM\n\n"; 73- 74-+#ifndef CAPSTONE 75- OS << "namespace llvm {\n\n"; 76- 77- OS << "class MCRegisterClass;\n" 78-@@ -122,16 +137,20 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, 79- 80- if (!Namespace.empty()) 81- OS << "namespace " << Namespace << " {\n"; 82-- OS << "enum {\n NoRegister,\n"; 83-+#endif 84-+ 85-+ OS << "enum {\n " << NAME_PREFIX "NoRegister,\n"; 86- 87- for (const auto &Reg : Registers) 88-- OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; 89-+ OS << " " << NAME_PREFIX Reg.getName() << " = " << Reg.EnumValue << ",\n"; 90- assert(Registers.size() == Registers.back().EnumValue && 91- "Register enum value mismatch!"); 92-- OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 93-+ OS << " " << NAME_PREFIX "NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 94- OS << "};\n"; 95-+#ifndef CAPSTONE 96- if (!Namespace.empty()) 97- OS << "} // end namespace " << Namespace << "\n"; 98-+#endif 99- 100- const auto &RegisterClasses = Bank.getRegClasses(); 101- if (!RegisterClasses.empty()) { 102-@@ -140,18 +159,29 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, 103- assert(RegisterClasses.size() <= 0xffff && 104- "Too many register classes to fit in tables"); 105- 106-- OS << "\n// Register classes\n\n"; 107-+ OS << "\n// Register classes\n"; 108-+#ifndef CAPSTONE 109-+ OS << "\n"; 110- if (!Namespace.empty()) 111- OS << "namespace " << Namespace << " {\n"; 112-+#endif 113- OS << "enum {\n"; 114- for (const auto &RC : RegisterClasses) 115-- OS << " " << RC.getName() << "RegClassID" 116-+ OS << " " << NAME_PREFIX RC.getName() << "RegClassID" 117- << " = " << RC.EnumValue << ",\n"; 118-- OS << "\n };\n"; 119-+#ifdef CAPSTONE 120-+ OS 121-+#else 122-+ OS << "\n " 123-+#endif 124-+ << "};\n"; 125-+#ifndef CAPSTONE 126- if (!Namespace.empty()) 127- OS << "} // end namespace " << Namespace << "\n\n"; 128-+#endif 129- } 130- 131-+#ifndef CAPSTONE 132- const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); 133- // If the only definition is the default NoRegAltName, we don't need to 134- // emit anything. 135-@@ -182,8 +212,11 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, 136- if (!Namespace.empty()) 137- OS << "} // end namespace " << Namespace << "\n\n"; 138- } 139-+#endif 140- 141-+#ifndef CAPSTONE 142- OS << "} // end namespace llvm\n\n"; 143-+#endif 144- OS << "#endif // GET_REGINFO_ENUM\n\n"; 145- } 146- 147-@@ -830,7 +863,9 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 148- 149- const auto &Regs = RegBank.getRegisters(); 150- 151-+#ifndef CAPSTONE 152- auto &SubRegIndices = RegBank.getSubRegIndices(); 153-+#endif 154- // The lists of sub-registers and super-registers go in the same array. That 155- // allows us to share suffixes. 156- typedef std::vector<const CodeGenRegister*> RegVec; 157-@@ -922,25 +957,40 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 158- LaneMaskSeqs.layout(); 159- SubRegIdxSeqs.layout(); 160- 161-+#ifndef CAPSTONE 162- OS << "namespace llvm {\n\n"; 163-+#endif 164- 165- const std::string &TargetName = Target.getName(); 166- 167- // Emit the shared table of differential lists. 168-- OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 169-+#ifdef CAPSTONE 170-+ OS << "static" 171-+#else 172-+ OS << "extern" 173-+#endif 174-+ << " const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 175- DiffSeqs.emit(OS, printDiff16); 176- OS << "};\n\n"; 177- 178-+#ifndef CAPSTONE 179- // Emit the shared table of regunit lane mask sequences. 180- OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; 181- LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); 182- OS << "};\n\n"; 183-+#endif 184- 185- // Emit the table of sub-register indexes. 186-- OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 187-+#ifdef CAPSTONE 188-+ OS << "static" 189-+#else 190-+ OS << "extern" 191-+#endif 192-+ << " const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 193- SubRegIdxSeqs.emit(OS, printSubRegIndex); 194- OS << "};\n\n"; 195- 196-+#ifndef CAPSTONE 197- // Emit the table of sub-register index sizes. 198- OS << "extern const MCRegisterInfo::SubRegCoveredBits " 199- << TargetName << "SubRegIdxRanges[] = {\n"; 200-@@ -950,14 +1000,22 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 201- << Idx.getName() << "\n"; 202- } 203- OS << "};\n\n"; 204-+#endif 205- 206- // Emit the string table. 207- RegStrings.layout(); 208-+#ifndef CAPSTONE 209- OS << "extern const char " << TargetName << "RegStrings[] = {\n"; 210- RegStrings.emit(OS, printChar); 211- OS << "};\n\n"; 212-+#endif 213- 214-- OS << "extern const MCRegisterDesc " << TargetName 215-+#ifdef CAPSTONE 216-+ OS << "static" 217-+#else 218-+ OS << "extern" 219-+#endif 220-+ << " const MCRegisterDesc " << TargetName 221- << "RegDesc[] = { // Descriptors\n"; 222- OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 223- 224-@@ -973,6 +1031,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 225- } 226- OS << "};\n\n"; // End of register descriptors... 227- 228-+#ifndef CAPSTONE 229- // Emit the table of register unit roots. Each regunit has one or two root 230- // registers. 231- OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; 232-@@ -986,11 +1045,14 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 233- OS << " },\n"; 234- } 235- OS << "};\n\n"; 236-+#endif 237- 238- const auto &RegisterClasses = RegBank.getRegClasses(); 239- 240- // Loop over all of the register classes... emitting each one. 241-+#ifndef CAPSTONE 242- OS << "namespace { // Register classes...\n"; 243-+#endif 244- 245- SequenceToOffsetTable<std::string> RegClassStrings; 246- 247-@@ -1005,15 +1067,28 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 248- 249- // Emit the register list now. 250- OS << " // " << Name << " Register Class...\n" 251-- << " const MCPhysReg " << Name 252-+ << " " 253-+#ifdef CAPSTONE 254-+ << "static " 255-+#endif 256-+ << "const MCPhysReg " << Name 257- << "[] = {\n "; 258- for (Record *Reg : Order) { 259-- OS << getQualifiedName(Reg) << ", "; 260-+#ifdef CAPSTONE 261-+ OS << NAME_PREFIX Reg->getName() 262-+#else 263-+ OS << getQualifiedName(Reg) 264-+#endif 265-+ << ", "; 266- } 267- OS << "\n };\n\n"; 268- 269- OS << " // " << Name << " Bit set.\n" 270-- << " const uint8_t " << Name 271-+ << " " 272-+#ifdef CAPSTONE 273-+ << "static " 274-+#endif 275-+ << "const uint8_t " << Name 276- << "Bits[] = {\n "; 277- BitVectorEmitter BVE; 278- for (Record *Reg : Order) { 279-@@ -1023,14 +1098,23 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 280- OS << "\n };\n\n"; 281- 282- } 283-+#ifndef CAPSTONE 284- OS << "} // end anonymous namespace\n\n"; 285-+#endif 286- 287- RegClassStrings.layout(); 288-+#ifndef CAPSTONE 289- OS << "extern const char " << TargetName << "RegClassStrings[] = {\n"; 290- RegClassStrings.emit(OS, printChar); 291- OS << "};\n\n"; 292-+#endif 293- 294-- OS << "extern const MCRegisterClass " << TargetName 295-+#ifdef CAPSTONE 296-+ OS << "static" 297-+#else 298-+ OS << "extern" 299-+#endif 300-+ << " const MCRegisterClass " << TargetName 301- << "MCRegisterClasses[] = {\n"; 302- 303- for (const auto &RC : RegisterClasses) { 304-@@ -1041,7 +1125,12 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 305- OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " 306- << RegClassStrings.get(RC.getName()) << ", " 307- << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " 308-- << RC.getQualifiedName() + "RegClassID" << ", " 309-+#ifdef CAPSTONE 310-+ << NAME_PREFIX RC.getName() 311-+#else 312-+ << RC.getQualifiedName() 313-+#endif 314-+ << "RegClassID" << ", " 315- << RegSize/8 << ", " 316- << RC.CopyCost << ", " 317- << ( RC.Allocatable ? "true" : "false" ) << " },\n"; 318-@@ -1049,6 +1138,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 319- 320- OS << "};\n\n"; 321- 322-+#ifndef CAPSTONE 323- EmitRegMappingTables(OS, Regs, false); 324- 325- // Emit Reg encoding table 326-@@ -1067,7 +1157,9 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 327- OS << " " << Value << ",\n"; 328- } 329- OS << "};\n"; // End of HW encoding table 330-+#endif 331- 332-+#ifndef CAPSTONE 333- // MCRegisterInfo initialization routine. 334- OS << "static inline void Init" << TargetName 335- << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 336-@@ -1088,7 +1180,12 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 337- OS << "}\n\n"; 338- 339- OS << "} // end namespace llvm\n\n"; 340-- OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 341-+#endif 342-+ OS << "#endif // GET_REGINFO_MC_DESC\n" 343-+#ifndef CAPSTONE 344-+ << "\n" 345-+#endif 346-+ ; 347- } 348- 349- void 350-@@ -1568,10 +1665,13 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 351- 352- void RegisterInfoEmitter::run(raw_ostream &OS) { 353- CodeGenRegBank &RegBank = Target.getRegBank(); 354-+ 355- runEnums(OS, Target, RegBank); 356- runMCDesc(OS, Target, RegBank); 357-+#ifndef CAPSTONE 358- runTargetHeader(OS, Target, RegBank); 359- runTargetDesc(OS, Target, RegBank); 360-+#endif 361- 362- if (RegisterInfoDebug) 363- debugDump(errs()); 364--- 365-2.19.1 366- 367diff --git a/llvm/0002-capstone-generate-GenSubtargetInfo.inc.patch b/llvm/0002-capstone-generate-GenSubtargetInfo.inc.patch 368deleted file mode 100644 369index 56ad28256..000000000 370--- a/llvm/0002-capstone-generate-GenSubtargetInfo.inc.patch 371+++ /dev/null 372@@ -1,86 +0,0 @@ 373-From 46ca491e1bbbc9ace2a91fe6a7b112c83b9b88cc Mon Sep 17 00:00:00 2001 374-From: mephi42 <mephi42@gmail.com> 375-Date: Tue, 7 Aug 2018 17:42:59 +0200 376-Subject: [PATCH 2/7] capstone: generate *GenSubtargetInfo.inc 377- 378---- 379- utils/TableGen/SubtargetEmitter.cpp | 28 +++++++++++++++++++++++++++- 380- 1 file changed, 27 insertions(+), 1 deletion(-) 381- 382-diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp 383-index c5da8d8142f..98ab3240472 100644 384---- a/utils/TableGen/SubtargetEmitter.cpp 385-+++ b/utils/TableGen/SubtargetEmitter.cpp 386-@@ -147,7 +147,9 @@ void SubtargetEmitter::Enumeration(raw_ostream &OS) { 387- if (N > MAX_SUBTARGET_FEATURES) 388- PrintFatalError("Too many subtarget features! Bump MAX_SUBTARGET_FEATURES."); 389- 390-+#ifndef CAPSTONE 391- OS << "namespace " << Target << " {\n"; 392-+#endif 393- 394- // Open enumeration. 395- OS << "enum {\n"; 396-@@ -158,12 +160,22 @@ void SubtargetEmitter::Enumeration(raw_ostream &OS) { 397- Record *Def = DefList[i]; 398- 399- // Get and emit name 400-- OS << " " << Def->getName() << " = " << i << ",\n"; 401-+ OS << " " 402-+#ifdef CAPSTONE 403-+ << Target << "_" 404-+#endif 405-+ << Def->getName() << " = " 406-+#ifdef CAPSTONE 407-+ << "1ULL << " 408-+#endif 409-+ << i << ",\n"; 410- } 411- 412- // Close enumeration and namespace 413- OS << "};\n"; 414-+#ifndef CAPSTONE 415- OS << "} // end namespace " << Target << "\n"; 416-+#endif 417- } 418- 419- // 420-@@ -1709,14 +1721,27 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) { 421- void SubtargetEmitter::run(raw_ostream &OS) { 422- emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); 423- 424-+#ifdef CAPSTONE 425-+ OS << "/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n" 426-+ "/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */\n" 427-+ "\n"; 428-+#endif 429-+ 430- OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n"; 431- OS << "#undef GET_SUBTARGETINFO_ENUM\n\n"; 432- 433-+#ifndef CAPSTONE 434- OS << "namespace llvm {\n"; 435-+#endif 436- Enumeration(OS); 437-+#ifdef CAPSTONE 438-+ OS << "\n"; 439-+#else 440- OS << "} // end namespace llvm\n\n"; 441-+#endif 442- OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; 443- 444-+#ifndef CAPSTONE 445- OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n"; 446- OS << "#undef GET_SUBTARGETINFO_MC_DESC\n\n"; 447- 448-@@ -1857,6 +1882,7 @@ void SubtargetEmitter::run(raw_ostream &OS) { 449- OS << "} // end namespace llvm\n\n"; 450- 451- OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n"; 452-+#endif 453- } 454- 455- namespace llvm { 456--- 457-2.19.1 458- 459diff --git a/llvm/0003-capstone-generate-GenInstrInfo.inc.patch b/llvm/0003-capstone-generate-GenInstrInfo.inc.patch 460deleted file mode 100644 461index 2baa59fc9..000000000 462--- a/llvm/0003-capstone-generate-GenInstrInfo.inc.patch 463+++ /dev/null 464@@ -1,130 +0,0 @@ 465-From a73fe8ac18d3ca81fa7a8d8c404cd7e0faf92ddc Mon Sep 17 00:00:00 2001 466-From: mephi42 <mephi42@gmail.com> 467-Date: Tue, 7 Aug 2018 17:59:43 +0200 468-Subject: [PATCH 3/7] capstone: generate *GenInstrInfo.inc 469- 470---- 471- utils/TableGen/InstrInfoEmitter.cpp | 49 ++++++++++++++++++++++++++--- 472- 1 file changed, 44 insertions(+), 5 deletions(-) 473- 474-diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp 475-index 0aff1aa6f94..2f3a2729262 100644 476---- a/utils/TableGen/InstrInfoEmitter.cpp 477-+++ b/utils/TableGen/InstrInfoEmitter.cpp 478-@@ -92,6 +92,7 @@ private: 479- 480- } // end anonymous namespace 481- 482-+#ifndef CAPSTONE 483- static void PrintDefList(const std::vector<Record*> &Uses, 484- unsigned Num, raw_ostream &OS) { 485- OS << "static const MCPhysReg ImplicitList" << Num << "[] = { "; 486-@@ -99,6 +100,7 @@ static void PrintDefList(const std::vector<Record*> &Uses, 487- OS << getQualifiedName(U) << ", "; 488- OS << "0 };\n"; 489- } 490-+#endif 491- 492- //===----------------------------------------------------------------------===// 493- // Operand Info Emission. 494-@@ -426,8 +428,17 @@ void InstrInfoEmitter::emitTIIHelperMethods(raw_ostream &OS) { 495- // run - Emit the main instruction description records for the target... 496- void InstrInfoEmitter::run(raw_ostream &OS) { 497- emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS); 498-+ 499-+#ifdef CAPSTONE 500-+ OS << "/* Capstone Disassembly Engine */\n" 501-+ "/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */\n" 502-+ "\n" 503-+ "\n"; 504-+#endif 505-+ 506- emitEnums(OS); 507- 508-+#ifndef CAPSTONE 509- OS << "#ifdef GET_INSTRINFO_MC_DESC\n"; 510- OS << "#undef GET_INSTRINFO_MC_DESC\n"; 511- 512-@@ -545,6 +556,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) { 513- emitOperandTypesEnum(OS, Target); 514- 515- emitMCIIHelperMethods(OS); 516-+#endif 517- } 518- 519- void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, 520-@@ -659,7 +671,9 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) { 521- OS << "#ifdef GET_INSTRINFO_ENUM\n"; 522- OS << "#undef GET_INSTRINFO_ENUM\n"; 523- 524-+#ifndef CAPSTONE 525- OS << "namespace llvm {\n\n"; 526-+#endif 527- 528- CodeGenTarget Target(Records); 529- 530-@@ -669,17 +683,39 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) { 531- if (Namespace.empty()) 532- PrintFatalError("No instructions defined!"); 533- 534-+#ifndef CAPSTONE 535- OS << "namespace " << Namespace << " {\n"; 536-- OS << " enum {\n"; 537-+#endif 538-+#ifdef CAPSTONE 539-+ OS << "\n" 540-+#else 541-+ OS << " " 542-+#endif 543-+ << "enum {\n"; 544- unsigned Num = 0; 545- for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) 546-- OS << " " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n"; 547-- OS << " INSTRUCTION_LIST_END = " << Num << "\n"; 548-+ OS << " " 549-+#ifdef CAPSTONE 550-+ << Target.getName() << "_" 551-+#endif 552-+ << Inst->TheDef->getName() << "\t= " << Num++ << ",\n"; 553-+ OS << " " 554-+#ifdef CAPSTONE 555-+ << Target.getName() << "_" 556-+#endif 557-+ << "INSTRUCTION_LIST_END = " << Num << "\n"; 558- OS << " };\n\n"; 559-+#ifndef CAPSTONE 560- OS << "} // end " << Namespace << " namespace\n"; 561- OS << "} // end llvm namespace\n"; 562-- OS << "#endif // GET_INSTRINFO_ENUM\n\n"; 563-- 564-+#endif 565-+ OS << "#endif // GET_INSTRINFO_ENUM\n" 566-+#ifndef CAPSTONE 567-+ << "\n" 568-+#endif 569-+ ; 570-+ 571-+#ifndef CAPSTONE 572- OS << "#ifdef GET_INSTRINFO_SCHED_ENUM\n"; 573- OS << "#undef GET_INSTRINFO_SCHED_ENUM\n"; 574- OS << "namespace llvm {\n\n"; 575-@@ -696,13 +732,16 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) { 576- OS << "} // end llvm namespace\n"; 577- 578- OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n"; 579-+#endif 580- } 581- 582- namespace llvm { 583- 584- void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) { 585- InstrInfoEmitter(RK).run(OS); 586-+#ifndef CAPSTONE 587- EmitMapTable(RK, OS); 588-+#endif 589- } 590- 591- } // end llvm namespace 592--- 593-2.19.1 594- 595diff --git a/llvm/0004-capstone-generate-GenDisassemblerTables.inc.patch b/llvm/0004-capstone-generate-GenDisassemblerTables.inc.patch 596deleted file mode 100644 597index 0002b81b4..000000000 598--- a/llvm/0004-capstone-generate-GenDisassemblerTables.inc.patch 599+++ /dev/null 600@@ -1,472 +0,0 @@ 601-From 29da4c6929679b8ac4019767ab4ebcd83c9894b4 Mon Sep 17 00:00:00 2001 602-From: mephi42 <mephi42@gmail.com> 603-Date: Tue, 7 Aug 2018 18:20:17 +0200 604-Subject: [PATCH 4/7] capstone: generate *GenDisassemblerTables.inc 605- 606---- 607- utils/TableGen/DisassemblerEmitter.cpp | 12 +- 608- utils/TableGen/FixedLenDecoderEmitter.cpp | 248 ++++++++++++++++++++-- 609- 2 files changed, 239 insertions(+), 21 deletions(-) 610- 611-diff --git a/utils/TableGen/DisassemblerEmitter.cpp b/utils/TableGen/DisassemblerEmitter.cpp 612-index b99a0a973a2..2ac6d89645c 100644 613---- a/utils/TableGen/DisassemblerEmitter.cpp 614-+++ b/utils/TableGen/DisassemblerEmitter.cpp 615-@@ -106,6 +106,11 @@ extern void EmitFixedLenDecoder(RecordKeeper &RK, raw_ostream &OS, 616- void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) { 617- CodeGenTarget Target(Records); 618- emitSourceFileHeader(" * " + Target.getName().str() + " Disassembler", OS); 619-+#ifdef CAPSTONE 620-+ OS << "/* Capstone Disassembly Engine */\n" 621-+ "/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */\n" 622-+ "\n"; 623-+#endif 624- 625- // X86 uses a custom disassembler. 626- if (Target.getName() == "X86") { 627-@@ -150,7 +155,12 @@ void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) { 628- } 629- 630- EmitFixedLenDecoder(Records, OS, Target.getName(), 631-- "if (", " == MCDisassembler::Fail)", 632-+ "if (", 633-+#ifdef CAPSTONE 634-+ " == MCDisassembler_Fail)", 635-+#else 636-+ " == MCDisassembler::Fail)", 637-+#endif 638- "MCDisassembler::Success", "MCDisassembler::Fail", ""); 639- } 640- 641-diff --git a/utils/TableGen/FixedLenDecoderEmitter.cpp b/utils/TableGen/FixedLenDecoderEmitter.cpp 642-index fcecc764d44..36845d960d8 100644 643---- a/utils/TableGen/FixedLenDecoderEmitter.cpp 644-+++ b/utils/TableGen/FixedLenDecoderEmitter.cpp 645-@@ -730,7 +730,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, 646- ++I; 647- unsigned Start = *I++; 648- unsigned Len = *I++; 649-- OS.indent(Indentation) << "MCD::OPC_ExtractField, " << Start << ", " 650-+ OS.indent(Indentation) 651-+#ifdef CAPSTONE 652-+ << "MCD_OPC_ExtractField" 653-+#else 654-+ << "MCD::OPC_ExtractField" 655-+#endif 656-+ << ", " << Start << ", " 657- << Len << ", // Inst{"; 658- if (Len > 1) 659- OS << (Start + Len - 1) << "-"; 660-@@ -739,7 +745,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, 661- } 662- case MCD::OPC_FilterValue: { 663- ++I; 664-- OS.indent(Indentation) << "MCD::OPC_FilterValue, "; 665-+ OS.indent(Indentation) 666-+#ifdef CAPSTONE 667-+ << "MCD_OPC_FilterValue" 668-+#else 669-+ << "MCD::OPC_FilterValue" 670-+#endif 671-+ << ", "; 672- // The filter value is ULEB128 encoded. 673- while (*I >= 128) 674- OS << (unsigned)*I++ << ", "; 675-@@ -759,7 +771,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, 676- ++I; 677- unsigned Start = *I++; 678- unsigned Len = *I++; 679-- OS.indent(Indentation) << "MCD::OPC_CheckField, " << Start << ", " 680-+ OS.indent(Indentation) 681-+#ifdef CAPSTONE 682-+ << "MCD_OPC_CheckField" 683-+#else 684-+ << "MCD::OPC_CheckField" 685-+#endif 686-+ << ", " << Start << ", " 687- << Len << ", ";// << Val << ", " << NumToSkip << ",\n"; 688- // ULEB128 encoded field value. 689- for (; *I >= 128; ++I) 690-@@ -777,7 +795,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, 691- } 692- case MCD::OPC_CheckPredicate: { 693- ++I; 694-- OS.indent(Indentation) << "MCD::OPC_CheckPredicate, "; 695-+ OS.indent(Indentation) 696-+#ifdef CAPSTONE 697-+ << "MCD_OPC_CheckPredicate" 698-+#else 699-+ << "MCD::OPC_CheckPredicate" 700-+#endif 701-+ << ", "; 702- for (; *I >= 128; ++I) 703- OS << (unsigned)*I << ", "; 704- OS << (unsigned)*I++ << ", "; 705-@@ -803,7 +827,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, 706- && "ULEB128 value too large!"); 707- // Decode the Opcode value. 708- unsigned Opc = decodeULEB128(Buffer); 709-- OS.indent(Indentation) << "MCD::OPC_" << (IsTry ? "Try" : "") 710-+ OS.indent(Indentation) 711-+#ifdef CAPSTONE 712-+ << "MCD_OPC_" 713-+#else 714-+ << "MCD::OPC_" 715-+#endif 716-+ << (IsTry ? "Try" : "") 717- << "Decode, "; 718- for (p = Buffer; *p >= 128; ++p) 719- OS << (unsigned)*p << ", "; 720-@@ -837,7 +867,12 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, 721- } 722- case MCD::OPC_SoftFail: { 723- ++I; 724-- OS.indent(Indentation) << "MCD::OPC_SoftFail"; 725-+ OS.indent(Indentation) 726-+#ifdef CAPSTONE 727-+ << "MCD_OPC_SoftFail"; 728-+#else 729-+ << "MCD::OPC_SoftFail"; 730-+#endif 731- // Positive mask 732- uint64_t Value = 0; 733- unsigned Shift = 0; 734-@@ -869,7 +904,13 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, 735- } 736- case MCD::OPC_Fail: { 737- ++I; 738-- OS.indent(Indentation) << "MCD::OPC_Fail,\n"; 739-+ OS.indent(Indentation) 740-+#ifdef CAPSTONE 741-+ << "MCD_OPC_Fail" 742-+#else 743-+ << "MCD::OPC_Fail" 744-+#endif 745-+ << ",\n"; 746- break; 747- } 748- } 749-@@ -884,23 +925,46 @@ void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS, 750- void FixedLenDecoderEmitter:: 751- emitPredicateFunction(formatted_raw_ostream &OS, PredicateSet &Predicates, 752- unsigned Indentation) const { 753-+#ifdef CAPSTONE 754-+ OS.indent(Indentation) << "static bool getbool(uint64_t b)\n"; 755-+ OS.indent(Indentation) << "{\n"; 756-+ OS.indent(Indentation) << "\treturn b != 0;\n"; 757-+ OS.indent(Indentation) << "}\n\n"; 758-+#endif 759-+ 760- // The predicate function is just a big switch statement based on the 761- // input predicate index. 762- OS.indent(Indentation) << "static bool checkDecoderPredicate(unsigned Idx, " 763-+#ifdef CAPSTONE 764-+ << "uint64_t Bits)\n{\n"; 765-+#else 766- << "const FeatureBitset& Bits) {\n"; 767-+#endif 768- Indentation += 2; 769- if (!Predicates.empty()) { 770- OS.indent(Indentation) << "switch (Idx) {\n"; 771-- OS.indent(Indentation) << "default: llvm_unreachable(\"Invalid index!\");\n"; 772-+ OS.indent(Indentation) << "default: " 773-+#ifdef CAPSTONE 774-+ << "// " 775-+#endif 776-+ << "llvm_unreachable(\"Invalid index!\");\n"; 777- unsigned Index = 0; 778- for (const auto &Predicate : Predicates) { 779- OS.indent(Indentation) << "case " << Index++ << ":\n"; 780-- OS.indent(Indentation+2) << "return (" << Predicate << ");\n"; 781-+ OS.indent(Indentation+2) << "return " 782-+#ifdef CAPSTONE 783-+ << "getbool" 784-+#endif 785-+ << "(" << Predicate << ");\n"; 786- } 787- OS.indent(Indentation) << "}\n"; 788- } else { 789- // No case statement to emit 790-- OS.indent(Indentation) << "llvm_unreachable(\"Invalid index!\");\n"; 791-+ OS.indent(Indentation) 792-+#ifdef CAPSTONE 793-+ << "// " 794-+#endif 795-+ << "llvm_unreachable(\"Invalid index!\");\n"; 796- } 797- Indentation -= 2; 798- OS.indent(Indentation) << "}\n\n"; 799-@@ -911,23 +975,39 @@ emitDecoderFunction(formatted_raw_ostream &OS, DecoderSet &Decoders, 800- unsigned Indentation) const { 801- // The decoder function is just a big switch statement based on the 802- // input decoder index. 803-+#ifdef CAPSTONE 804-+#define EDF_EOL " \\\n" 805-+ OS.indent(Indentation) << "#define DecodeToMCInst(fname,fieldname, InsnType) \\\n"; 806-+ OS.indent(Indentation) << "static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \\\n"; 807-+ OS.indent(Indentation) << " uint64_t Address, const void *Decoder) \\\n"; 808-+ OS.indent(Indentation) << "{ \\\n"; 809-+#else 810-+#define EDF_EOL "\n" 811- OS.indent(Indentation) << "template<typename InsnType>\n"; 812- OS.indent(Indentation) << "static DecodeStatus decodeToMCInst(DecodeStatus S," 813- << " unsigned Idx, InsnType insn, MCInst &MI,\n"; 814- OS.indent(Indentation) << " uint64_t " 815- << "Address, const void *Decoder, bool &DecodeComplete) {\n"; 816-+#endif 817- Indentation += 2; 818-+#ifndef CAPSTONE 819- OS.indent(Indentation) << "DecodeComplete = true;\n"; 820-- OS.indent(Indentation) << "InsnType tmp;\n"; 821-- OS.indent(Indentation) << "switch (Idx) {\n"; 822-- OS.indent(Indentation) << "default: llvm_unreachable(\"Invalid index!\");\n"; 823-+#endif 824-+ OS.indent(Indentation) << "InsnType tmp;" EDF_EOL; 825-+ OS.indent(Indentation) << "switch (Idx) {" EDF_EOL; 826-+ OS.indent(Indentation) << "default:" 827-+#ifndef CAPSTONE 828-+ << " llvm_unreachable(\"Invalid index!\");\n"; 829-+#else 830-+ << " \\\n"; 831-+#endif 832- unsigned Index = 0; 833- for (const auto &Decoder : Decoders) { 834-- OS.indent(Indentation) << "case " << Index++ << ":\n"; 835-+ OS.indent(Indentation) << "case " << Index++ << ":" EDF_EOL; 836- OS << Decoder; 837-- OS.indent(Indentation+2) << "return S;\n"; 838-+ OS.indent(Indentation+2) << "return S;" EDF_EOL; 839- } 840-- OS.indent(Indentation) << "}\n"; 841-+ OS.indent(Indentation) << "}" EDF_EOL; 842- Indentation -= 2; 843- OS.indent(Indentation) << "}\n\n"; 844- } 845-@@ -1054,16 +1134,21 @@ void FilterChooser::emitBinaryParser(raw_ostream &o, unsigned &Indentation, 846- const std::string &Decoder = OpInfo.Decoder; 847- 848- if (OpInfo.numFields() != 1) 849-- o.indent(Indentation) << "tmp = 0;\n"; 850-+ o.indent(Indentation) << "tmp = 0;" EDF_EOL; 851- 852- for (const EncodingField &EF : OpInfo) { 853- o.indent(Indentation) << "tmp "; 854- if (OpInfo.numFields() != 1) o << '|'; 855-- o << "= fieldFromInstruction" 856-+ o << "= " 857-+#ifdef CAPSTONE 858-+ << "fieldname" 859-+#else 860-+ << "fieldFromInstruction" 861-+#endif 862- << "(insn, " << EF.Base << ", " << EF.Width << ')'; 863- if (OpInfo.numFields() != 1 || EF.Offset != 0) 864- o << " << " << EF.Offset; 865-- o << ";\n"; 866-+ o << ";" EDF_EOL; 867- } 868- 869- if (Decoder != "") { 870-@@ -1071,8 +1156,12 @@ void FilterChooser::emitBinaryParser(raw_ostream &o, unsigned &Indentation, 871- o.indent(Indentation) << Emitter->GuardPrefix << Decoder 872- << "(MI, tmp, Address, Decoder)" 873- << Emitter->GuardPostfix 874-+#ifdef CAPSTONE 875-+ << " return MCDisassembler_Fail; \\\n"; 876-+#else 877- << " { " << (OpHasCompleteDecoder ? "" : "DecodeComplete = false; ") 878- << "return MCDisassembler::Fail; }\n"; 879-+#endif 880- } else { 881- OpHasCompleteDecoder = true; 882- o.indent(Indentation) << "MI.addOperand(MCOperand::createImm(tmp));\n"; 883-@@ -1091,7 +1180,13 @@ void FilterChooser::emitDecoder(raw_ostream &OS, unsigned Indentation, 884- << "(MI, insn, Address, Decoder)" 885- << Emitter->GuardPostfix 886- << " { " << (HasCompleteDecoder ? "" : "DecodeComplete = false; ") 887-- << "return MCDisassembler::Fail; }\n"; 888-+ << "return " 889-+#ifdef CAPSTONE 890-+ << "MCDisassembler_Fail" 891-+#else 892-+ << "MCDisassembler::Fail" 893-+#endif 894-+ << "; }\n"; 895- break; 896- } 897- 898-@@ -1129,10 +1224,19 @@ unsigned FilterChooser::getDecoderIndex(DecoderSet &Decoders, 899- static void emitSinglePredicateMatch(raw_ostream &o, StringRef str, 900- const std::string &PredicateNamespace) { 901- if (str[0] == '!') 902-+#ifdef CAPSTONE 903-+ o << "~(Bits & " << PredicateNamespace << "_" 904-+ << str.slice(1,str.size()) << ")"; 905-+#else 906- o << "!Bits[" << PredicateNamespace << "::" 907- << str.slice(1,str.size()) << "]"; 908-+#endif 909- else 910-+#ifdef CAPSTONE 911-+ o << "(Bits & " << PredicateNamespace << "_" << str << ")"; 912-+#else 913- o << "Bits[" << PredicateNamespace << "::" << str << "]"; 914-+#endif 915- } 916- 917- bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation, 918-@@ -2047,6 +2151,17 @@ static bool populateInstruction(CodeGenTarget &Target, 919- // fieldFromInstruction(). 920- static void emitFieldFromInstruction(formatted_raw_ostream &OS) { 921- OS << "// Helper function for extracting fields from encoded instructions.\n" 922-+#ifdef CAPSTONE 923-+ << "#define FieldFromInstruction(fname, InsnType) \\\n" 924-+ << "static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \\\n" 925-+ << "{ \\\n" 926-+ << " InsnType fieldMask; \\\n" 927-+ << " if (numBits == sizeof(InsnType)*8) \\\n" 928-+ << " fieldMask = (InsnType)(-1LL); \\\n" 929-+ << " else \\\n" 930-+ << " fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \\\n" 931-+ << " return (insn & fieldMask) >> startBit; \\\n" 932-+#else 933- << "template<typename InsnType>\n" 934- << "static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,\n" 935- << " unsigned numBits) {\n" 936-@@ -2058,12 +2173,92 @@ static void emitFieldFromInstruction(formatted_raw_ostream &OS) { 937- << " else\n" 938- << " fieldMask = (((InsnType)1 << numBits) - 1) << startBit;\n" 939- << " return (insn & fieldMask) >> startBit;\n" 940-+#endif 941- << "}\n\n"; 942- } 943- 944- // emitDecodeInstruction - Emit the templated helper function 945- // decodeInstruction(). 946- static void emitDecodeInstruction(formatted_raw_ostream &OS) { 947-+#ifdef CAPSTONE 948-+ OS << "#define DecodeInstruction(fname, fieldname, decoder, InsnType) \\\n" 949-+ << "static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \\\n" 950-+ << " InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \\\n" 951-+ << "{ \\\n" 952-+ << " uint64_t Bits = getFeatureBits(feature); \\\n" 953-+ << " const uint8_t *Ptr = DecodeTable; \\\n" 954-+ << " uint32_t CurFieldValue = 0, ExpectedValue; \\\n" 955-+ << " DecodeStatus S = MCDisassembler_Success; \\\n" 956-+ << " unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \\\n" 957-+ << " InsnType Val, FieldValue, PositiveMask, NegativeMask; \\\n" 958-+ << " bool Pred, Fail; \\\n" 959-+ << " for (;;) { \\\n" 960-+ << " switch (*Ptr) { \\\n" 961-+ << " default: \\\n" 962-+ << " return MCDisassembler_Fail; \\\n" 963-+ << " case MCD_OPC_ExtractField: { \\\n" 964-+ << " Start = *++Ptr; \\\n" 965-+ << " Len = *++Ptr; \\\n" 966-+ << " ++Ptr; \\\n" 967-+ << " CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \\\n" 968-+ << " break; \\\n" 969-+ << " } \\\n" 970-+ << " case MCD_OPC_FilterValue: { \\\n" 971-+ << " Val = (InsnType)decodeULEB128(++Ptr, &Len); \\\n" 972-+ << " Ptr += Len; \\\n" 973-+ << " NumToSkip = *Ptr++; \\\n" 974-+ << " NumToSkip |= (*Ptr++) << 8; \\\n" 975-+ << " if (Val != CurFieldValue) \\\n" 976-+ << " Ptr += NumToSkip; \\\n" 977-+ << " break; \\\n" 978-+ << " } \\\n" 979-+ << " case MCD_OPC_CheckField: { \\\n" 980-+ << " Start = *++Ptr; \\\n" 981-+ << " Len = *++Ptr; \\\n" 982-+ << " FieldValue = fieldname(insn, Start, Len); \\\n" 983-+ << " ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \\\n" 984-+ << " Ptr += Len; \\\n" 985-+ << " NumToSkip = *Ptr++; \\\n" 986-+ << " NumToSkip |= (*Ptr++) << 8; \\\n" 987-+ << " if (ExpectedValue != FieldValue) \\\n" 988-+ << " Ptr += NumToSkip; \\\n" 989-+ << " break; \\\n" 990-+ << " } \\\n" 991-+ << " case MCD_OPC_CheckPredicate: { \\\n" 992-+ << " PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \\\n" 993-+ << " Ptr += Len; \\\n" 994-+ << " NumToSkip = *Ptr++; \\\n" 995-+ << " NumToSkip |= (*Ptr++) << 8; \\\n" 996-+ << " Pred = checkDecoderPredicate(PIdx, Bits); \\\n" 997-+ << " if (!Pred) \\\n" 998-+ << " Ptr += NumToSkip; \\\n" 999-+ << " (void)Pred; \\\n" 1000-+ << " break; \\\n" 1001-+ << " } \\\n" 1002-+ << " case MCD_OPC_Decode: { \\\n" 1003-+ << " Opc = (unsigned)decodeULEB128(++Ptr, &Len); \\\n" 1004-+ << " Ptr += Len; \\\n" 1005-+ << " DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \\\n" 1006-+ << " Ptr += Len; \\\n" 1007-+ << " MCInst_setOpcode(MI, Opc); \\\n" 1008-+ << " return decoder(S, DecodeIdx, insn, MI, Address, MRI); \\\n" 1009-+ << " } \\\n" 1010-+ << " case MCD_OPC_SoftFail: { \\\n" 1011-+ << " PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \\\n" 1012-+ << " Ptr += Len; \\\n" 1013-+ << " NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \\\n" 1014-+ << " Ptr += Len; \\\n" 1015-+ << " Fail = (insn & PositiveMask) || (~insn & NegativeMask); \\\n" 1016-+ << " if (Fail) \\\n" 1017-+ << " S = MCDisassembler_SoftFail; \\\n" 1018-+ << " break; \\\n" 1019-+ << " } \\\n" 1020-+ << " case MCD_OPC_Fail: { \\\n" 1021-+ << " return MCDisassembler_Fail; \\\n" 1022-+ << " } \\\n" 1023-+ << " } \\\n" 1024-+ << " } \\\n" 1025-+#else 1026- OS << "template<typename InsnType>\n" 1027- << "static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], " 1028- "MCInst &MI,\n" 1029-@@ -2240,12 +2435,18 @@ static void emitDecodeInstruction(formatted_raw_ostream &OS) { 1030- << " }\n" 1031- << " llvm_unreachable(\"bogosity detected in disassembler state " 1032- "machine!\");\n" 1033-+#endif 1034- << "}\n\n"; 1035- } 1036- 1037- // Emits disassembler code for instruction decoding. 1038- void FixedLenDecoderEmitter::run(raw_ostream &o) { 1039- formatted_raw_ostream OS(o); 1040-+#ifdef CAPSTONE 1041-+ OS << "#include \"../../MCInst.h\"\n"; 1042-+ OS << "#include \"../../LEB128.h\"\n"; 1043-+ OS << "\n"; 1044-+#else 1045- OS << "#include \"llvm/MC/MCInst.h\"\n"; 1046- OS << "#include \"llvm/Support/Debug.h\"\n"; 1047- OS << "#include \"llvm/Support/DataTypes.h\"\n"; 1048-@@ -2254,6 +2455,7 @@ void FixedLenDecoderEmitter::run(raw_ostream &o) { 1049- OS << "#include <assert.h>\n"; 1050- OS << '\n'; 1051- OS << "namespace llvm {\n\n"; 1052-+#endif 1053- 1054- emitFieldFromInstruction(OS); 1055- 1056-@@ -2322,7 +2524,13 @@ void FixedLenDecoderEmitter::run(raw_ostream &o) { 1057- // Emit the main entry point for the decoder, decodeInstruction(). 1058- emitDecodeInstruction(OS); 1059- 1060-+#ifdef CAPSTONE 1061-+ OS << "FieldFromInstruction(fieldFromInstruction, uint64_t)\n"; 1062-+ OS << "DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint64_t)\n"; 1063-+ OS << "DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint64_t)\n"; 1064-+#else 1065- OS << "\n} // End llvm namespace\n"; 1066-+#endif 1067- } 1068- 1069- namespace llvm { 1070--- 1071-2.19.1 1072- 1073diff --git a/llvm/0005-capstone-generate-GenAsmWriter.inc.patch b/llvm/0005-capstone-generate-GenAsmWriter.inc.patch 1074deleted file mode 100644 1075index cd1353eb7..000000000 1076--- a/llvm/0005-capstone-generate-GenAsmWriter.inc.patch 1077+++ /dev/null 1078@@ -1,225 +0,0 @@ 1079-From 5569e48b9cb34a33910e1e850fbfabc999f016a2 Mon Sep 17 00:00:00 2001 1080-From: mephi42 <mephi42@gmail.com> 1081-Date: Tue, 7 Aug 2018 20:00:08 +0200 1082-Subject: [PATCH 5/7] capstone: generate *GenAsmWriter.inc 1083- 1084---- 1085- utils/TableGen/AsmWriterEmitter.cpp | 89 +++++++++++++++++++++++++++-- 1086- utils/TableGen/AsmWriterInst.cpp | 4 ++ 1087- 2 files changed, 87 insertions(+), 6 deletions(-) 1088- 1089-diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp 1090-index 3c4c9c8e5c6..133800d217c 100644 1091---- a/utils/TableGen/AsmWriterEmitter.cpp 1092-+++ b/utils/TableGen/AsmWriterEmitter.cpp 1093-@@ -272,16 +272,22 @@ static void UnescapeString(std::string &Str) { 1094- /// clearing the Instructions vector. 1095- void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { 1096- Record *AsmWriter = Target.getAsmWriter(); 1097-+#ifndef CAPSTONE 1098- StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 1099-+#endif 1100- bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); 1101- 1102- O << 1103- "/// printInstruction - This method is automatically generated by tablegen\n" 1104- "/// from the instruction set description.\n" 1105-+#ifdef CAPSTONE 1106-+ "static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)\n{\n"; 1107-+#else 1108- "void " << Target.getName() << ClassName 1109- << "::printInstruction(const MCInst *MI, " 1110- << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") 1111- << "raw_ostream &O) {\n"; 1112-+#endif 1113- 1114- // Build an aggregate string, and build a table of offsets into it. 1115- SequenceToOffsetTable<std::string> StringTable; 1116-@@ -379,9 +385,16 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { 1117- } 1118- 1119- // Emit the string table itself. 1120-+#ifdef CAPSTONE 1121-+ O << "#ifndef CAPSTONE_DIET\n"; 1122-+#endif 1123- O << " static const char AsmStrs[] = {\n"; 1124- StringTable.emit(O, printChar); 1125-- O << " };\n\n"; 1126-+ O << " };\n" 1127-+#ifdef CAPSTONE 1128-+ << "#endif\n" 1129-+#endif 1130-+ << "\n"; 1131- 1132- // Emit the lookup tables in pieces to minimize wasted bytes. 1133- unsigned BytesNeeded = ((OpcodeInfoBits - BitsLeft) + 7) / 8; 1134-@@ -409,21 +422,45 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { 1135- // If the total bits is more than 32-bits we need to use a 64-bit type. 1136- if (BitsLeft < (OpcodeInfoBits - 32)) 1137- BitsOS << "(uint64_t)"; 1138-- BitsOS << "OpInfo" << Table << "[MI->getOpcode()] << " << Shift << ";\n"; 1139-+ BitsOS << "OpInfo" << Table << "[" 1140-+#ifdef CAPSTONE 1141-+ << "MCInst_getOpcode(MI)" 1142-+#else 1143-+ << "MI->getOpcode()" 1144-+#endif 1145-+ << "] << " << Shift << ";\n"; 1146- // Prepare the shift for the next iteration and increment the table count. 1147- Shift += TableSize; 1148- ++Table; 1149- } 1150- 1151- // Emit the initial tab character. 1152-+#ifndef CAPSTONE 1153- O << " O << \"\\t\";\n\n"; 1154-+#endif 1155- 1156- O << " // Emit the opcode for the instruction.\n"; 1157- O << BitsString; 1158- 1159- // Emit the starting string. 1160-- O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" 1161-- << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n"; 1162-+ O << " " 1163-+#ifdef CAPSTONE 1164-+ << "// " 1165-+#endif 1166-+ << "assert(Bits != 0 && \"Cannot print this instruction.\");\n" 1167-+#ifdef CAPSTONE 1168-+ << "#ifndef CAPSTONE_DIET\n" 1169-+ << " SStream_concat0(O, " 1170-+#else 1171-+ << " O << " 1172-+#endif 1173-+ << "AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1" 1174-+#ifdef CAPSTONE 1175-+ << ");\n" 1176-+ << "#endif\n\n"; 1177-+#else 1178-+ << ");\n\n"; 1179-+#endif 1180- 1181- // Output the table driven operand information. 1182- BitsLeft = OpcodeInfoBits-AsmStrBits; 1183-@@ -455,7 +492,11 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { 1184- O << " switch ((Bits >> " 1185- << (OpcodeInfoBits-BitsLeft) << ") & " 1186- << ((1 << NumBits)-1) << ") {\n" 1187-- << " default: llvm_unreachable(\"Invalid command number.\");\n"; 1188-+ << " default: " 1189-+#ifdef CAPSTONE 1190-+ << "// " 1191-+#endif 1192-+ << "llvm_unreachable(\"Invalid command number.\");\n"; 1193- 1194- // Print out all the cases. 1195- for (unsigned j = 0, e = Commands.size(); j != e; ++j) { 1196-@@ -536,6 +577,9 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName, 1197- } 1198- 1199- StringTable.layout(); 1200-+#ifdef CAPSTONE 1201-+ O << "#ifndef CAPSTONE_DIET\n"; 1202-+#endif 1203- O << " static const char AsmStrs" << AltName << "[] = {\n"; 1204- StringTable.emit(O, printChar); 1205- O << " };\n\n"; 1206-@@ -552,8 +596,10 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName, 1207- } 1208- 1209- void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { 1210-+#ifndef CAPSTONE 1211- Record *AsmWriter = Target.getAsmWriter(); 1212- StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 1213-+#endif 1214- const auto &Registers = Target.getRegBank().getRegisters(); 1215- const std::vector<Record*> &AltNameIndices = Target.getRegAltNameIndices(); 1216- bool hasAltNames = AltNameIndices.size() > 1; 1217-@@ -563,12 +609,20 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { 1218- "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" 1219- "/// from the register set description. This returns the assembler name\n" 1220- "/// for the specified register.\n" 1221-+#ifdef CAPSTONE 1222-+ "static const char *getRegisterName(unsigned RegNo)\n{\n"; 1223-+#else 1224- "const char *" << Target.getName() << ClassName << "::"; 1225- if (hasAltNames) 1226- O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n"; 1227- else 1228- O << "getRegisterName(unsigned RegNo) {\n"; 1229-- O << " assert(RegNo && RegNo < " << (Registers.size()+1) 1230-+#endif 1231-+ O << " " 1232-+#ifdef CAPSTONE 1233-+ << "// " 1234-+#endif 1235-+ << "assert(RegNo && RegNo < " << (Registers.size()+1) 1236- << " && \"Invalid register number!\");\n" 1237- << "\n"; 1238- 1239-@@ -595,10 +649,22 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { 1240- } 1241- O << " }\n"; 1242- } else { 1243-+#ifdef CAPSTONE 1244-+ O << " //int i;\n" 1245-+ << " //for (i = 0; i < sizeof(RegAsmOffset); i++)\n" 1246-+ << " // printf(\"%s = %u\\n\", AsmStrs+RegAsmOffset[i], i + 1);\n" 1247-+ << " //printf(\"*************************\\n\");\n" 1248-+#else 1249- O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n" 1250- << " \"Invalid alt name index for register!\");\n" 1251-+#endif 1252- << " return AsmStrs+RegAsmOffset[RegNo-1];\n"; 1253- } 1254-+#ifdef CAPSTONE 1255-+ O << "#else\n" 1256-+ << " return NULL;\n" 1257-+ << "#endif\n"; 1258-+#endif 1259- O << "}\n"; 1260- } 1261- 1262-@@ -1135,9 +1201,20 @@ AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) { 1263- } 1264- 1265- void AsmWriterEmitter::run(raw_ostream &O) { 1266-+#ifdef CAPSTONE 1267-+ O << "/* Capstone Disassembly Engine */\n" 1268-+ "/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */\n" 1269-+ "\n" 1270-+ "#include <stdio.h>\t// debug\n" 1271-+ "#include <capstone/platform.h>\n" 1272-+ "\n" 1273-+ "\n"; 1274-+#endif 1275- EmitPrintInstruction(O); 1276- EmitGetRegisterName(O); 1277-+#ifndef CAPSTONE 1278- EmitPrintAliasInstruction(O); 1279-+#endif 1280- } 1281- 1282- namespace llvm { 1283-diff --git a/utils/TableGen/AsmWriterInst.cpp b/utils/TableGen/AsmWriterInst.cpp 1284-index 2c19e5d663d..6fa751e50df 100644 1285---- a/utils/TableGen/AsmWriterInst.cpp 1286-+++ b/utils/TableGen/AsmWriterInst.cpp 1287-@@ -28,9 +28,13 @@ static bool isIdentChar(char C) { 1288- 1289- std::string AsmWriterOperand::getCode(bool PassSubtarget) const { 1290- if (OperandType == isLiteralTextOperand) { 1291-+#ifdef CAPSTONE 1292-+ return "SStream_concat0(O, \"" + Str + "\");"; 1293-+#else 1294- if (Str.size() == 1) 1295- return "O << '" + Str + "';"; 1296- return "O << \"" + Str + "\";"; 1297-+#endif 1298- } 1299- 1300- if (OperandType == isLiteralStatementOperand) 1301--- 1302-2.19.1 1303- 1304diff --git a/llvm/0006-capstone-generate-MappingInsn.inc.patch b/llvm/0006-capstone-generate-MappingInsn.inc.patch 1305deleted file mode 100644 1306index 7ee22d787..000000000 1307--- a/llvm/0006-capstone-generate-MappingInsn.inc.patch 1308+++ /dev/null 1309@@ -1,174 +0,0 @@ 1310-From 7a436110ef15c803dc8524af2fb5612bcacbb126 Mon Sep 17 00:00:00 2001 1311-From: mephi42 <mephi42@gmail.com> 1312-Date: Tue, 7 Aug 2018 20:55:32 +0200 1313-Subject: [PATCH 6/7] capstone: generate *MappingInsn.inc 1314- 1315---- 1316- lib/Target/SystemZ/CMakeLists.txt | 1 + 1317- utils/TableGen/InstrInfoEmitter.cpp | 95 +++++++++++++++++++++++++++++ 1318- utils/TableGen/TableGen.cpp | 6 ++ 1319- utils/TableGen/TableGenBackends.h | 1 + 1320- 4 files changed, 103 insertions(+) 1321- 1322-diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt 1323-index f83b4242fb4..4b5d9c4a3b2 100644 1324---- a/lib/Target/SystemZ/CMakeLists.txt 1325-+++ b/lib/Target/SystemZ/CMakeLists.txt 1326-@@ -6,6 +6,7 @@ tablegen(LLVM SystemZGenCallingConv.inc -gen-callingconv) 1327- tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel) 1328- tablegen(LLVM SystemZGenDisassemblerTables.inc -gen-disassembler) 1329- tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info) 1330-+tablegen(LLVM SystemZMappingInsn.inc -mapping-insn) 1331- tablegen(LLVM SystemZGenMCCodeEmitter.inc -gen-emitter) 1332- tablegen(LLVM SystemZGenRegisterInfo.inc -gen-register-info) 1333- tablegen(LLVM SystemZGenSubtargetInfo.inc -gen-subtarget) 1334-diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp 1335-index 2f3a2729262..14ab1ea8a72 100644 1336---- a/utils/TableGen/InstrInfoEmitter.cpp 1337-+++ b/utils/TableGen/InstrInfoEmitter.cpp 1338-@@ -744,4 +744,99 @@ void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) { 1339- #endif 1340- } 1341- 1342-+#ifdef CAPSTONE 1343-+std::string GetPublicName(const CodeGenInstruction *Inst) { 1344-+ std::string Name = Inst->TheDef->getName(); 1345-+ // Apply backward compatibility fixups. 1346-+ // BRNLE -> BNLER. 1347-+ if (Name.length() >= 5 && Name.substr(0, 5) == "BRAsm") { 1348-+ Name = "B" + Name.substr(5, Name.length() - 5) + "R"; 1349-+ } 1350-+ // SSKEOpt -> SSKE. 1351-+ while (Name.length() >= 3 && Name.substr(Name.length() - 3, 3) == "Opt") { 1352-+ Name = Name.substr(0, Name.length() - 3); 1353-+ } 1354-+ // BRCLAsm -> BRCL. 1355-+ while (true) { 1356-+ size_t pos = Name.find("Asm"); 1357-+ if (pos == std::string::npos) { 1358-+ break; 1359-+ } 1360-+ Name = Name.substr(0, pos) + Name.substr(pos + 3); 1361-+ } 1362-+ // CPSDRxx -> CPSDR. 1363-+ if (Name.length() >= 2) { 1364-+ std::string Suffix2 = Name.substr(Name.length() - 2, 2); 1365-+ if (Suffix2 == "dd" || Suffix2 == "ds" || 1366-+ Suffix2 == "sd" || Suffix2 == "ss") { 1367-+ Name = Name.substr(0, Name.length() - 2); 1368-+ } 1369-+ } 1370-+ return "SYSZ_INS_" + Name; 1371-+} 1372-+ 1373-+std::string GetRegisterName(Record *Reg) { 1374-+ std::string Name = Reg->getName(); 1375-+ for (char& c : Name) { 1376-+ c = toupper(c); 1377-+ } 1378-+ // R0L, R0D -> R0. 1379-+ if (Name.length() >= 3 && 1380-+ Name[Name.length() - 3] == 'R' && 1381-+ (Name[Name.length() - 1] == 'L' || 1382-+ Name[Name.length() - 1] == 'D')) { 1383-+ Name = Name.substr(0, Name.length() - 3) + Name[Name.length() - 2]; 1384-+ } 1385-+ return "SYSZ_REG_" + Name; 1386-+} 1387-+ 1388-+std::string GetGroupName(Record *Pred) { 1389-+ std::string Name = Pred->getName(); 1390-+ for (char& c : Name) { 1391-+ c = toupper(c); 1392-+ } 1393-+ if (Name.length() >= 7 && Name.substr(0, 7) == "FEATURE") { 1394-+ Name = Name.substr(7); 1395-+ } 1396-+ return "SYSZ_GRP_" + Name; 1397-+} 1398-+ 1399-+void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS) { 1400-+ OS << "// This is auto-gen data for Capstone engine (www.capstone-engine.org)\n" 1401-+ "// By Nguyen Anh Quynh <aquynh@gmail.com>\n" 1402-+ "\n"; 1403-+ CodeGenTarget Target(RK); 1404-+ for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) { 1405-+ if (Inst->TheDef->getValueAsBit("isPseudo") || 1406-+ Inst->TheDef->getValueAsBit("isCodeGenOnly")) { 1407-+ continue; 1408-+ } 1409-+ OS << "{\n" 1410-+ << "\t" << Target.getName() << "_" << Inst->TheDef->getName() << ", " 1411-+ << GetPublicName(Inst) << ",\n" 1412-+ << "#ifndef CAPSTONE_DIET\n" 1413-+ << "\t{ "; 1414-+ for (Record *Use : Inst->TheDef->getValueAsListOfDefs("Uses")) { 1415-+ OS << GetRegisterName(Use) << ", "; 1416-+ } 1417-+ OS << "0 }, { "; 1418-+ for (Record *Def : Inst->TheDef->getValueAsListOfDefs("Defs")) { 1419-+ OS << GetRegisterName(Def) << ", "; 1420-+ } 1421-+ OS << "0 }, { "; 1422-+ ListInit *Predicates = Inst->TheDef->getValueAsListInit("Predicates"); 1423-+ for (unsigned i = 0; i < Predicates->size(); ++i) { 1424-+ OS << GetGroupName(Predicates->getElementAsRecord(i)) << ", "; 1425-+ } 1426-+ OS << "0 }, " 1427-+ << Inst->TheDef->getValueAsBit("isBranch") 1428-+ << ", " 1429-+ << Inst->TheDef->getValueAsBit("isIndirectBranch") 1430-+ << "\n" 1431-+ << "#endif\n" 1432-+ << "},\n"; 1433-+ } 1434-+} 1435-+#endif 1436-+ 1437- } // end llvm namespace 1438-diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp 1439-index cf1404d8769..bbb4e860536 100644 1440---- a/utils/TableGen/TableGen.cpp 1441-+++ b/utils/TableGen/TableGen.cpp 1442-@@ -27,6 +27,7 @@ enum ActionType { 1443- GenEmitter, 1444- GenRegisterInfo, 1445- GenInstrInfo, 1446-+ MappingInsn, 1447- GenInstrDocs, 1448- GenAsmWriter, 1449- GenAsmMatcher, 1450-@@ -65,6 +66,8 @@ namespace { 1451- "Generate registers and register classes info"), 1452- clEnumValN(GenInstrInfo, "gen-instr-info", 1453- "Generate instruction descriptions"), 1454-+ clEnumValN(MappingInsn, "mapping-insn", 1455-+ ""), 1456- clEnumValN(GenInstrDocs, "gen-instr-docs", 1457- "Generate instruction documentation"), 1458- clEnumValN(GenCallingConv, "gen-callingconv", 1459-@@ -135,6 +138,9 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { 1460- case GenInstrInfo: 1461- EmitInstrInfo(Records, OS); 1462- break; 1463-+ case MappingInsn: 1464-+ EmitMappingInsn(Records, OS); 1465-+ break; 1466- case GenInstrDocs: 1467- EmitInstrDocs(Records, OS); 1468- break; 1469-diff --git a/utils/TableGen/TableGenBackends.h b/utils/TableGen/TableGenBackends.h 1470-index 1329a6d833f..a41e46b1db0 100644 1471---- a/utils/TableGen/TableGenBackends.h 1472-+++ b/utils/TableGen/TableGenBackends.h 1473-@@ -75,6 +75,7 @@ void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS); 1474- void EmitDisassembler(RecordKeeper &RK, raw_ostream &OS); 1475- void EmitFastISel(RecordKeeper &RK, raw_ostream &OS); 1476- void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS); 1477-+void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS); 1478- void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS); 1479- void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS); 1480- void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS); 1481--- 1482-2.19.1 1483- 1484diff --git a/llvm/0007-capstone-generate-GenInsnNameMaps.inc.patch b/llvm/0007-capstone-generate-GenInsnNameMaps.inc.patch 1485deleted file mode 100644 1486index 019540d65..000000000 1487--- a/llvm/0007-capstone-generate-GenInsnNameMaps.inc.patch 1488+++ /dev/null 1489@@ -1,110 +0,0 @@ 1490-From b42f9f2014ec49a22077b6610863d9341a74e142 Mon Sep 17 00:00:00 2001 1491-From: mephi42 <mephi42@gmail.com> 1492-Date: Fri, 17 Aug 2018 11:07:39 +0200 1493-Subject: [PATCH 7/7] capstone: generate *GenInsnNameMaps.inc 1494- 1495---- 1496- lib/Target/SystemZ/CMakeLists.txt | 1 + 1497- utils/TableGen/InstrInfoEmitter.cpp | 29 +++++++++++++++++++++++++++++ 1498- utils/TableGen/TableGen.cpp | 6 ++++++ 1499- utils/TableGen/TableGenBackends.h | 1 + 1500- 4 files changed, 37 insertions(+) 1501- 1502-diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt 1503-index 4b5d9c4a3b2..2c64e0a94b8 100644 1504---- a/lib/Target/SystemZ/CMakeLists.txt 1505-+++ b/lib/Target/SystemZ/CMakeLists.txt 1506-@@ -7,6 +7,7 @@ tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel) 1507- tablegen(LLVM SystemZGenDisassemblerTables.inc -gen-disassembler) 1508- tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info) 1509- tablegen(LLVM SystemZMappingInsn.inc -mapping-insn) 1510-+tablegen(LLVM SystemZGenInsnNameMaps.inc -gen-insn-name-maps) 1511- tablegen(LLVM SystemZGenMCCodeEmitter.inc -gen-emitter) 1512- tablegen(LLVM SystemZGenRegisterInfo.inc -gen-register-info) 1513- tablegen(LLVM SystemZGenSubtargetInfo.inc -gen-subtarget) 1514-diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp 1515-index 14ab1ea8a72..ccf8170ca62 100644 1516---- a/utils/TableGen/InstrInfoEmitter.cpp 1517-+++ b/utils/TableGen/InstrInfoEmitter.cpp 1518-@@ -837,6 +837,35 @@ void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS) { 1519- << "},\n"; 1520- } 1521- } 1522-+ 1523-+std::string GetMnemonic(const CodeGenInstruction *Inst) { 1524-+ std::string Mnemonic = Inst->AsmString; 1525-+ 1526-+ for (size_t i = 0; i < Mnemonic.length(); i++) { 1527-+ if (Mnemonic[i] == '\t') { 1528-+ return Mnemonic.substr(0, i); 1529-+ } 1530-+ } 1531-+ return Mnemonic; 1532-+} 1533-+ 1534-+void EmitInsnNameMaps(RecordKeeper &RK, raw_ostream &OS) { 1535-+ OS << "// This is auto-gen data for Capstone engine (www.capstone-engine.org)\n" 1536-+ "// By Nguyen Anh Quynh <aquynh@gmail.com>\n" 1537-+ "\n"; 1538-+ CodeGenTarget Target(RK); 1539-+ std::map<std::string, std::string> M; 1540-+ for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) { 1541-+ if (Inst->TheDef->getValueAsBit("isPseudo") || 1542-+ Inst->TheDef->getValueAsBit("isCodeGenOnly")) { 1543-+ continue; 1544-+ } 1545-+ M[GetPublicName(Inst)] = GetMnemonic(Inst); 1546-+ } 1547-+ for (auto &P : M) { 1548-+ OS << "\t{ " << P.first << ", \"" << P.second << "\" },\n"; 1549-+ } 1550-+} 1551- #endif 1552- 1553- } // end llvm namespace 1554-diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp 1555-index bbb4e860536..27c6603de5a 100644 1556---- a/utils/TableGen/TableGen.cpp 1557-+++ b/utils/TableGen/TableGen.cpp 1558-@@ -28,6 +28,7 @@ enum ActionType { 1559- GenRegisterInfo, 1560- GenInstrInfo, 1561- MappingInsn, 1562-+ GenInsnNameMaps, 1563- GenInstrDocs, 1564- GenAsmWriter, 1565- GenAsmMatcher, 1566-@@ -68,6 +69,8 @@ namespace { 1567- "Generate instruction descriptions"), 1568- clEnumValN(MappingInsn, "mapping-insn", 1569- ""), 1570-+ clEnumValN(GenInsnNameMaps, "gen-insn-name-maps", 1571-+ ""), 1572- clEnumValN(GenInstrDocs, "gen-instr-docs", 1573- "Generate instruction documentation"), 1574- clEnumValN(GenCallingConv, "gen-callingconv", 1575-@@ -141,6 +144,9 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { 1576- case MappingInsn: 1577- EmitMappingInsn(Records, OS); 1578- break; 1579-+ case GenInsnNameMaps: 1580-+ EmitInsnNameMaps(Records, OS); 1581-+ break; 1582- case GenInstrDocs: 1583- EmitInstrDocs(Records, OS); 1584- break; 1585-diff --git a/utils/TableGen/TableGenBackends.h b/utils/TableGen/TableGenBackends.h 1586-index a41e46b1db0..5656e5be849 100644 1587---- a/utils/TableGen/TableGenBackends.h 1588-+++ b/utils/TableGen/TableGenBackends.h 1589-@@ -76,6 +76,7 @@ void EmitDisassembler(RecordKeeper &RK, raw_ostream &OS); 1590- void EmitFastISel(RecordKeeper &RK, raw_ostream &OS); 1591- void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS); 1592- void EmitMappingInsn(RecordKeeper &RK, raw_ostream &OS); 1593-+void EmitInsnNameMaps(RecordKeeper &RK, raw_ostream &OS); 1594- void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS); 1595- void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS); 1596- void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS); 1597--- 1598-2.19.1 1599- 1600-- 16012.20.1 1602 1603