1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is the top level entry point for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing.
15//
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// PowerPC Subtarget features.
20//
21
22//===----------------------------------------------------------------------===//
23// CPU Directives                                                             //
24//===----------------------------------------------------------------------===//
25
26def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38def DirectiveE500   : SubtargetFeature<"", "DarwinDirective",
39                                       "PPC::DIR_E500", "">;
40def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
41                                       "PPC::DIR_E500mc", "">;
42def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective",
43                                       "PPC::DIR_E5500", "">;
44def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
45def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
46def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
47def DirectivePwr5x
48    : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
49def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
50def DirectivePwr6x
51    : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
52def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
53def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
54def DirectivePwr9: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR9", "">;
55
56def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
57                                        "Enable 64-bit instructions">;
58def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
59                              "Enable floating-point instructions">;
60def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
61                              "Enable 64-bit registers usage for ppc32 [beta]">;
62def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
63                              "Use condition-register bits individually">;
64def FeatureFPU       : SubtargetFeature<"fpu","HasFPU","true",
65                                        "Enable classic FPU instructions",
66                                        [FeatureHardFloat]>;
67def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
68                                        "Enable Altivec instructions",
69                                        [FeatureFPU]>;
70def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
71                                        "Enable SPE instructions",
72                                        [FeatureHardFloat]>;
73def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
74                                        "Enable the MFOCRF instruction">;
75def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
76                                        "Enable the fsqrt instruction",
77                                        [FeatureFPU]>;
78def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
79                                        "Enable the fcpsgn instruction",
80                                        [FeatureFPU]>;
81def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
82                                        "Enable the fre instruction",
83                                        [FeatureFPU]>;
84def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
85                                        "Enable the fres instruction",
86                                        [FeatureFPU]>;
87def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
88                                        "Enable the frsqrte instruction",
89                                        [FeatureFPU]>;
90def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
91                                        "Enable the frsqrtes instruction",
92                                        [FeatureFPU]>;
93def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
94                              "Assume higher precision reciprocal estimates">;
95def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
96                                        "Enable the stfiwx instruction",
97                                        [FeatureFPU]>;
98def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
99                                        "Enable the lfiwax instruction",
100                                        [FeatureFPU]>;
101def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
102                                        "Enable the fri[mnpz] instructions",
103                                        [FeatureFPU]>;
104def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
105  "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
106                                        [FeatureFPU]>;
107def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
108                                        "Enable the isel instruction">;
109def FeatureBPERMD    : SubtargetFeature<"bpermd", "HasBPERMD", "true",
110                                        "Enable the bpermd instruction">;
111def FeatureExtDiv    : SubtargetFeature<"extdiv", "HasExtDiv", "true",
112                                        "Enable extended divide instructions">;
113def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
114                                        "Enable the ldbrx instruction">;
115def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
116                                        "Enable the cmpb instruction">;
117def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
118                                        "Enable icbt instruction">;
119def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
120                                        "Enable Book E instructions",
121                                        [FeatureICBT]>;
122def FeatureMSYNC     : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
123                              "Has only the msync instruction instead of sync",
124                              [FeatureBookE]>;
125def FeatureE500      : SubtargetFeature<"e500", "IsE500", "true",
126                                        "Enable E500/E500mc instructions">;
127def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true",
128                                        "Enable secure plt mode">;
129def FeaturePPC4xx    : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
130                                        "Enable PPC 4xx instructions">;
131def FeaturePPC6xx    : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
132                                        "Enable PPC 6xx instructions">;
133def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
134                                        "Enable QPX instructions",
135                                        [FeatureFPU]>;
136def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
137                                        "Enable VSX instructions",
138                                        [FeatureAltivec]>;
139def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
140                                        "Enable POWER8 Altivec instructions",
141                                        [FeatureAltivec]>;
142def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
143                                       "Enable POWER8 Crypto instructions",
144                                       [FeatureP8Altivec]>;
145def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
146                                        "Enable POWER8 vector instructions",
147                                        [FeatureVSX, FeatureP8Altivec]>;
148def FeatureDirectMove :
149  SubtargetFeature<"direct-move", "HasDirectMove", "true",
150                   "Enable Power8 direct move instructions",
151                   [FeatureVSX]>;
152def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
153                                             "HasPartwordAtomics", "true",
154                                             "Enable l[bh]arx and st[bh]cx.">;
155def FeatureInvariantFunctionDescriptors :
156  SubtargetFeature<"invariant-function-descriptors",
157                   "HasInvariantFunctionDescriptors", "true",
158                   "Assume function descriptors are invariant">;
159def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
160                                       "Always use indirect calls">;
161def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
162                                  "Enable Hardware Transactional Memory instructions">;
163def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
164                                        "Implement mftb using the mfspr instruction">;
165def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
166                                     "Target supports add/load integer fusion.">;
167def FeatureFloat128 :
168  SubtargetFeature<"float128", "HasFloat128", "true",
169                   "Enable the __float128 data type for IEEE-754R Binary128.",
170                   [FeatureVSX]>;
171def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
172                                        "POPCNTD_Fast",
173                                        "Enable the popcnt[dw] instructions">;
174// Note that for the a2/a2q processor models we should not use popcnt[dw] by
175// default. These processors do support the instructions, but they're
176// microcoded, and the software emulation is about twice as fast.
177def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
178                                          "POPCNTD_Slow",
179                                          "Has slow popcnt[dw] instructions">;
180
181def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
182  "Treat vector data stream cache control instructions as deprecated">;
183
184def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
185                                     "true",
186                                     "Enable instructions added in ISA 3.0.">;
187def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
188                                        "Enable POWER9 Altivec instructions",
189                                        [FeatureISA3_0, FeatureP8Altivec]>;
190def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
191                                        "Enable POWER9 vector instructions",
192                                        [FeatureISA3_0, FeatureP8Vector,
193                                         FeatureP9Altivec]>;
194
195// Since new processors generally contain a superset of features of those that
196// came before them, the idea is to make implementations of new processors
197// less error prone and easier to read.
198// Namely:
199//     list<SubtargetFeature> Power8FeatureList = ...
200//     list<SubtargetFeature> FutureProcessorSpecificFeatureList =
201//         [ features that Power8 does not support ]
202//     list<SubtargetFeature> FutureProcessorFeatureList =
203//         !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList)
204
205// Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
206// well as providing a single point of definition if the feature set will be
207// used elsewhere.
208def ProcessorFeatures {
209  list<SubtargetFeature> Power7FeatureList =
210      [DirectivePwr7, FeatureAltivec, FeatureVSX,
211       FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
212       FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
213       FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
214       FeatureFPRND, FeatureFPCVT, FeatureISEL,
215       FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
216       Feature64Bit /*, Feature64BitRegs */,
217       FeatureBPERMD, FeatureExtDiv,
218       FeatureMFTB, DeprecatedDST];
219  list<SubtargetFeature> Power8SpecificFeatures =
220      [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
221       FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic,
222       FeatureFusion];
223  list<SubtargetFeature> Power8FeatureList =
224      !listconcat(Power7FeatureList, Power8SpecificFeatures);
225  list<SubtargetFeature> Power9SpecificFeatures =
226      [DirectivePwr9, FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0];
227  list<SubtargetFeature> Power9FeatureList =
228      !listconcat(Power8FeatureList, Power9SpecificFeatures);
229}
230
231// Note: Future features to add when support is extended to more
232// recent ISA levels:
233//
234// DFP          p6, p6x, p7        decimal floating-point instructions
235// POPCNTB      p5 through p7      popcntb and related instructions
236
237//===----------------------------------------------------------------------===//
238// Classes used for relation maps.
239//===----------------------------------------------------------------------===//
240// RecFormRel - Filter class used to relate non-record-form instructions with
241// their record-form variants.
242class RecFormRel;
243
244// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
245// FMA instruction forms with their corresponding factor-killing forms.
246class AltVSXFMARel {
247  bit IsVSXFMAAlt = 0;
248}
249
250//===----------------------------------------------------------------------===//
251// Relation Map Definitions.
252//===----------------------------------------------------------------------===//
253
254def getRecordFormOpcode : InstrMapping {
255  let FilterClass = "RecFormRel";
256  // Instructions with the same BaseName and Interpretation64Bit values
257  // form a row.
258  let RowFields = ["BaseName", "Interpretation64Bit"];
259  // Instructions with the same RC value form a column.
260  let ColFields = ["RC"];
261  // The key column are the non-record-form instructions.
262  let KeyCol = ["0"];
263  // Value columns RC=1
264  let ValueCols = [["1"]];
265}
266
267def getNonRecordFormOpcode : InstrMapping {
268  let FilterClass = "RecFormRel";
269  // Instructions with the same BaseName and Interpretation64Bit values
270  // form a row.
271  let RowFields = ["BaseName", "Interpretation64Bit"];
272  // Instructions with the same RC value form a column.
273  let ColFields = ["RC"];
274  // The key column are the record-form instructions.
275  let KeyCol = ["1"];
276  // Value columns are RC=0
277  let ValueCols = [["0"]];
278}
279
280def getAltVSXFMAOpcode : InstrMapping {
281  let FilterClass = "AltVSXFMARel";
282  // Instructions with the same BaseName and Interpretation64Bit values
283  // form a row.
284  let RowFields = ["BaseName"];
285  // Instructions with the same RC value form a column.
286  let ColFields = ["IsVSXFMAAlt"];
287  // The key column are the (default) addend-killing instructions.
288  let KeyCol = ["0"];
289  // Value columns IsVSXFMAAlt=1
290  let ValueCols = [["1"]];
291}
292
293//===----------------------------------------------------------------------===//
294// Register File Description
295//===----------------------------------------------------------------------===//
296
297include "PPCRegisterInfo.td"
298include "PPCSchedule.td"
299
300//===----------------------------------------------------------------------===//
301// PowerPC processors supported.
302//
303
304def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
305                                           FeatureMFTB]>;
306def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
307                                          FeatureFRES, FeatureFRSQRTE,
308                                          FeatureICBT, FeatureBookE,
309                                          FeatureMSYNC, FeatureMFTB]>;
310def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
311                                          FeatureFRES, FeatureFRSQRTE,
312                                          FeatureICBT, FeatureBookE,
313                                          FeatureMSYNC, FeatureMFTB]>;
314def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
315def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
316                                       FeatureMFTB]>;
317def : Processor<"603", G3Itineraries, [Directive603,
318                                       FeatureFRES, FeatureFRSQRTE,
319                                       FeatureMFTB]>;
320def : Processor<"603e", G3Itineraries, [Directive603,
321                                        FeatureFRES, FeatureFRSQRTE,
322                                        FeatureMFTB]>;
323def : Processor<"603ev", G3Itineraries, [Directive603,
324                                         FeatureFRES, FeatureFRSQRTE,
325                                         FeatureMFTB]>;
326def : Processor<"604", G3Itineraries, [Directive604,
327                                       FeatureFRES, FeatureFRSQRTE,
328                                       FeatureMFTB]>;
329def : Processor<"604e", G3Itineraries, [Directive604,
330                                        FeatureFRES, FeatureFRSQRTE,
331                                        FeatureMFTB]>;
332def : Processor<"620", G3Itineraries, [Directive620,
333                                       FeatureFRES, FeatureFRSQRTE,
334                                       FeatureMFTB]>;
335def : Processor<"750", G4Itineraries, [Directive750,
336                                       FeatureFRES, FeatureFRSQRTE,
337                                       FeatureMFTB]>;
338def : Processor<"g3", G3Itineraries, [Directive750,
339                                      FeatureFRES, FeatureFRSQRTE,
340                                      FeatureMFTB]>;
341def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
342                                        FeatureFRES, FeatureFRSQRTE,
343                                        FeatureMFTB]>;
344def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
345                                      FeatureFRES, FeatureFRSQRTE,
346                                      FeatureMFTB]>;
347def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
348                                            FeatureFRES, FeatureFRSQRTE,
349                                            FeatureMFTB]>;
350def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
351                                           FeatureFRES, FeatureFRSQRTE,
352                                           FeatureMFTB]>;
353
354def : ProcessorModel<"970", G5Model,
355                  [Directive970, FeatureAltivec,
356                   FeatureMFOCRF, FeatureFSqrt,
357                   FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
358                   Feature64Bit /*, Feature64BitRegs */,
359                   FeatureMFTB]>;
360def : ProcessorModel<"g5", G5Model,
361                  [Directive970, FeatureAltivec,
362                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
363                   FeatureFRES, FeatureFRSQRTE,
364                   Feature64Bit /*, Feature64BitRegs */,
365                   FeatureMFTB, DeprecatedDST]>;
366def : ProcessorModel<"e500", PPCE500Model,
367                  [DirectiveE500,
368                   FeatureICBT, FeatureBookE,
369                   FeatureISEL, FeatureMFTB]>;
370def : ProcessorModel<"e500mc", PPCE500mcModel,
371                  [DirectiveE500mc,
372                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
373                   FeatureISEL, FeatureMFTB]>;
374def : ProcessorModel<"e5500", PPCE5500Model,
375                  [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
376                   FeatureSTFIWX, FeatureICBT, FeatureBookE,
377                   FeatureISEL, FeatureMFTB]>;
378def : ProcessorModel<"a2", PPCA2Model,
379                  [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
380                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
381                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
382                   FeatureSTFIWX, FeatureLFIWAX,
383                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
384                   FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
385                   Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
386def : ProcessorModel<"a2q", PPCA2Model,
387                  [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
388                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
389                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
390                   FeatureSTFIWX, FeatureLFIWAX,
391                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
392                   FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
393                   Feature64Bit /*, Feature64BitRegs */, FeatureQPX,
394                   FeatureMFTB]>;
395def : ProcessorModel<"pwr3", G5Model,
396                  [DirectivePwr3, FeatureAltivec,
397                   FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
398                   FeatureSTFIWX, Feature64Bit]>;
399def : ProcessorModel<"pwr4", G5Model,
400                  [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
401                   FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
402                   FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
403def : ProcessorModel<"pwr5", G5Model,
404                  [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
405                   FeatureFSqrt, FeatureFRE, FeatureFRES,
406                   FeatureFRSQRTE, FeatureFRSQRTES,
407                   FeatureSTFIWX, Feature64Bit,
408                   FeatureMFTB, DeprecatedDST]>;
409def : ProcessorModel<"pwr5x", G5Model,
410                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
411                   FeatureFSqrt, FeatureFRE, FeatureFRES,
412                   FeatureFRSQRTE, FeatureFRSQRTES,
413                   FeatureSTFIWX, FeatureFPRND, Feature64Bit,
414                   FeatureMFTB, DeprecatedDST]>;
415def : ProcessorModel<"pwr6", G5Model,
416                  [DirectivePwr6, FeatureAltivec,
417                   FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
418                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
419                   FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
420                   FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
421                   FeatureMFTB, DeprecatedDST]>;
422def : ProcessorModel<"pwr6x", G5Model,
423                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
424                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
425                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
426                   FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
427                   FeatureFPRND, Feature64Bit,
428                   FeatureMFTB, DeprecatedDST]>;
429def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
430def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
431def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>;
432def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
433                                       FeatureMFTB]>;
434def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
435                                         FeatureMFTB]>;
436def : ProcessorModel<"ppc64", G5Model,
437                  [Directive64, FeatureAltivec,
438                   FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
439                   FeatureFRSQRTE, FeatureSTFIWX,
440                   Feature64Bit /*, Feature64BitRegs */,
441                   FeatureMFTB]>;
442def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
443
444//===----------------------------------------------------------------------===//
445// Calling Conventions
446//===----------------------------------------------------------------------===//
447
448include "PPCCallingConv.td"
449
450def PPCInstrInfo : InstrInfo {
451  let isLittleEndianEncoding = 1;
452
453  // FIXME: Unset this when no longer needed!
454  let decodePositionallyEncodedOperands = 1;
455
456  let noNamedPositionallyEncodedOperands = 1;
457}
458
459def PPCAsmParser : AsmParser {
460  let ShouldEmitMatchRegisterName = 0;
461}
462
463def PPCAsmParserVariant : AsmParserVariant {
464  int Variant = 0;
465
466  // We do not use hard coded registers in asm strings.  However, some
467  // InstAlias definitions use immediate literals.  Set RegisterPrefix
468  // so that those are not misinterpreted as registers.
469  string RegisterPrefix = "%";
470  string BreakCharacters = ".";
471}
472
473def PPC : Target {
474  // Information about the instructions.
475  let InstructionSet = PPCInstrInfo;
476
477  let AssemblyParsers = [PPCAsmParser];
478  let AssemblyParserVariants = [PPCAsmParserVariant];
479  let AllowRegisterRenaming = 1;
480}
481