1 /* Capstone Disassembler Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
3
4 #include <stdio.h>
5 #include <stdlib.h>
6
7 #include <capstone/platform.h>
8 #include <capstone/capstone.h>
9
10 struct platform {
11 cs_arch arch;
12 cs_mode mode;
13 unsigned char *code;
14 size_t size;
15 const char *comment;
print_string_hex(unsigned char * str,size_t len)16 cs_opt_type opt_type;
17 cs_opt_value opt_value;
18 };
19
20 static void print_string_hex(unsigned char *str, size_t len)
21 {
22 unsigned char *c;
23
24 printf("Code: ");
25 for (c = str; c < str + len; c++) {
26 printf("0x%02x ", *c & 0xff);
print_insn(csh handle)27 }
28 printf("\n");
29 }
30
31 static void test()
32 {
33 #ifdef CAPSTONE_HAS_X86
34 #define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
35 #define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
36 #define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
37 #endif
38 #ifdef CAPSTONE_HAS_ARM
39 #define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
40 #define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
41 #define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
42 #define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
43 #define THUMB_MCLASS "\xef\xf3\x02\x80"
test()44 #define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
45 #endif
46 #ifdef CAPSTONE_HAS_MIPS
47 #define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08"
48 #define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
49 #define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
50 #define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0"
51 #endif
52 #ifdef CAPSTONE_HAS_ARM64
53 #define ARM64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
54 #endif
55 #ifdef CAPSTONE_HAS_POWERPC
56 #define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
57 #define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
58 #endif
59 #ifdef CAPSTONE_HAS_SPARC
60 #define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
61 #define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
62 #endif
63 #ifdef CAPSTONE_HAS_SYSZ
64 #define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
65 #endif
66 #ifdef CAPSTONE_HAS_XCORE
67 #define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
68 #endif
69 #ifdef CAPSTONE_HAS_M68K
70 #define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28"
71 #endif
72 #ifdef CAPSTONE_HAS_M680X
73 #define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
74 #endif
75 #ifdef CAPSTONE_HAS_MOS65XX
76 #define MOS65XX_CODE "\x0A\x00\xFE\x34\x12\xD0\xFF\xEA\x19\x56\x34\x46\x80"
77 #endif
78 #define EBPF_CODE "\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00"
79
80 struct platform platforms[] = {
81 #ifdef CAPSTONE_HAS_X86
82 {
83 CS_ARCH_X86,
84 CS_MODE_16,
85 (unsigned char *)X86_CODE16,
86 sizeof(X86_CODE16) - 1,
87 "X86 16bit (Intel syntax)"
88 },
89 {
90 CS_ARCH_X86,
91 CS_MODE_32,
92 (unsigned char *)X86_CODE32,
93 sizeof(X86_CODE32) - 1,
94 "X86 32bit (ATT syntax)",
95 CS_OPT_SYNTAX,
96 CS_OPT_SYNTAX_ATT,
97 },
98 {
99 CS_ARCH_X86,
100 CS_MODE_32,
101 (unsigned char *)X86_CODE32,
102 sizeof(X86_CODE32) - 1,
103 "X86 32 (Intel syntax)"
104 },
105 {
106 CS_ARCH_X86,
107 CS_MODE_64,
108 (unsigned char *)X86_CODE64,
109 sizeof(X86_CODE64) - 1,
110 "X86 64 (Intel syntax)"
111 },
112 #endif
113 #ifdef CAPSTONE_HAS_ARM
114 {
115 CS_ARCH_ARM,
116 CS_MODE_ARM,
117 (unsigned char *)ARM_CODE,
118 sizeof(ARM_CODE) - 1,
119 "ARM"
120 },
121 {
122 CS_ARCH_ARM,
123 CS_MODE_THUMB,
124 (unsigned char *)THUMB_CODE2,
125 sizeof(THUMB_CODE2) - 1,
126 "THUMB-2"
127 },
128 {
129 CS_ARCH_ARM,
130 CS_MODE_ARM,
131 (unsigned char *)ARM_CODE2,
132 sizeof(ARM_CODE2) - 1,
133 "ARM: Cortex-A15 + NEON"
134 },
135 {
136 CS_ARCH_ARM,
137 CS_MODE_THUMB,
138 (unsigned char *)THUMB_CODE,
139 sizeof(THUMB_CODE) - 1,
140 "THUMB"
141 },
142 {
143 CS_ARCH_ARM,
144 (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS),
145 (unsigned char*)THUMB_MCLASS,
146 sizeof(THUMB_MCLASS) - 1,
147 "Thumb-MClass"
148 },
149 {
150 CS_ARCH_ARM,
151 (cs_mode)(CS_MODE_ARM + CS_MODE_V8),
152 (unsigned char*)ARMV8,
153 sizeof(ARMV8) - 1,
154 "Arm-V8"
155 },
156 #endif
157 #ifdef CAPSTONE_HAS_MIPS
158 {
159 CS_ARCH_MIPS,
160 (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
161 (unsigned char *)MIPS_CODE,
162 sizeof(MIPS_CODE) - 1,
163 "MIPS-32 (Big-endian)"
164 },
165 {
166 CS_ARCH_MIPS,
167 (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
168 (unsigned char *)MIPS_CODE2,
169 sizeof(MIPS_CODE2) - 1,
170 "MIPS-64-EL (Little-endian)"
171 },
172 {
173 CS_ARCH_MIPS,
174 (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
175 (unsigned char*)MIPS_32R6M,
176 sizeof(MIPS_32R6M) - 1,
177 "MIPS-32R6 | Micro (Big-endian)"
178 },
179 {
180 CS_ARCH_MIPS,
181 (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
182 (unsigned char*)MIPS_32R6,
183 sizeof(MIPS_32R6) - 1,
184 "MIPS-32R6 (Big-endian)"
185 },
186 #endif
187 #ifdef CAPSTONE_HAS_ARM64
188 {
189 CS_ARCH_ARM64,
190 CS_MODE_ARM,
191 (unsigned char *)ARM64_CODE,
192 sizeof(ARM64_CODE) - 1,
193 "ARM-64"
194 },
195 #endif
196 #ifdef CAPSTONE_HAS_POWERPC
197 {
198 CS_ARCH_PPC,
199 CS_MODE_BIG_ENDIAN,
200 (unsigned char*)PPC_CODE,
201 sizeof(PPC_CODE) - 1,
202 "PPC-64"
203 },
204 {
205 CS_ARCH_PPC,
206 CS_MODE_BIG_ENDIAN + CS_MODE_QPX,
207 (unsigned char*)PPC_CODE2,
208 sizeof(PPC_CODE2) - 1,
209 "PPC-64 + QPX",
210 },
211 #endif
212 #ifdef CAPSTONE_HAS_SPARC
213 {
214 CS_ARCH_SPARC,
215 CS_MODE_BIG_ENDIAN,
216 (unsigned char*)SPARC_CODE,
217 sizeof(SPARC_CODE) - 1,
218 "Sparc"
219 },
220 {
221 CS_ARCH_SPARC,
222 (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
223 (unsigned char*)SPARCV9_CODE,
224 sizeof(SPARCV9_CODE) - 1,
225 "SparcV9"
226 },
227 #endif
228 #ifdef CAPSTONE_HAS_SYSZ
229 {
230 CS_ARCH_SYSZ,
231 (cs_mode)0,
232 (unsigned char*)SYSZ_CODE,
233 sizeof(SYSZ_CODE) - 1,
234 "SystemZ"
235 },
236 #endif
237 #ifdef CAPSTONE_HAS_XCORE
238 {
239 CS_ARCH_XCORE,
240 (cs_mode)0,
241 (unsigned char*)XCORE_CODE,
242 sizeof(XCORE_CODE) - 1,
243 "XCore"
244 },
245 #endif
246 #ifdef CAPSTONE_HAS_M68K
247 {
248 CS_ARCH_M68K,
249 (cs_mode)(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040),
250 (unsigned char*)M68K_CODE,
251 sizeof(M68K_CODE) - 1,
252 "M68K",
253 },
254 #endif
255 #ifdef CAPSTONE_HAS_M680X
256 {
257 CS_ARCH_M680X,
258 (cs_mode)(CS_MODE_M680X_6809),
259 (unsigned char*)M680X_CODE,
260 sizeof(M680X_CODE) - 1,
261 "M680X_M6809",
262 },
263 #endif
264 #ifdef CAPSTONE_HAS_MOS65XX
265 {
266 CS_ARCH_MOS65XX,
267 (cs_mode)0,
268 (unsigned char*)MOS65XX_CODE,
269 sizeof(MOS65XX_CODE) - 1,
270 "MOS65XX",
271 },
272 #endif
273 #ifdef CAPSTONE_HAS_BPF
274 {
275 CS_ARCH_BPF,
276 CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED,
277 (unsigned char*) EBPF_CODE,
278 sizeof(EBPF_CODE) - 1,
279 "eBPF"
280 },
281 #endif
282 };
283
284 csh handle;
285 uint64_t address = 0x1000;
286 cs_insn *all_insn;
287 cs_detail *detail;
288 int i;
289 size_t count;
290 cs_err err;
291
292 for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
293 printf("****************\n");
294 printf("Platform: %s\n", platforms[i].comment);
295 err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
296 if (err) {
297 printf("Failed on cs_open() with error returned: %u\n", err);
298 abort();
299 }
300
301 if (platforms[i].opt_type)
302 cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
303
304 cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
305
306 count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &all_insn);
307 if (count) {
308 size_t j;
309 int n;
310
311 print_string_hex(platforms[i].code, platforms[i].size);
312 printf("Disasm:\n");
313
314 for (j = 0; j < count; j++) {
315 cs_insn *in = &(all_insn[j]);
316 printf("0x%" PRIx64 ":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n",
317 in->address, in->mnemonic, in->op_str,
318 in->id, cs_insn_name(handle, in->id));
319
320 // print implicit registers used by this instruction
321 detail = in->detail;
322
323 if (detail->regs_read_count > 0) {
324 printf("\tImplicit registers read: ");
325 for (n = 0; n < detail->regs_read_count; n++) {
326 printf("%s ", cs_reg_name(handle, detail->regs_read[n]));
327 }
328 printf("\n");
329 }
330
331 // print implicit registers modified by this instruction
332 if (detail->regs_write_count > 0) {
333 printf("\tImplicit registers modified: ");
334 for (n = 0; n < detail->regs_write_count; n++) {
335 printf("%s ", cs_reg_name(handle, detail->regs_write[n]));
336 }
337 printf("\n");
338 }
339
340 // print the groups this instruction belong to
341 if (detail->groups_count > 0) {
342 printf("\tThis instruction belongs to groups: ");
343 for (n = 0; n < detail->groups_count; n++) {
344 printf("%s ", cs_group_name(handle, detail->groups[n]));
345 }
346 printf("\n");
347 }
348 }
349
350 // print out the next offset, after the last insn
351 printf("0x%" PRIx64 ":\n", all_insn[j-1].address + all_insn[j-1].size);
352
353 // free memory allocated by cs_disasm()
354 cs_free(all_insn, count);
355 } else {
356 printf("****************\n");
357 printf("Platform: %s\n", platforms[i].comment);
358 print_string_hex(platforms[i].code, platforms[i].size);
359 printf("ERROR: Failed to disasm given code!\n");
360 abort();
361 }
362
363 printf("\n");
364
365 cs_close(&handle);
366 }
367 }
368
369 int main()
370 {
371 test();
372
373 return 0;
374 }
375