1 /** @file 2 3 This file contains the register definition of XHCI host controller. 4 5 Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR> 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef _EFI_XHCI_REG_H_ 11 #define _EFI_XHCI_REG_H_ 12 13 #define PCI_IF_XHCI 0x30 14 15 // 16 // PCI Configuration Registers 17 // 18 #define XHC_BAR_INDEX 0x00 19 20 #define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset 21 #define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask 22 23 #define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset 24 25 #define USB_HUB_CLASS_CODE 0x09 26 #define USB_HUB_SUBCLASS_CODE 0x00 27 28 #define XHC_CAP_USB_LEGACY 0x01 29 #define XHC_CAP_USB_DEBUG 0x0A 30 31 //============================================// 32 // XHCI register offset // 33 //============================================// 34 35 // 36 // Capability registers offset 37 // 38 #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset 39 #define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h 40 #define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1 41 #define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2 42 #define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3 43 #define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters 44 #define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset 45 #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset 46 47 // 48 // Operational registers offset 49 // 50 #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset 51 #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset 52 #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset 53 #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset 54 #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset 55 #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset 56 #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset 57 #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset 58 59 // 60 // Runtime registers offset 61 // 62 #define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset 63 #define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset 64 #define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset 65 #define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset 66 #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset 67 #define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset 68 69 // 70 // Debug registers offset 71 // 72 #define XHC_DC_DCCTRL 0x20 73 74 #define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore 75 #define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore 76 77 #pragma pack (1) 78 typedef struct { 79 UINT8 MaxSlots; // Number of Device Slots 80 UINT16 MaxIntrs:11; // Number of Interrupters 81 UINT16 Rsvd:5; 82 UINT8 MaxPorts; // Number of Ports 83 } HCSPARAMS1; 84 85 // 86 // Structural Parameters 1 Register Bitmap Definition 87 // 88 typedef union { 89 UINT32 Dword; 90 HCSPARAMS1 Data; 91 } XHC_HCSPARAMS1; 92 93 typedef struct { 94 UINT32 Ist:4; // Isochronous Scheduling Threshold 95 UINT32 Erst:4; // Event Ring Segment Table Max 96 UINT32 Rsvd:13; 97 UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi 98 UINT32 Spr:1; // Scratchpad Restore 99 UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo 100 } HCSPARAMS2; 101 102 // 103 // Structural Parameters 2 Register Bitmap Definition 104 // 105 typedef union { 106 UINT32 Dword; 107 HCSPARAMS2 Data; 108 } XHC_HCSPARAMS2; 109 110 typedef struct { 111 UINT16 Ac64:1; // 64-bit Addressing Capability 112 UINT16 Bnc:1; // BW Negotiation Capability 113 UINT16 Csz:1; // Context Size 114 UINT16 Ppc:1; // Port Power Control 115 UINT16 Pind:1; // Port Indicators 116 UINT16 Lhrc:1; // Light HC Reset Capability 117 UINT16 Ltc:1; // Latency Tolerance Messaging Capability 118 UINT16 Nss:1; // No Secondary SID Support 119 UINT16 Pae:1; // Parse All Event Data 120 UINT16 Rsvd:3; 121 UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size 122 UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer 123 } HCCPARAMS; 124 125 // 126 // Capability Parameters Register Bitmap Definition 127 // 128 typedef union { 129 UINT32 Dword; 130 HCCPARAMS Data; 131 } XHC_HCCPARAMS; 132 133 #pragma pack () 134 135 // 136 // Register Bit Definition 137 // 138 #define XHC_USBCMD_RUN BIT0 // Run/Stop 139 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset 140 #define XHC_USBCMD_INTE BIT2 // Interrupter Enable 141 #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable 142 143 #define XHC_USBSTS_HALT BIT0 // Host Controller Halted 144 #define XHC_USBSTS_HSE BIT2 // Host System Error 145 #define XHC_USBSTS_EINT BIT3 // Event Interrupt 146 #define XHC_USBSTS_PCD BIT4 // Port Change Detect 147 #define XHC_USBSTS_SSS BIT8 // Save State Status 148 #define XHC_USBSTS_RSS BIT9 // Restore State Status 149 #define XHC_USBSTS_SRE BIT10 // Save/Restore Error 150 #define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready 151 #define XHC_USBSTS_HCE BIT12 // Host Controller Error 152 153 #define XHC_PAGESIZE_MASK 0xFFFF // Page Size 154 155 #define XHC_CRCR_RCS BIT0 // Ring Cycle State 156 #define XHC_CRCR_CS BIT1 // Command Stop 157 #define XHC_CRCR_CA BIT2 // Command Abort 158 #define XHC_CRCR_CRR BIT3 // Command Ring Running 159 160 #define XHC_CONFIG_MASK 0xFF // Command Ring Running 161 162 #define XHC_PORTSC_CCS BIT0 // Current Connect Status 163 #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled 164 #define XHC_PORTSC_OCA BIT3 // Over-current Active 165 #define XHC_PORTSC_RESET BIT4 // Port Reset 166 #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State 167 #define XHC_PORTSC_PP BIT9 // Port Power 168 #define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed 169 #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe 170 #define XHC_PORTSC_CSC BIT17 // Connect Status Change 171 #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change 172 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change 173 #define XHC_PORTSC_OCC BIT20 // Over-Current Change 174 #define XHC_PORTSC_PRC BIT21 // Port Reset Change 175 #define XHC_PORTSC_PLC BIT22 // Port Link State Change 176 #define XHC_PORTSC_CEC BIT23 // Port Config Error Change 177 #define XHC_PORTSC_CAS BIT24 // Cold Attach Status 178 179 #define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status 180 #define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled 181 #define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active 182 #define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset 183 #define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power 184 #define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change 185 #define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change 186 #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change 187 #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change 188 #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change 189 #define XHC_IMAN_IP BIT0 // Interrupt Pending 190 #define XHC_IMAN_IE BIT1 // Interrupt Enable 191 192 #define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval 193 #define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter 194 195 // 196 // Hub Class Feature Selector for Clear Port Feature Request 197 // It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec. 198 // For more details, Please refer to USB 3.0 Spec Table 10-7. 199 // 200 typedef enum { 201 Usb3PortBHPortReset = 28, 202 Usb3PortBHPortResetChange = 29 203 } XHC_PORT_FEATURE; 204 205 // 206 // Structure to map the hardware port states to the 207 // UEFI's port states. 208 // 209 typedef struct { 210 UINT32 HwState; 211 UINT16 UefiState; 212 } USB_PORT_STATE_MAP; 213 214 // 215 // Structure to map the hardware port states to feature selector for clear port feature request. 216 // 217 typedef struct { 218 UINT32 HwState; 219 UINT16 Selector; 220 } USB_CLEAR_PORT_MAP; 221 222 /** 223 Read 1-byte width XHCI capability register. 224 225 @param Xhc The XHCI Instance. 226 @param Offset The offset of the 1-byte width capability register. 227 228 @return The register content read. 229 @retval If err, return 0xFFFF. 230 231 **/ 232 UINT8 233 XhcReadCapReg8 ( 234 IN USB_XHCI_INSTANCE *Xhc, 235 IN UINT32 Offset 236 ); 237 238 /** 239 Read 4-bytes width XHCI capability register. 240 241 @param Xhc The XHCI Instance. 242 @param Offset The offset of the 4-bytes width capability register. 243 244 @return The register content read. 245 @retval If err, return 0xFFFFFFFF. 246 247 **/ 248 UINT32 249 XhcReadCapReg ( 250 IN USB_XHCI_INSTANCE *Xhc, 251 IN UINT32 Offset 252 ); 253 254 /** 255 Read 4-bytes width XHCI Operational register. 256 257 @param Xhc The XHCI Instance. 258 @param Offset The offset of the 4-bytes width operational register. 259 260 @return The register content read. 261 @retval If err, return 0xFFFFFFFF. 262 263 **/ 264 UINT32 265 XhcReadOpReg ( 266 IN USB_XHCI_INSTANCE *Xhc, 267 IN UINT32 Offset 268 ); 269 270 /** 271 Write the data to the 4-bytes width XHCI operational register. 272 273 @param Xhc The XHCI Instance. 274 @param Offset The offset of the 4-bytes width operational register. 275 @param Data The data to write. 276 277 **/ 278 VOID 279 XhcWriteOpReg ( 280 IN USB_XHCI_INSTANCE *Xhc, 281 IN UINT32 Offset, 282 IN UINT32 Data 283 ); 284 285 286 /** 287 Read XHCI runtime register. 288 289 @param Xhc The XHCI Instance. 290 @param Offset The offset of the runtime register. 291 292 @return The register content read 293 294 **/ 295 UINT32 296 XhcReadRuntimeReg ( 297 IN USB_XHCI_INSTANCE *Xhc, 298 IN UINT32 Offset 299 ); 300 301 /** 302 Write the data to the XHCI runtime register. 303 304 @param Xhc The XHCI Instance. 305 @param Offset The offset of the runtime register. 306 @param Data The data to write. 307 308 **/ 309 VOID 310 XhcWriteRuntimeReg ( 311 IN USB_XHCI_INSTANCE *Xhc, 312 IN UINT32 Offset, 313 IN UINT32 Data 314 ); 315 316 317 /** 318 Write the data to the XHCI door bell register. 319 320 @param Xhc The XHCI Instance. 321 @param Offset The offset of the door bell register. 322 @param Data The data to write. 323 324 **/ 325 VOID 326 XhcWriteDoorBellReg ( 327 IN USB_XHCI_INSTANCE *Xhc, 328 IN UINT32 Offset, 329 IN UINT32 Data 330 ); 331 332 /** 333 Set one bit of the operational register while keeping other bits. 334 335 @param Xhc The XHCI Instance. 336 @param Offset The offset of the operational register. 337 @param Bit The bit mask of the register to set. 338 339 **/ 340 VOID 341 XhcSetOpRegBit ( 342 IN USB_XHCI_INSTANCE *Xhc, 343 IN UINT32 Offset, 344 IN UINT32 Bit 345 ); 346 347 /** 348 Clear one bit of the operational register while keeping other bits. 349 350 @param Xhc The XHCI Instance. 351 @param Offset The offset of the operational register. 352 @param Bit The bit mask of the register to clear. 353 354 **/ 355 VOID 356 XhcClearOpRegBit ( 357 IN USB_XHCI_INSTANCE *Xhc, 358 IN UINT32 Offset, 359 IN UINT32 Bit 360 ); 361 362 /** 363 Wait the operation register's bit as specified by Bit 364 to be set (or clear). 365 366 @param Xhc The XHCI Instance. 367 @param Offset The offset of the operational register. 368 @param Bit The bit of the register to wait for. 369 @param WaitToSet Wait the bit to set or clear. 370 @param Timeout The time to wait before abort (in millisecond, ms). 371 372 @retval EFI_SUCCESS The bit successfully changed by host controller. 373 @retval EFI_TIMEOUT The time out occurred. 374 375 **/ 376 EFI_STATUS 377 XhcWaitOpRegBit ( 378 IN USB_XHCI_INSTANCE *Xhc, 379 IN UINT32 Offset, 380 IN UINT32 Bit, 381 IN BOOLEAN WaitToSet, 382 IN UINT32 Timeout 383 ); 384 385 /** 386 Read XHCI runtime register. 387 388 @param Xhc The XHCI Instance. 389 @param Offset The offset of the runtime register. 390 391 @return The register content read 392 393 **/ 394 UINT32 395 XhcReadRuntimeReg ( 396 IN USB_XHCI_INSTANCE *Xhc, 397 IN UINT32 Offset 398 ); 399 400 /** 401 Write the data to the XHCI runtime register. 402 403 @param Xhc The XHCI Instance. 404 @param Offset The offset of the runtime register. 405 @param Data The data to write. 406 407 **/ 408 VOID 409 XhcWriteRuntimeReg ( 410 IN USB_XHCI_INSTANCE *Xhc, 411 IN UINT32 Offset, 412 IN UINT32 Data 413 ); 414 415 /** 416 Set one bit of the runtime register while keeping other bits. 417 418 @param Xhc The XHCI Instance. 419 @param Offset The offset of the runtime register. 420 @param Bit The bit mask of the register to set. 421 422 **/ 423 VOID 424 XhcSetRuntimeRegBit ( 425 IN USB_XHCI_INSTANCE *Xhc, 426 IN UINT32 Offset, 427 IN UINT32 Bit 428 ); 429 430 /** 431 Clear one bit of the runtime register while keeping other bits. 432 433 @param Xhc The XHCI Instance. 434 @param Offset The offset of the runtime register. 435 @param Bit The bit mask of the register to set. 436 437 **/ 438 VOID 439 XhcClearRuntimeRegBit ( 440 IN USB_XHCI_INSTANCE *Xhc, 441 IN UINT32 Offset, 442 IN UINT32 Bit 443 ); 444 445 /** 446 Read XHCI extended capability register. 447 448 @param Xhc The XHCI Instance. 449 @param Offset The offset of the extended capability register. 450 451 @return The register content read 452 453 **/ 454 UINT32 455 XhcReadExtCapReg ( 456 IN USB_XHCI_INSTANCE *Xhc, 457 IN UINT32 Offset 458 ); 459 460 /** 461 Whether the XHCI host controller is halted. 462 463 @param Xhc The XHCI Instance. 464 465 @retval TRUE The controller is halted. 466 @retval FALSE It isn't halted. 467 468 **/ 469 BOOLEAN 470 XhcIsHalt ( 471 IN USB_XHCI_INSTANCE *Xhc 472 ); 473 474 /** 475 Whether system error occurred. 476 477 @param Xhc The XHCI Instance. 478 479 @retval TRUE System error happened. 480 @retval FALSE No system error. 481 482 **/ 483 BOOLEAN 484 XhcIsSysError ( 485 IN USB_XHCI_INSTANCE *Xhc 486 ); 487 488 /** 489 Reset the XHCI host controller. 490 491 @param Xhc The XHCI Instance. 492 @param Timeout Time to wait before abort (in millisecond, ms). 493 494 @retval EFI_SUCCESS The XHCI host controller is reset. 495 @return Others Failed to reset the XHCI before Timeout. 496 497 **/ 498 EFI_STATUS 499 XhcResetHC ( 500 IN USB_XHCI_INSTANCE *Xhc, 501 IN UINT32 Timeout 502 ); 503 504 /** 505 Halt the XHCI host controller. 506 507 @param Xhc The XHCI Instance. 508 @param Timeout Time to wait before abort (in millisecond, ms). 509 510 @return EFI_SUCCESS The XHCI host controller is halt. 511 @return EFI_TIMEOUT Failed to halt the XHCI before Timeout. 512 513 **/ 514 EFI_STATUS 515 XhcHaltHC ( 516 IN USB_XHCI_INSTANCE *Xhc, 517 IN UINT32 Timeout 518 ); 519 520 /** 521 Set the XHCI host controller to run. 522 523 @param Xhc The XHCI Instance. 524 @param Timeout Time to wait before abort (in millisecond, ms). 525 526 @return EFI_SUCCESS The XHCI host controller is running. 527 @return EFI_TIMEOUT Failed to set the XHCI to run before Timeout. 528 529 **/ 530 EFI_STATUS 531 XhcRunHC ( 532 IN USB_XHCI_INSTANCE *Xhc, 533 IN UINT32 Timeout 534 ); 535 536 /** 537 Calculate the offset of the XHCI capability. 538 539 @param Xhc The XHCI Instance. 540 @param CapId The XHCI Capability ID. 541 542 @return The offset of XHCI legacy support capability register. 543 544 **/ 545 UINT32 546 XhcGetCapabilityAddr ( 547 IN USB_XHCI_INSTANCE *Xhc, 548 IN UINT8 CapId 549 ); 550 551 #endif 552