1 /** @file 2 3 This file contains the definition for XHCI host controller schedule routines. 4 5 Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR> 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef _EFI_XHCI_SCHED_H_ 11 #define _EFI_XHCI_SCHED_H_ 12 13 #define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R') 14 15 // 16 // Transfer types, used in URB to identify the transfer type 17 // 18 #define XHC_CTRL_TRANSFER 0x01 19 #define XHC_BULK_TRANSFER 0x02 20 #define XHC_INT_TRANSFER_SYNC 0x04 21 #define XHC_INT_TRANSFER_ASYNC 0x08 22 #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10 23 24 // 25 // 6.4.6 TRB Types 26 // 27 #define TRB_TYPE_NORMAL 1 28 #define TRB_TYPE_SETUP_STAGE 2 29 #define TRB_TYPE_DATA_STAGE 3 30 #define TRB_TYPE_STATUS_STAGE 4 31 #define TRB_TYPE_ISOCH 5 32 #define TRB_TYPE_LINK 6 33 #define TRB_TYPE_EVENT_DATA 7 34 #define TRB_TYPE_NO_OP 8 35 #define TRB_TYPE_EN_SLOT 9 36 #define TRB_TYPE_DIS_SLOT 10 37 #define TRB_TYPE_ADDRESS_DEV 11 38 #define TRB_TYPE_CON_ENDPOINT 12 39 #define TRB_TYPE_EVALU_CONTXT 13 40 #define TRB_TYPE_RESET_ENDPOINT 14 41 #define TRB_TYPE_STOP_ENDPOINT 15 42 #define TRB_TYPE_SET_TR_DEQUE 16 43 #define TRB_TYPE_RESET_DEV 17 44 #define TRB_TYPE_GET_PORT_BANW 21 45 #define TRB_TYPE_FORCE_HEADER 22 46 #define TRB_TYPE_NO_OP_COMMAND 23 47 #define TRB_TYPE_TRANS_EVENT 32 48 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33 49 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34 50 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37 51 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38 52 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39 53 54 // 55 // Endpoint Type (EP Type). 56 // 57 #define ED_NOT_VALID 0 58 #define ED_ISOCH_OUT 1 59 #define ED_BULK_OUT 2 60 #define ED_INTERRUPT_OUT 3 61 #define ED_CONTROL_BIDIR 4 62 #define ED_ISOCH_IN 5 63 #define ED_BULK_IN 6 64 #define ED_INTERRUPT_IN 7 65 66 // 67 // 6.4.5 TRB Completion Codes 68 // 69 #define TRB_COMPLETION_INVALID 0 70 #define TRB_COMPLETION_SUCCESS 1 71 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2 72 #define TRB_COMPLETION_BABBLE_ERROR 3 73 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4 74 #define TRB_COMPLETION_TRB_ERROR 5 75 #define TRB_COMPLETION_STALL_ERROR 6 76 #define TRB_COMPLETION_SHORT_PACKET 13 77 #define TRB_COMPLETION_STOPPED 26 78 #define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27 79 80 // 81 // The topology string used to present usb device location 82 // 83 typedef struct _USB_DEV_TOPOLOGY { 84 // 85 // The tier concatenation of down stream port. 86 // 87 UINT32 RouteString:20; 88 // 89 // The root port number of the chain. 90 // 91 UINT32 RootPortNum:8; 92 // 93 // The Tier the device reside. 94 // 95 UINT32 TierNum:4; 96 } USB_DEV_TOPOLOGY; 97 98 // 99 // USB Device's RouteChart 100 // 101 typedef union _USB_DEV_ROUTE { 102 UINT32 Dword; 103 USB_DEV_TOPOLOGY Route; 104 } USB_DEV_ROUTE; 105 106 // 107 // Endpoint address and its capabilities 108 // 109 typedef struct _USB_ENDPOINT { 110 // 111 // Store logical device address assigned by UsbBus 112 // It's because some XHCI host controllers may assign the same physcial device 113 // address for those devices inserted at different root port. 114 // 115 UINT8 BusAddr; 116 UINT8 DevAddr; 117 UINT8 EpAddr; 118 EFI_USB_DATA_DIRECTION Direction; 119 UINT8 DevSpeed; 120 UINTN MaxPacket; 121 UINTN Type; 122 } USB_ENDPOINT; 123 124 // 125 // TRB Template 126 // 127 typedef struct _TRB_TEMPLATE { 128 UINT32 Parameter1; 129 130 UINT32 Parameter2; 131 132 UINT32 Status; 133 134 UINT32 CycleBit:1; 135 UINT32 RsvdZ1:9; 136 UINT32 Type:6; 137 UINT32 Control:16; 138 } TRB_TEMPLATE; 139 140 typedef struct _TRANSFER_RING { 141 VOID *RingSeg0; 142 UINTN TrbNumber; 143 TRB_TEMPLATE *RingEnqueue; 144 TRB_TEMPLATE *RingDequeue; 145 UINT32 RingPCS; 146 } TRANSFER_RING; 147 148 typedef struct _EVENT_RING { 149 VOID *ERSTBase; 150 VOID *EventRingSeg0; 151 UINTN TrbNumber; 152 TRB_TEMPLATE *EventRingEnqueue; 153 TRB_TEMPLATE *EventRingDequeue; 154 UINT32 EventRingCCS; 155 } EVENT_RING; 156 157 // 158 // URB (Usb Request Block) contains information for all kinds of 159 // usb requests. 160 // 161 typedef struct _URB { 162 UINT32 Signature; 163 LIST_ENTRY UrbList; 164 // 165 // Usb Device URB related information 166 // 167 USB_ENDPOINT Ep; 168 EFI_USB_DEVICE_REQUEST *Request; 169 VOID *Data; 170 UINTN DataLen; 171 VOID *DataPhy; 172 VOID *DataMap; 173 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback; 174 VOID *Context; 175 // 176 // Execute result 177 // 178 UINT32 Result; 179 // 180 // completed data length 181 // 182 UINTN Completed; 183 // 184 // Command/Tranfer Ring info 185 // 186 TRANSFER_RING *Ring; 187 TRB_TEMPLATE *TrbStart; 188 TRB_TEMPLATE *TrbEnd; 189 UINTN TrbNum; 190 BOOLEAN StartDone; 191 BOOLEAN EndDone; 192 BOOLEAN Finished; 193 194 TRB_TEMPLATE *EvtTrb; 195 } URB; 196 197 // 198 // 6.5 Event Ring Segment Table 199 // The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime 200 // expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the 201 // Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table 202 // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1). 203 // 204 typedef struct _EVENT_RING_SEG_TABLE_ENTRY { 205 UINT32 PtrLo; 206 UINT32 PtrHi; 207 UINT32 RingTrbSize:16; 208 UINT32 RsvdZ1:16; 209 UINT32 RsvdZ2; 210 } EVENT_RING_SEG_TABLE_ENTRY; 211 212 // 213 // 6.4.1.1 Normal TRB 214 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and 215 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer 216 // Rings, and to define the Data stage information for Control Transfer Rings. 217 // 218 typedef struct _TRANSFER_TRB_NORMAL { 219 UINT32 TRBPtrLo; 220 221 UINT32 TRBPtrHi; 222 223 UINT32 Length:17; 224 UINT32 TDSize:5; 225 UINT32 IntTarget:10; 226 227 UINT32 CycleBit:1; 228 UINT32 ENT:1; 229 UINT32 ISP:1; 230 UINT32 NS:1; 231 UINT32 CH:1; 232 UINT32 IOC:1; 233 UINT32 IDT:1; 234 UINT32 RsvdZ1:2; 235 UINT32 BEI:1; 236 UINT32 Type:6; 237 UINT32 RsvdZ2:16; 238 } TRANSFER_TRB_NORMAL; 239 240 // 241 // 6.4.1.2.1 Setup Stage TRB 242 // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint. 243 // 244 typedef struct _TRANSFER_TRB_CONTROL_SETUP { 245 UINT32 bmRequestType:8; 246 UINT32 bRequest:8; 247 UINT32 wValue:16; 248 249 UINT32 wIndex:16; 250 UINT32 wLength:16; 251 252 UINT32 Length:17; 253 UINT32 RsvdZ1:5; 254 UINT32 IntTarget:10; 255 256 UINT32 CycleBit:1; 257 UINT32 RsvdZ2:4; 258 UINT32 IOC:1; 259 UINT32 IDT:1; 260 UINT32 RsvdZ3:3; 261 UINT32 Type:6; 262 UINT32 TRT:2; 263 UINT32 RsvdZ4:14; 264 } TRANSFER_TRB_CONTROL_SETUP; 265 266 // 267 // 6.4.1.2.2 Data Stage TRB 268 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer. 269 // 270 typedef struct _TRANSFER_TRB_CONTROL_DATA { 271 UINT32 TRBPtrLo; 272 273 UINT32 TRBPtrHi; 274 275 UINT32 Length:17; 276 UINT32 TDSize:5; 277 UINT32 IntTarget:10; 278 279 UINT32 CycleBit:1; 280 UINT32 ENT:1; 281 UINT32 ISP:1; 282 UINT32 NS:1; 283 UINT32 CH:1; 284 UINT32 IOC:1; 285 UINT32 IDT:1; 286 UINT32 RsvdZ1:3; 287 UINT32 Type:6; 288 UINT32 DIR:1; 289 UINT32 RsvdZ2:15; 290 } TRANSFER_TRB_CONTROL_DATA; 291 292 // 293 // 6.4.1.2.2 Data Stage TRB 294 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer. 295 // 296 typedef struct _TRANSFER_TRB_CONTROL_STATUS { 297 UINT32 RsvdZ1; 298 UINT32 RsvdZ2; 299 300 UINT32 RsvdZ3:22; 301 UINT32 IntTarget:10; 302 303 UINT32 CycleBit:1; 304 UINT32 ENT:1; 305 UINT32 RsvdZ4:2; 306 UINT32 CH:1; 307 UINT32 IOC:1; 308 UINT32 RsvdZ5:4; 309 UINT32 Type:6; 310 UINT32 DIR:1; 311 UINT32 RsvdZ6:15; 312 } TRANSFER_TRB_CONTROL_STATUS; 313 314 // 315 // 6.4.2.1 Transfer Event TRB 316 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1 317 // for more information on the use and operation of Transfer Events. 318 // 319 typedef struct _EVT_TRB_TRANSFER { 320 UINT32 TRBPtrLo; 321 322 UINT32 TRBPtrHi; 323 324 UINT32 Length:24; 325 UINT32 Completecode:8; 326 327 UINT32 CycleBit:1; 328 UINT32 RsvdZ1:1; 329 UINT32 ED:1; 330 UINT32 RsvdZ2:7; 331 UINT32 Type:6; 332 UINT32 EndpointId:5; 333 UINT32 RsvdZ3:3; 334 UINT32 SlotId:8; 335 } EVT_TRB_TRANSFER; 336 337 // 338 // 6.4.2.2 Command Completion Event TRB 339 // A Command Completion Event TRB shall be generated by the xHC when a command completes on the 340 // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events. 341 // 342 typedef struct _EVT_TRB_COMMAND_COMPLETION { 343 UINT32 TRBPtrLo; 344 345 UINT32 TRBPtrHi; 346 347 UINT32 RsvdZ2:24; 348 UINT32 Completecode:8; 349 350 UINT32 CycleBit:1; 351 UINT32 RsvdZ3:9; 352 UINT32 Type:6; 353 UINT32 VFID:8; 354 UINT32 SlotId:8; 355 } EVT_TRB_COMMAND_COMPLETION; 356 357 typedef union _TRB { 358 TRB_TEMPLATE TrbTemplate; 359 TRANSFER_TRB_NORMAL TrbNormal; 360 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup; 361 TRANSFER_TRB_CONTROL_DATA TrbCtrData; 362 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus; 363 } TRB; 364 365 // 366 // 6.4.3.1 No Op Command TRB 367 // The No Op Command TRB provides a simple means for verifying the operation of the Command Ring 368 // mechanisms offered by the xHCI. 369 // 370 typedef struct _CMD_TRB_NO_OP { 371 UINT32 RsvdZ0; 372 UINT32 RsvdZ1; 373 UINT32 RsvdZ2; 374 375 UINT32 CycleBit:1; 376 UINT32 RsvdZ3:9; 377 UINT32 Type:6; 378 UINT32 RsvdZ4:16; 379 } CMD_TRB_NO_OP; 380 381 // 382 // 6.4.3.2 Enable Slot Command TRB 383 // The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the 384 // selected slot to the host in a Command Completion Event. 385 // 386 typedef struct _CMD_TRB_ENABLE_SLOT { 387 UINT32 RsvdZ0; 388 UINT32 RsvdZ1; 389 UINT32 RsvdZ2; 390 391 UINT32 CycleBit:1; 392 UINT32 RsvdZ3:9; 393 UINT32 Type:6; 394 UINT32 RsvdZ4:16; 395 } CMD_TRB_ENABLE_SLOT; 396 397 // 398 // 6.4.3.3 Disable Slot Command TRB 399 // The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any 400 // internal xHC resources assigned to the slot. 401 // 402 typedef struct _CMD_TRB_DISABLE_SLOT { 403 UINT32 RsvdZ0; 404 UINT32 RsvdZ1; 405 UINT32 RsvdZ2; 406 407 UINT32 CycleBit:1; 408 UINT32 RsvdZ3:9; 409 UINT32 Type:6; 410 UINT32 RsvdZ4:8; 411 UINT32 SlotId:8; 412 } CMD_TRB_DISABLE_SLOT; 413 414 // 415 // 6.4.3.4 Address Device Command TRB 416 // The Address Device Command TRB transitions the selected Device Context from the Default to the 417 // Addressed state and causes the xHC to select an address for the USB device in the Default State and 418 // issue a SET_ADDRESS request to the USB device. 419 // 420 typedef struct _CMD_TRB_ADDRESS_DEVICE { 421 UINT32 PtrLo; 422 423 UINT32 PtrHi; 424 425 UINT32 RsvdZ1; 426 427 UINT32 CycleBit:1; 428 UINT32 RsvdZ2:8; 429 UINT32 BSR:1; 430 UINT32 Type:6; 431 UINT32 RsvdZ3:8; 432 UINT32 SlotId:8; 433 } CMD_TRB_ADDRESS_DEVICE; 434 435 // 436 // 6.4.3.5 Configure Endpoint Command TRB 437 // The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the 438 // endpoints selected by the command. 439 // 440 typedef struct _CMD_TRB_CONFIG_ENDPOINT { 441 UINT32 PtrLo; 442 443 UINT32 PtrHi; 444 445 UINT32 RsvdZ1; 446 447 UINT32 CycleBit:1; 448 UINT32 RsvdZ2:8; 449 UINT32 DC:1; 450 UINT32 Type:6; 451 UINT32 RsvdZ3:8; 452 UINT32 SlotId:8; 453 } CMD_TRB_CONFIG_ENDPOINT; 454 455 // 456 // 6.4.3.6 Evaluate Context Command TRB 457 // The Evaluate Context Command TRB is used by system software to inform the xHC that the selected 458 // Context data structures in the Device Context have been modified by system software and that the xHC 459 // shall evaluate any changes 460 // 461 typedef struct _CMD_TRB_EVALUATE_CONTEXT { 462 UINT32 PtrLo; 463 464 UINT32 PtrHi; 465 466 UINT32 RsvdZ1; 467 468 UINT32 CycleBit:1; 469 UINT32 RsvdZ2:9; 470 UINT32 Type:6; 471 UINT32 RsvdZ3:8; 472 UINT32 SlotId:8; 473 } CMD_TRB_EVALUATE_CONTEXT; 474 475 // 476 // 6.4.3.7 Reset Endpoint Command TRB 477 // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring 478 // 479 typedef struct _CMD_TRB_RESET_ENDPOINT { 480 UINT32 RsvdZ0; 481 UINT32 RsvdZ1; 482 UINT32 RsvdZ2; 483 484 UINT32 CycleBit:1; 485 UINT32 RsvdZ3:8; 486 UINT32 TSP:1; 487 UINT32 Type:6; 488 UINT32 EDID:5; 489 UINT32 RsvdZ4:3; 490 UINT32 SlotId:8; 491 } CMD_TRB_RESET_ENDPOINT; 492 493 // 494 // 6.4.3.8 Stop Endpoint Command TRB 495 // The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a 496 // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC. 497 // 498 typedef struct _CMD_TRB_STOP_ENDPOINT { 499 UINT32 RsvdZ0; 500 UINT32 RsvdZ1; 501 UINT32 RsvdZ2; 502 503 UINT32 CycleBit:1; 504 UINT32 RsvdZ3:9; 505 UINT32 Type:6; 506 UINT32 EDID:5; 507 UINT32 RsvdZ4:2; 508 UINT32 SP:1; 509 UINT32 SlotId:8; 510 } CMD_TRB_STOP_ENDPOINT; 511 512 // 513 // 6.4.3.9 Set TR Dequeue Pointer Command TRB 514 // The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue 515 // Pointer and DCS fields of an Endpoint or Stream Context. 516 // 517 typedef struct _CMD_SET_TR_DEQ_POINTER { 518 UINT32 PtrLo; 519 520 UINT32 PtrHi; 521 522 UINT32 RsvdZ1:16; 523 UINT32 StreamID:16; 524 525 UINT32 CycleBit:1; 526 UINT32 RsvdZ2:9; 527 UINT32 Type:6; 528 UINT32 Endpoint:5; 529 UINT32 RsvdZ3:3; 530 UINT32 SlotId:8; 531 } CMD_SET_TR_DEQ_POINTER; 532 533 // 534 // 6.4.4.1 Link TRB 535 // A Link TRB provides support for non-contiguous TRB Rings. 536 // 537 typedef struct _LINK_TRB { 538 UINT32 PtrLo; 539 540 UINT32 PtrHi; 541 542 UINT32 RsvdZ1:22; 543 UINT32 InterTarget:10; 544 545 UINT32 CycleBit:1; 546 UINT32 TC:1; 547 UINT32 RsvdZ2:2; 548 UINT32 CH:1; 549 UINT32 IOC:1; 550 UINT32 RsvdZ3:4; 551 UINT32 Type:6; 552 UINT32 RsvdZ4:16; 553 } LINK_TRB; 554 555 // 556 // 6.2.2 Slot Context 557 // 558 typedef struct _SLOT_CONTEXT { 559 UINT32 RouteString:20; 560 UINT32 Speed:4; 561 UINT32 RsvdZ1:1; 562 UINT32 MTT:1; 563 UINT32 Hub:1; 564 UINT32 ContextEntries:5; 565 566 UINT32 MaxExitLatency:16; 567 UINT32 RootHubPortNum:8; 568 UINT32 PortNum:8; 569 570 UINT32 TTHubSlotId:8; 571 UINT32 TTPortNum:8; 572 UINT32 TTT:2; 573 UINT32 RsvdZ2:4; 574 UINT32 InterTarget:10; 575 576 UINT32 DeviceAddress:8; 577 UINT32 RsvdZ3:19; 578 UINT32 SlotState:5; 579 580 UINT32 RsvdZ4; 581 UINT32 RsvdZ5; 582 UINT32 RsvdZ6; 583 UINT32 RsvdZ7; 584 } SLOT_CONTEXT; 585 586 typedef struct _SLOT_CONTEXT_64 { 587 UINT32 RouteString:20; 588 UINT32 Speed:4; 589 UINT32 RsvdZ1:1; 590 UINT32 MTT:1; 591 UINT32 Hub:1; 592 UINT32 ContextEntries:5; 593 594 UINT32 MaxExitLatency:16; 595 UINT32 RootHubPortNum:8; 596 UINT32 PortNum:8; 597 598 UINT32 TTHubSlotId:8; 599 UINT32 TTPortNum:8; 600 UINT32 TTT:2; 601 UINT32 RsvdZ2:4; 602 UINT32 InterTarget:10; 603 604 UINT32 DeviceAddress:8; 605 UINT32 RsvdZ3:19; 606 UINT32 SlotState:5; 607 608 UINT32 RsvdZ4; 609 UINT32 RsvdZ5; 610 UINT32 RsvdZ6; 611 UINT32 RsvdZ7; 612 613 UINT32 RsvdZ8; 614 UINT32 RsvdZ9; 615 UINT32 RsvdZ10; 616 UINT32 RsvdZ11; 617 618 UINT32 RsvdZ12; 619 UINT32 RsvdZ13; 620 UINT32 RsvdZ14; 621 UINT32 RsvdZ15; 622 623 } SLOT_CONTEXT_64; 624 625 626 // 627 // 6.2.3 Endpoint Context 628 // 629 typedef struct _ENDPOINT_CONTEXT { 630 UINT32 EPState:3; 631 UINT32 RsvdZ1:5; 632 UINT32 Mult:2; 633 UINT32 MaxPStreams:5; 634 UINT32 LSA:1; 635 UINT32 Interval:8; 636 UINT32 RsvdZ2:8; 637 638 UINT32 RsvdZ3:1; 639 UINT32 CErr:2; 640 UINT32 EPType:3; 641 UINT32 RsvdZ4:1; 642 UINT32 HID:1; 643 UINT32 MaxBurstSize:8; 644 UINT32 MaxPacketSize:16; 645 646 UINT32 PtrLo; 647 648 UINT32 PtrHi; 649 650 UINT32 AverageTRBLength:16; 651 UINT32 MaxESITPayload:16; 652 653 UINT32 RsvdZ5; 654 UINT32 RsvdZ6; 655 UINT32 RsvdZ7; 656 } ENDPOINT_CONTEXT; 657 658 typedef struct _ENDPOINT_CONTEXT_64 { 659 UINT32 EPState:3; 660 UINT32 RsvdZ1:5; 661 UINT32 Mult:2; 662 UINT32 MaxPStreams:5; 663 UINT32 LSA:1; 664 UINT32 Interval:8; 665 UINT32 RsvdZ2:8; 666 667 UINT32 RsvdZ3:1; 668 UINT32 CErr:2; 669 UINT32 EPType:3; 670 UINT32 RsvdZ4:1; 671 UINT32 HID:1; 672 UINT32 MaxBurstSize:8; 673 UINT32 MaxPacketSize:16; 674 675 UINT32 PtrLo; 676 677 UINT32 PtrHi; 678 679 UINT32 AverageTRBLength:16; 680 UINT32 MaxESITPayload:16; 681 682 UINT32 RsvdZ5; 683 UINT32 RsvdZ6; 684 UINT32 RsvdZ7; 685 686 UINT32 RsvdZ8; 687 UINT32 RsvdZ9; 688 UINT32 RsvdZ10; 689 UINT32 RsvdZ11; 690 691 UINT32 RsvdZ12; 692 UINT32 RsvdZ13; 693 UINT32 RsvdZ14; 694 UINT32 RsvdZ15; 695 696 } ENDPOINT_CONTEXT_64; 697 698 699 // 700 // 6.2.5.1 Input Control Context 701 // 702 typedef struct _INPUT_CONTRL_CONTEXT { 703 UINT32 Dword1; 704 UINT32 Dword2; 705 UINT32 RsvdZ1; 706 UINT32 RsvdZ2; 707 UINT32 RsvdZ3; 708 UINT32 RsvdZ4; 709 UINT32 RsvdZ5; 710 UINT32 RsvdZ6; 711 } INPUT_CONTRL_CONTEXT; 712 713 typedef struct _INPUT_CONTRL_CONTEXT_64 { 714 UINT32 Dword1; 715 UINT32 Dword2; 716 UINT32 RsvdZ1; 717 UINT32 RsvdZ2; 718 UINT32 RsvdZ3; 719 UINT32 RsvdZ4; 720 UINT32 RsvdZ5; 721 UINT32 RsvdZ6; 722 UINT32 RsvdZ7; 723 UINT32 RsvdZ8; 724 UINT32 RsvdZ9; 725 UINT32 RsvdZ10; 726 UINT32 RsvdZ11; 727 UINT32 RsvdZ12; 728 UINT32 RsvdZ13; 729 UINT32 RsvdZ14; 730 } INPUT_CONTRL_CONTEXT_64; 731 732 // 733 // 6.2.1 Device Context 734 // 735 typedef struct _DEVICE_CONTEXT { 736 SLOT_CONTEXT Slot; 737 ENDPOINT_CONTEXT EP[31]; 738 } DEVICE_CONTEXT; 739 740 typedef struct _DEVICE_CONTEXT_64 { 741 SLOT_CONTEXT_64 Slot; 742 ENDPOINT_CONTEXT_64 EP[31]; 743 } DEVICE_CONTEXT_64; 744 745 // 746 // 6.2.5 Input Context 747 // 748 typedef struct _INPUT_CONTEXT { 749 INPUT_CONTRL_CONTEXT InputControlContext; 750 SLOT_CONTEXT Slot; 751 ENDPOINT_CONTEXT EP[31]; 752 } INPUT_CONTEXT; 753 754 typedef struct _INPUT_CONTEXT_64 { 755 INPUT_CONTRL_CONTEXT_64 InputControlContext; 756 SLOT_CONTEXT_64 Slot; 757 ENDPOINT_CONTEXT_64 EP[31]; 758 } INPUT_CONTEXT_64; 759 760 761 /** 762 Initialize the XHCI host controller for schedule. 763 764 @param Xhc The XHCI Instance to be initialized. 765 766 **/ 767 VOID 768 XhcInitSched ( 769 IN USB_XHCI_INSTANCE *Xhc 770 ); 771 772 /** 773 Free the resouce allocated at initializing schedule. 774 775 @param Xhc The XHCI Instance. 776 777 **/ 778 VOID 779 XhcFreeSched ( 780 IN USB_XHCI_INSTANCE *Xhc 781 ); 782 783 /** 784 Ring the door bell to notify XHCI there is a transaction to be executed through URB. 785 786 @param Xhc The XHCI Instance. 787 @param Urb The URB to be rung. 788 789 @retval EFI_SUCCESS Successfully ring the door bell. 790 791 **/ 792 EFI_STATUS 793 RingIntTransferDoorBell ( 794 IN USB_XHCI_INSTANCE *Xhc, 795 IN URB *Urb 796 ); 797 798 /** 799 Execute the transfer by polling the URB. This is a synchronous operation. 800 801 @param Xhc The XHCI Instance. 802 @param CmdTransfer The executed URB is for cmd transfer or not. 803 @param Urb The URB to execute. 804 @param Timeout The time to wait before abort, in millisecond. 805 806 @return EFI_DEVICE_ERROR The transfer failed due to transfer error. 807 @return EFI_TIMEOUT The transfer failed due to time out. 808 @return EFI_SUCCESS The transfer finished OK. 809 810 **/ 811 EFI_STATUS 812 XhcExecTransfer ( 813 IN USB_XHCI_INSTANCE *Xhc, 814 IN BOOLEAN CmdTransfer, 815 IN URB *Urb, 816 IN UINTN Timeout 817 ); 818 819 /** 820 Delete a single asynchronous interrupt transfer for 821 the device and endpoint. 822 823 @param Xhc The XHCI Instance. 824 @param BusAddr The logical device address assigned by UsbBus driver. 825 @param EpNum The endpoint of the target. 826 827 @retval EFI_SUCCESS An asynchronous transfer is removed. 828 @retval EFI_NOT_FOUND No transfer for the device is found. 829 830 **/ 831 EFI_STATUS 832 XhciDelAsyncIntTransfer ( 833 IN USB_XHCI_INSTANCE *Xhc, 834 IN UINT8 BusAddr, 835 IN UINT8 EpNum 836 ); 837 838 /** 839 Remove all the asynchronous interrupt transfers. 840 841 @param Xhc The XHCI Instance. 842 843 **/ 844 VOID 845 XhciDelAllAsyncIntTransfers ( 846 IN USB_XHCI_INSTANCE *Xhc 847 ); 848 849 /** 850 Insert a single asynchronous interrupt transfer for 851 the device and endpoint. 852 853 @param Xhc The XHCI Instance 854 @param BusAddr The logical device address assigned by UsbBus driver 855 @param EpAddr Endpoint addrress 856 @param DevSpeed The device speed 857 @param MaxPacket The max packet length of the endpoint 858 @param DataLen The length of data buffer 859 @param Callback The function to call when data is transferred 860 @param Context The context to the callback 861 862 @return Created URB or NULL 863 864 **/ 865 URB * 866 XhciInsertAsyncIntTransfer ( 867 IN USB_XHCI_INSTANCE *Xhc, 868 IN UINT8 BusAddr, 869 IN UINT8 EpAddr, 870 IN UINT8 DevSpeed, 871 IN UINTN MaxPacket, 872 IN UINTN DataLen, 873 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback, 874 IN VOID *Context 875 ); 876 877 /** 878 Set Bios Ownership 879 880 @param Xhc The XHCI Instance. 881 882 **/ 883 VOID 884 XhcSetBiosOwnership ( 885 IN USB_XHCI_INSTANCE *Xhc 886 ); 887 888 /** 889 Clear Bios Ownership 890 891 @param Xhc The XHCI Instance. 892 893 **/ 894 VOID 895 XhcClearBiosOwnership ( 896 IN USB_XHCI_INSTANCE *Xhc 897 ); 898 899 /** 900 Find out the slot id according to the device's route string. 901 902 @param Xhc The XHCI Instance. 903 @param RouteString The route string described the device location. 904 905 @return The slot id used by the device. 906 907 **/ 908 UINT8 909 EFIAPI 910 XhcRouteStringToSlotId ( 911 IN USB_XHCI_INSTANCE *Xhc, 912 IN USB_DEV_ROUTE RouteString 913 ); 914 915 /** 916 Calculate the device context index by endpoint address and direction. 917 918 @param EpAddr The target endpoint number. 919 @param Direction The direction of the target endpoint. 920 921 @return The device context index of endpoint. 922 923 **/ 924 UINT8 925 XhcEndpointToDci ( 926 IN UINT8 EpAddr, 927 IN UINT8 Direction 928 ); 929 930 /** 931 Ring the door bell to notify XHCI there is a transaction to be executed. 932 933 @param Xhc The XHCI Instance. 934 @param SlotId The slot id of the target device. 935 @param Dci The device context index of the target slot or endpoint. 936 937 @retval EFI_SUCCESS Successfully ring the door bell. 938 939 **/ 940 EFI_STATUS 941 EFIAPI 942 XhcRingDoorBell ( 943 IN USB_XHCI_INSTANCE *Xhc, 944 IN UINT8 SlotId, 945 IN UINT8 Dci 946 ); 947 948 /** 949 Interrupt transfer periodic check handler. 950 951 @param Event Interrupt event. 952 @param Context Pointer to USB_XHCI_INSTANCE. 953 954 **/ 955 VOID 956 EFIAPI 957 XhcMonitorAsyncRequests ( 958 IN EFI_EVENT Event, 959 IN VOID *Context 960 ); 961 962 /** 963 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached. 964 965 @param Xhc The XHCI Instance. 966 @param ParentRouteChart The route string pointed to the parent device if it exists. 967 @param Port The port to be polled. 968 @param PortState The port state. 969 970 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state. 971 @retval Others Should not appear. 972 973 **/ 974 EFI_STATUS 975 EFIAPI 976 XhcPollPortStatusChange ( 977 IN USB_XHCI_INSTANCE *Xhc, 978 IN USB_DEV_ROUTE ParentRouteChart, 979 IN UINT8 Port, 980 IN EFI_USB_PORT_STATUS *PortState 981 ); 982 983 /** 984 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd. 985 986 @param Xhc The XHCI Instance. 987 @param SlotId The slot id to be configured. 988 @param PortNum The total number of downstream port supported by the hub. 989 @param TTT The TT think time of the hub device. 990 @param MTT The multi-TT of the hub device. 991 992 @retval EFI_SUCCESS Successfully configure the hub device's slot context. 993 994 **/ 995 EFI_STATUS 996 XhcConfigHubContext ( 997 IN USB_XHCI_INSTANCE *Xhc, 998 IN UINT8 SlotId, 999 IN UINT8 PortNum, 1000 IN UINT8 TTT, 1001 IN UINT8 MTT 1002 ); 1003 1004 1005 /** 1006 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd. 1007 1008 @param Xhc The XHCI Instance. 1009 @param SlotId The slot id to be configured. 1010 @param PortNum The total number of downstream port supported by the hub. 1011 @param TTT The TT think time of the hub device. 1012 @param MTT The multi-TT of the hub device. 1013 1014 @retval EFI_SUCCESS Successfully configure the hub device's slot context. 1015 1016 **/ 1017 EFI_STATUS 1018 XhcConfigHubContext64 ( 1019 IN USB_XHCI_INSTANCE *Xhc, 1020 IN UINT8 SlotId, 1021 IN UINT8 PortNum, 1022 IN UINT8 TTT, 1023 IN UINT8 MTT 1024 ); 1025 1026 1027 /** 1028 Configure all the device endpoints through XHCI's Configure_Endpoint cmd. 1029 1030 @param Xhc The XHCI Instance. 1031 @param SlotId The slot id to be configured. 1032 @param DeviceSpeed The device's speed. 1033 @param ConfigDesc The pointer to the usb device configuration descriptor. 1034 1035 @retval EFI_SUCCESS Successfully configure all the device endpoints. 1036 1037 **/ 1038 EFI_STATUS 1039 EFIAPI 1040 XhcSetConfigCmd ( 1041 IN USB_XHCI_INSTANCE *Xhc, 1042 IN UINT8 SlotId, 1043 IN UINT8 DeviceSpeed, 1044 IN USB_CONFIG_DESCRIPTOR *ConfigDesc 1045 ); 1046 1047 1048 /** 1049 Configure all the device endpoints through XHCI's Configure_Endpoint cmd. 1050 1051 @param Xhc The XHCI Instance. 1052 @param SlotId The slot id to be configured. 1053 @param DeviceSpeed The device's speed. 1054 @param ConfigDesc The pointer to the usb device configuration descriptor. 1055 1056 @retval EFI_SUCCESS Successfully configure all the device endpoints. 1057 1058 **/ 1059 EFI_STATUS 1060 EFIAPI 1061 XhcSetConfigCmd64 ( 1062 IN USB_XHCI_INSTANCE *Xhc, 1063 IN UINT8 SlotId, 1064 IN UINT8 DeviceSpeed, 1065 IN USB_CONFIG_DESCRIPTOR *ConfigDesc 1066 ); 1067 1068 /** 1069 Set interface through XHCI's Configure_Endpoint cmd. 1070 1071 @param Xhc The XHCI Instance. 1072 @param SlotId The slot id to be configured. 1073 @param DeviceSpeed The device's speed. 1074 @param ConfigDesc The pointer to the usb device configuration descriptor. 1075 @param Request USB device request to send. 1076 1077 @retval EFI_SUCCESS Successfully set interface. 1078 1079 **/ 1080 EFI_STATUS 1081 EFIAPI 1082 XhcSetInterface ( 1083 IN USB_XHCI_INSTANCE *Xhc, 1084 IN UINT8 SlotId, 1085 IN UINT8 DeviceSpeed, 1086 IN USB_CONFIG_DESCRIPTOR *ConfigDesc, 1087 IN EFI_USB_DEVICE_REQUEST *Request 1088 ); 1089 1090 /** 1091 Set interface through XHCI's Configure_Endpoint cmd. 1092 1093 @param Xhc The XHCI Instance. 1094 @param SlotId The slot id to be configured. 1095 @param DeviceSpeed The device's speed. 1096 @param ConfigDesc The pointer to the usb device configuration descriptor. 1097 @param Request USB device request to send. 1098 1099 @retval EFI_SUCCESS Successfully set interface. 1100 1101 **/ 1102 EFI_STATUS 1103 EFIAPI 1104 XhcSetInterface64 ( 1105 IN USB_XHCI_INSTANCE *Xhc, 1106 IN UINT8 SlotId, 1107 IN UINT8 DeviceSpeed, 1108 IN USB_CONFIG_DESCRIPTOR *ConfigDesc, 1109 IN EFI_USB_DEVICE_REQUEST *Request 1110 ); 1111 1112 /** 1113 Find out the actual device address according to the requested device address from UsbBus. 1114 1115 @param Xhc The XHCI Instance. 1116 @param BusDevAddr The requested device address by UsbBus upper driver. 1117 1118 @return The actual device address assigned to the device. 1119 1120 **/ 1121 UINT8 1122 EFIAPI 1123 XhcBusDevAddrToSlotId ( 1124 IN USB_XHCI_INSTANCE *Xhc, 1125 IN UINT8 BusDevAddr 1126 ); 1127 1128 /** 1129 Assign and initialize the device slot for a new device. 1130 1131 @param Xhc The XHCI Instance. 1132 @param ParentRouteChart The route string pointed to the parent device. 1133 @param ParentPort The port at which the device is located. 1134 @param RouteChart The route string pointed to the device. 1135 @param DeviceSpeed The device speed. 1136 1137 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it. 1138 1139 **/ 1140 EFI_STATUS 1141 EFIAPI 1142 XhcInitializeDeviceSlot ( 1143 IN USB_XHCI_INSTANCE *Xhc, 1144 IN USB_DEV_ROUTE ParentRouteChart, 1145 IN UINT16 ParentPort, 1146 IN USB_DEV_ROUTE RouteChart, 1147 IN UINT8 DeviceSpeed 1148 ); 1149 1150 /** 1151 Assign and initialize the device slot for a new device. 1152 1153 @param Xhc The XHCI Instance. 1154 @param ParentRouteChart The route string pointed to the parent device. 1155 @param ParentPort The port at which the device is located. 1156 @param RouteChart The route string pointed to the device. 1157 @param DeviceSpeed The device speed. 1158 1159 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it. 1160 1161 **/ 1162 EFI_STATUS 1163 EFIAPI 1164 XhcInitializeDeviceSlot64 ( 1165 IN USB_XHCI_INSTANCE *Xhc, 1166 IN USB_DEV_ROUTE ParentRouteChart, 1167 IN UINT16 ParentPort, 1168 IN USB_DEV_ROUTE RouteChart, 1169 IN UINT8 DeviceSpeed 1170 ); 1171 1172 /** 1173 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd. 1174 1175 @param Xhc The XHCI Instance. 1176 @param SlotId The slot id to be evaluated. 1177 @param MaxPacketSize The max packet size supported by the device control transfer. 1178 1179 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0. 1180 1181 **/ 1182 EFI_STATUS 1183 EFIAPI 1184 XhcEvaluateContext ( 1185 IN USB_XHCI_INSTANCE *Xhc, 1186 IN UINT8 SlotId, 1187 IN UINT32 MaxPacketSize 1188 ); 1189 1190 1191 /** 1192 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd. 1193 1194 @param Xhc The XHCI Instance. 1195 @param SlotId The slot id to be evaluated. 1196 @param MaxPacketSize The max packet size supported by the device control transfer. 1197 1198 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0. 1199 1200 **/ 1201 EFI_STATUS 1202 EFIAPI 1203 XhcEvaluateContext64 ( 1204 IN USB_XHCI_INSTANCE *Xhc, 1205 IN UINT8 SlotId, 1206 IN UINT32 MaxPacketSize 1207 ); 1208 1209 1210 /** 1211 Disable the specified device slot. 1212 1213 @param Xhc The XHCI Instance. 1214 @param SlotId The slot id to be disabled. 1215 1216 @retval EFI_SUCCESS Successfully disable the device slot. 1217 1218 **/ 1219 EFI_STATUS 1220 EFIAPI 1221 XhcDisableSlotCmd ( 1222 IN USB_XHCI_INSTANCE *Xhc, 1223 IN UINT8 SlotId 1224 ); 1225 1226 1227 /** 1228 Disable the specified device slot. 1229 1230 @param Xhc The XHCI Instance. 1231 @param SlotId The slot id to be disabled. 1232 1233 @retval EFI_SUCCESS Successfully disable the device slot. 1234 1235 **/ 1236 EFI_STATUS 1237 EFIAPI 1238 XhcDisableSlotCmd64 ( 1239 IN USB_XHCI_INSTANCE *Xhc, 1240 IN UINT8 SlotId 1241 ); 1242 1243 1244 /** 1245 Synchronize the specified transfer ring to update the enqueue and dequeue pointer. 1246 1247 @param Xhc The XHCI Instance. 1248 @param TrsRing The transfer ring to sync. 1249 1250 @retval EFI_SUCCESS The transfer ring is synchronized successfully. 1251 1252 **/ 1253 EFI_STATUS 1254 EFIAPI 1255 XhcSyncTrsRing ( 1256 IN USB_XHCI_INSTANCE *Xhc, 1257 TRANSFER_RING *TrsRing 1258 ); 1259 1260 /** 1261 Synchronize the specified event ring to update the enqueue and dequeue pointer. 1262 1263 @param Xhc The XHCI Instance. 1264 @param EvtRing The event ring to sync. 1265 1266 @retval EFI_SUCCESS The event ring is synchronized successfully. 1267 1268 **/ 1269 EFI_STATUS 1270 EFIAPI 1271 XhcSyncEventRing ( 1272 IN USB_XHCI_INSTANCE *Xhc, 1273 EVENT_RING *EvtRing 1274 ); 1275 1276 /** 1277 Check if there is a new generated event. 1278 1279 @param Xhc The XHCI Instance. 1280 @param EvtRing The event ring to check. 1281 @param NewEvtTrb The new event TRB found. 1282 1283 @retval EFI_SUCCESS Found a new event TRB at the event ring. 1284 @retval EFI_NOT_READY The event ring has no new event. 1285 1286 **/ 1287 EFI_STATUS 1288 EFIAPI 1289 XhcCheckNewEvent ( 1290 IN USB_XHCI_INSTANCE *Xhc, 1291 IN EVENT_RING *EvtRing, 1292 OUT TRB_TEMPLATE **NewEvtTrb 1293 ); 1294 1295 /** 1296 Create XHCI transfer ring. 1297 1298 @param Xhc The XHCI Instance. 1299 @param TrbNum The number of TRB in the ring. 1300 @param TransferRing The created transfer ring. 1301 1302 **/ 1303 VOID 1304 CreateTransferRing ( 1305 IN USB_XHCI_INSTANCE *Xhc, 1306 IN UINTN TrbNum, 1307 OUT TRANSFER_RING *TransferRing 1308 ); 1309 1310 /** 1311 Create XHCI event ring. 1312 1313 @param Xhc The XHCI Instance. 1314 @param EventRing The created event ring. 1315 1316 **/ 1317 VOID 1318 CreateEventRing ( 1319 IN USB_XHCI_INSTANCE *Xhc, 1320 OUT EVENT_RING *EventRing 1321 ); 1322 1323 /** 1324 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted 1325 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint 1326 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is 1327 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the 1328 Stopped to the Running state. 1329 1330 @param Xhc The XHCI Instance. 1331 @param Urb The urb which makes the endpoint halted. 1332 1333 @retval EFI_SUCCESS The recovery is successful. 1334 @retval Others Failed to recovery halted endpoint. 1335 1336 **/ 1337 EFI_STATUS 1338 EFIAPI 1339 XhcRecoverHaltedEndpoint ( 1340 IN USB_XHCI_INSTANCE *Xhc, 1341 IN URB *Urb 1342 ); 1343 1344 /** 1345 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer 1346 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to 1347 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running 1348 state. 1349 1350 @param Xhc The XHCI Instance. 1351 @param Urb The urb which doesn't get completed in a specified timeout range. 1352 1353 @retval EFI_SUCCESS The dequeuing of the TDs is successful. 1354 @retval Others Failed to stop the endpoint and dequeue the TDs. 1355 1356 **/ 1357 EFI_STATUS 1358 EFIAPI 1359 XhcDequeueTrbFromEndpoint ( 1360 IN USB_XHCI_INSTANCE *Xhc, 1361 IN URB *Urb 1362 ); 1363 1364 /** 1365 Stop endpoint through XHCI's Stop_Endpoint cmd. 1366 1367 @param Xhc The XHCI Instance. 1368 @param SlotId The slot id to be configured. 1369 @param Dci The device context index of endpoint. 1370 @param PendingUrb The pending URB to check completion status when stopping the end point. 1371 1372 @retval EFI_SUCCESS Stop endpoint successfully. 1373 @retval Others Failed to stop endpoint. 1374 1375 **/ 1376 EFI_STATUS 1377 EFIAPI 1378 XhcStopEndpoint ( 1379 IN USB_XHCI_INSTANCE *Xhc, 1380 IN UINT8 SlotId, 1381 IN UINT8 Dci, 1382 IN URB *PendingUrb OPTIONAL 1383 ); 1384 1385 /** 1386 Reset endpoint through XHCI's Reset_Endpoint cmd. 1387 1388 @param Xhc The XHCI Instance. 1389 @param SlotId The slot id to be configured. 1390 @param Dci The device context index of endpoint. 1391 1392 @retval EFI_SUCCESS Reset endpoint successfully. 1393 @retval Others Failed to reset endpoint. 1394 1395 **/ 1396 EFI_STATUS 1397 EFIAPI 1398 XhcResetEndpoint ( 1399 IN USB_XHCI_INSTANCE *Xhc, 1400 IN UINT8 SlotId, 1401 IN UINT8 Dci 1402 ); 1403 1404 /** 1405 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd. 1406 1407 @param Xhc The XHCI Instance. 1408 @param SlotId The slot id to be configured. 1409 @param Dci The device context index of endpoint. 1410 @param Urb The dequeue pointer of the transfer ring specified 1411 by the urb to be updated. 1412 1413 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds. 1414 @retval Others Failed to set transfer ring dequeue pointer. 1415 1416 **/ 1417 EFI_STATUS 1418 EFIAPI 1419 XhcSetTrDequeuePointer ( 1420 IN USB_XHCI_INSTANCE *Xhc, 1421 IN UINT8 SlotId, 1422 IN UINT8 Dci, 1423 IN URB *Urb 1424 ); 1425 1426 /** 1427 Create a new URB for a new transaction. 1428 1429 @param Xhc The XHCI Instance 1430 @param DevAddr The device address 1431 @param EpAddr Endpoint addrress 1432 @param DevSpeed The device speed 1433 @param MaxPacket The max packet length of the endpoint 1434 @param Type The transaction type 1435 @param Request The standard USB request for control transfer 1436 @param Data The user data to transfer 1437 @param DataLen The length of data buffer 1438 @param Callback The function to call when data is transferred 1439 @param Context The context to the callback 1440 1441 @return Created URB or NULL 1442 1443 **/ 1444 URB* 1445 XhcCreateUrb ( 1446 IN USB_XHCI_INSTANCE *Xhc, 1447 IN UINT8 DevAddr, 1448 IN UINT8 EpAddr, 1449 IN UINT8 DevSpeed, 1450 IN UINTN MaxPacket, 1451 IN UINTN Type, 1452 IN EFI_USB_DEVICE_REQUEST *Request, 1453 IN VOID *Data, 1454 IN UINTN DataLen, 1455 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback, 1456 IN VOID *Context 1457 ); 1458 1459 /** 1460 Free an allocated URB. 1461 1462 @param Xhc The XHCI device. 1463 @param Urb The URB to free. 1464 1465 **/ 1466 VOID 1467 XhcFreeUrb ( 1468 IN USB_XHCI_INSTANCE *Xhc, 1469 IN URB *Urb 1470 ); 1471 1472 /** 1473 Create a transfer TRB. 1474 1475 @param Xhc The XHCI Instance 1476 @param Urb The urb used to construct the transfer TRB. 1477 1478 @return Created TRB or NULL 1479 1480 **/ 1481 EFI_STATUS 1482 XhcCreateTransferTrb ( 1483 IN USB_XHCI_INSTANCE *Xhc, 1484 IN URB *Urb 1485 ); 1486 1487 #endif 1488