1 /*
2 * JMicron JMC2x0 series PCIe Ethernet gPXE Device Driver
3 *
4 * Copyright 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 * 02110-1301, USA.
19 *
20 */
21 FILE_LICENCE ( GPL2_OR_LATER );
22
23 #ifndef __JME_H_INCLUDED__
24 #define __JME_H_INCLUDED__
25
26 #define PCI_VENDOR_ID_JMICRON 0x197b
27 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
28 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
29
30 /*
31 * Extra PCI Configuration space interface
32 */
33 #define PCI_DCSR_MRRS 0x59
34 #define PCI_DCSR_MRRS_MASK 0x70
35
36 enum pci_dcsr_mrrs_vals {
37 MRRS_128B = 0x00,
38 MRRS_256B = 0x10,
39 MRRS_512B = 0x20,
40 MRRS_1024B = 0x30,
41 MRRS_2048B = 0x40,
42 MRRS_4096B = 0x50,
43 };
44
45 /*
46 * TX/RX Descriptors
47 *
48 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
49 */
50 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
51 #define TX_DESC_SIZE 16
52
53 struct txdesc {
54 union {
55 uint8_t all[16];
56 uint32_t dw[4];
57 struct {
58 /* DW0 */
59 uint16_t vlan;
60 uint8_t rsv1;
61 uint8_t flags;
62
63 /* DW1 */
64 uint16_t datalen;
65 uint16_t mss;
66
67 /* DW2 */
68 uint16_t pktsize;
69 uint16_t rsv2;
70
71 /* DW3 */
72 uint32_t bufaddr;
73 } desc1;
74 struct {
75 /* DW0 */
76 uint16_t rsv1;
77 uint8_t rsv2;
78 uint8_t flags;
79
80 /* DW1 */
81 uint16_t datalen;
82 uint16_t rsv3;
83
84 /* DW2 */
85 uint32_t bufaddrh;
86
87 /* DW3 */
88 uint32_t bufaddrl;
89 } desc2;
90 struct {
91 /* DW0 */
92 uint8_t ehdrsz;
93 uint8_t rsv1;
94 uint8_t rsv2;
95 uint8_t flags;
96
97 /* DW1 */
98 uint16_t trycnt;
99 uint16_t segcnt;
100
101 /* DW2 */
102 uint16_t pktsz;
103 uint16_t rsv3;
104
105 /* DW3 */
106 uint32_t bufaddrl;
107 } descwb;
108 };
109 };
110
111 enum jme_txdesc_flags_bits {
112 TXFLAG_OWN = 0x80,
113 TXFLAG_INT = 0x40,
114 TXFLAG_64BIT = 0x20,
115 TXFLAG_TCPCS = 0x10,
116 TXFLAG_UDPCS = 0x08,
117 TXFLAG_IPCS = 0x04,
118 TXFLAG_LSEN = 0x02,
119 TXFLAG_TAGON = 0x01,
120 };
121
122 #define TXDESC_MSS_SHIFT 2
123 enum jme_txwbdesc_flags_bits {
124 TXWBFLAG_OWN = 0x80,
125 TXWBFLAG_INT = 0x40,
126 TXWBFLAG_TMOUT = 0x20,
127 TXWBFLAG_TRYOUT = 0x10,
128 TXWBFLAG_COL = 0x08,
129
130 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
131 TXWBFLAG_TRYOUT |
132 TXWBFLAG_COL,
133 };
134
135 #define RX_DESC_SIZE 16
136 #define RX_BUF_DMA_ALIGN 8
137 #define RX_PREPAD_SIZE 10
138 #define ETH_CRC_LEN 2
139 #define RX_VLANHDR_LEN 2
140 #define RX_EXTRA_LEN (ETH_HLEN + \
141 ETH_CRC_LEN + \
142 RX_VLANHDR_LEN + \
143 RX_BUF_DMA_ALIGN)
144 #define FIXED_MTU 1500
145 #define RX_ALLOC_LEN (FIXED_MTU + RX_EXTRA_LEN)
146
147 struct rxdesc {
148 union {
149 uint8_t all[16];
150 uint32_t dw[4];
151 struct {
152 /* DW0 */
153 uint16_t rsv2;
154 uint8_t rsv1;
155 uint8_t flags;
156
157 /* DW1 */
158 uint16_t datalen;
159 uint16_t wbcpl;
160
161 /* DW2 */
162 uint32_t bufaddrh;
163
164 /* DW3 */
165 uint32_t bufaddrl;
166 } desc1;
167 struct {
168 /* DW0 */
169 uint16_t vlan;
170 uint16_t flags;
171
172 /* DW1 */
173 uint16_t framesize;
174 uint8_t errstat;
175 uint8_t desccnt;
176
177 /* DW2 */
178 uint32_t rsshash;
179
180 /* DW3 */
181 uint8_t hashfun;
182 uint8_t hashtype;
183 uint16_t resrv;
184 } descwb;
185 };
186 };
187
188 enum jme_rxdesc_flags_bits {
189 RXFLAG_OWN = 0x80,
190 RXFLAG_INT = 0x40,
191 RXFLAG_64BIT = 0x20,
192 };
193
194 enum jme_rxwbdesc_flags_bits {
195 RXWBFLAG_OWN = 0x8000,
196 RXWBFLAG_INT = 0x4000,
197 RXWBFLAG_MF = 0x2000,
198 RXWBFLAG_64BIT = 0x2000,
199 RXWBFLAG_TCPON = 0x1000,
200 RXWBFLAG_UDPON = 0x0800,
201 RXWBFLAG_IPCS = 0x0400,
202 RXWBFLAG_TCPCS = 0x0200,
203 RXWBFLAG_UDPCS = 0x0100,
204 RXWBFLAG_TAGON = 0x0080,
205 RXWBFLAG_IPV4 = 0x0040,
206 RXWBFLAG_IPV6 = 0x0020,
207 RXWBFLAG_PAUSE = 0x0010,
208 RXWBFLAG_MAGIC = 0x0008,
209 RXWBFLAG_WAKEUP = 0x0004,
210 RXWBFLAG_DEST = 0x0003,
211 RXWBFLAG_DEST_UNI = 0x0001,
212 RXWBFLAG_DEST_MUL = 0x0002,
213 RXWBFLAG_DEST_BRO = 0x0003,
214 };
215
216 enum jme_rxwbdesc_desccnt_mask {
217 RXWBDCNT_WBCPL = 0x80,
218 RXWBDCNT_DCNT = 0x7F,
219 };
220
221 enum jme_rxwbdesc_errstat_bits {
222 RXWBERR_LIMIT = 0x80,
223 RXWBERR_MIIER = 0x40,
224 RXWBERR_NIBON = 0x20,
225 RXWBERR_COLON = 0x10,
226 RXWBERR_ABORT = 0x08,
227 RXWBERR_SHORT = 0x04,
228 RXWBERR_OVERUN = 0x02,
229 RXWBERR_CRCERR = 0x01,
230 RXWBERR_ALLERR = 0xFF,
231 };
232
233 /*
234 * The structure holding buffer information and ring descriptors all together.
235 */
236 struct jme_ring {
237 void *desc; /* pointer to ring memory */
238 unsigned long dma; /* phys address for ring dma */
239
240 /* Buffer information corresponding to each descriptor */
241 struct io_buffer **bufinf;
242
243 int next_to_clean;
244 int next_to_fill;
245 int next_to_use;
246 int nr_free;
247 };
248
249 /*
250 * Jmac Adapter Private data
251 */
252 struct jme_adapter {
253 void *regs;
254 struct mii_if_info mii_if;
255 struct pci_device *pdev;
256 unsigned int fpgaver;
257 unsigned int chiprev;
258 uint32_t reg_ghc;
259 uint32_t reg_txcs;
260 uint32_t reg_rxcs;
261 uint32_t reg_rxmcs;
262 uint32_t phylink;
263 struct jme_ring rxring;
264 uint32_t rx_ring_size;
265 uint32_t rx_ring_mask;
266 struct jme_ring txring;
267 uint32_t tx_ring_size;
268 uint32_t tx_ring_mask;
269 };
270
271 /*
272 * I/O Resters
273 */
274 enum jme_iomap_regs_value {
275 JME_REGS_SIZE = 0x1000,
276 };
277
278 enum jme_iomap_offsets {
279 JME_MAC = 0x0000,
280 JME_PHY = 0x0400,
281 JME_MISC = 0x0800,
282 JME_RSS = 0x0C00,
283 };
284
285 enum jme_iomap_lens {
286 JME_MAC_LEN = 0x80,
287 JME_PHY_LEN = 0x58,
288 JME_MISC_LEN = 0x98,
289 JME_RSS_LEN = 0xFF,
290 };
291
292 enum jme_iomap_regs {
293 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
294 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
295 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
296 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
297 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
298 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
299 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
300 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
301
302 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
303 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
304 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
305 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
306 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
307 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
308 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
309 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
310 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
311 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
312 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
313 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
314
315 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
316 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
317 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
318
319
320 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
321 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
322 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
323 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
324
325
326 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
327 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
328 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
329 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
330 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
331 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
332 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
333 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
334 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
335 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
336 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
337 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
338 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
339 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
340 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
341 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
342 };
343
344 /*
345 * TX Control/Status Bits
346 */
347 enum jme_txcs_bits {
348 TXCS_QUEUE7S = 0x00008000,
349 TXCS_QUEUE6S = 0x00004000,
350 TXCS_QUEUE5S = 0x00002000,
351 TXCS_QUEUE4S = 0x00001000,
352 TXCS_QUEUE3S = 0x00000800,
353 TXCS_QUEUE2S = 0x00000400,
354 TXCS_QUEUE1S = 0x00000200,
355 TXCS_QUEUE0S = 0x00000100,
356 TXCS_FIFOTH = 0x000000C0,
357 TXCS_DMASIZE = 0x00000030,
358 TXCS_BURST = 0x00000004,
359 TXCS_ENABLE = 0x00000001,
360 };
361
362 enum jme_txcs_value {
363 TXCS_FIFOTH_16QW = 0x000000C0,
364 TXCS_FIFOTH_12QW = 0x00000080,
365 TXCS_FIFOTH_8QW = 0x00000040,
366 TXCS_FIFOTH_4QW = 0x00000000,
367
368 TXCS_DMASIZE_64B = 0x00000000,
369 TXCS_DMASIZE_128B = 0x00000010,
370 TXCS_DMASIZE_256B = 0x00000020,
371 TXCS_DMASIZE_512B = 0x00000030,
372
373 TXCS_SELECT_QUEUE0 = 0x00000000,
374 TXCS_SELECT_QUEUE1 = 0x00010000,
375 TXCS_SELECT_QUEUE2 = 0x00020000,
376 TXCS_SELECT_QUEUE3 = 0x00030000,
377 TXCS_SELECT_QUEUE4 = 0x00040000,
378 TXCS_SELECT_QUEUE5 = 0x00050000,
379 TXCS_SELECT_QUEUE6 = 0x00060000,
380 TXCS_SELECT_QUEUE7 = 0x00070000,
381
382 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
383 TXCS_BURST,
384 };
385
386 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
387
388 /*
389 * TX MAC Control/Status Bits
390 */
391 enum jme_txmcs_bit_masks {
392 TXMCS_IFG2 = 0xC0000000,
393 TXMCS_IFG1 = 0x30000000,
394 TXMCS_TTHOLD = 0x00000300,
395 TXMCS_FBURST = 0x00000080,
396 TXMCS_CARRIEREXT = 0x00000040,
397 TXMCS_DEFER = 0x00000020,
398 TXMCS_BACKOFF = 0x00000010,
399 TXMCS_CARRIERSENSE = 0x00000008,
400 TXMCS_COLLISION = 0x00000004,
401 TXMCS_CRC = 0x00000002,
402 TXMCS_PADDING = 0x00000001,
403 };
404
405 enum jme_txmcs_values {
406 TXMCS_IFG2_6_4 = 0x00000000,
407 TXMCS_IFG2_8_5 = 0x40000000,
408 TXMCS_IFG2_10_6 = 0x80000000,
409 TXMCS_IFG2_12_7 = 0xC0000000,
410
411 TXMCS_IFG1_8_4 = 0x00000000,
412 TXMCS_IFG1_12_6 = 0x10000000,
413 TXMCS_IFG1_16_8 = 0x20000000,
414 TXMCS_IFG1_20_10 = 0x30000000,
415
416 TXMCS_TTHOLD_1_8 = 0x00000000,
417 TXMCS_TTHOLD_1_4 = 0x00000100,
418 TXMCS_TTHOLD_1_2 = 0x00000200,
419 TXMCS_TTHOLD_FULL = 0x00000300,
420
421 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
422 TXMCS_IFG1_16_8 |
423 TXMCS_TTHOLD_FULL |
424 TXMCS_DEFER |
425 TXMCS_CRC |
426 TXMCS_PADDING,
427 };
428
429 enum jme_txpfc_bits_masks {
430 TXPFC_VLAN_TAG = 0xFFFF0000,
431 TXPFC_VLAN_EN = 0x00008000,
432 TXPFC_PF_EN = 0x00000001,
433 };
434
435 enum jme_txtrhd_bits_masks {
436 TXTRHD_TXPEN = 0x80000000,
437 TXTRHD_TXP = 0x7FFFFF00,
438 TXTRHD_TXREN = 0x00000080,
439 TXTRHD_TXRL = 0x0000007F,
440 };
441
442 enum jme_txtrhd_shifts {
443 TXTRHD_TXP_SHIFT = 8,
444 TXTRHD_TXRL_SHIFT = 0,
445 };
446
447 /*
448 * RX Control/Status Bits
449 */
450 enum jme_rxcs_bit_masks {
451 /* FIFO full threshold for transmitting Tx Pause Packet */
452 RXCS_FIFOTHTP = 0x30000000,
453 /* FIFO threshold for processing next packet */
454 RXCS_FIFOTHNP = 0x0C000000,
455 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
456 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
457 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
458 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
459 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
460 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
461 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
462 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
463 RXCS_QST = 0x00000004, /* Receive queue start */
464 RXCS_SUSPEND = 0x00000002,
465 RXCS_ENABLE = 0x00000001,
466 };
467
468 enum jme_rxcs_values {
469 RXCS_FIFOTHTP_16T = 0x00000000,
470 RXCS_FIFOTHTP_32T = 0x10000000,
471 RXCS_FIFOTHTP_64T = 0x20000000,
472 RXCS_FIFOTHTP_128T = 0x30000000,
473
474 RXCS_FIFOTHNP_16QW = 0x00000000,
475 RXCS_FIFOTHNP_32QW = 0x04000000,
476 RXCS_FIFOTHNP_64QW = 0x08000000,
477 RXCS_FIFOTHNP_128QW = 0x0C000000,
478
479 RXCS_DMAREQSZ_16B = 0x00000000,
480 RXCS_DMAREQSZ_32B = 0x01000000,
481 RXCS_DMAREQSZ_64B = 0x02000000,
482 RXCS_DMAREQSZ_128B = 0x03000000,
483
484 RXCS_QUEUESEL_Q0 = 0x00000000,
485 RXCS_QUEUESEL_Q1 = 0x00010000,
486 RXCS_QUEUESEL_Q2 = 0x00020000,
487 RXCS_QUEUESEL_Q3 = 0x00030000,
488
489 RXCS_RETRYGAP_256ns = 0x00000000,
490 RXCS_RETRYGAP_512ns = 0x00001000,
491 RXCS_RETRYGAP_1024ns = 0x00002000,
492 RXCS_RETRYGAP_2048ns = 0x00003000,
493 RXCS_RETRYGAP_4096ns = 0x00004000,
494 RXCS_RETRYGAP_8192ns = 0x00005000,
495 RXCS_RETRYGAP_16384ns = 0x00006000,
496 RXCS_RETRYGAP_32768ns = 0x00007000,
497
498 RXCS_RETRYCNT_0 = 0x00000000,
499 RXCS_RETRYCNT_4 = 0x00000100,
500 RXCS_RETRYCNT_8 = 0x00000200,
501 RXCS_RETRYCNT_12 = 0x00000300,
502 RXCS_RETRYCNT_16 = 0x00000400,
503 RXCS_RETRYCNT_20 = 0x00000500,
504 RXCS_RETRYCNT_24 = 0x00000600,
505 RXCS_RETRYCNT_28 = 0x00000700,
506 RXCS_RETRYCNT_32 = 0x00000800,
507 RXCS_RETRYCNT_36 = 0x00000900,
508 RXCS_RETRYCNT_40 = 0x00000A00,
509 RXCS_RETRYCNT_44 = 0x00000B00,
510 RXCS_RETRYCNT_48 = 0x00000C00,
511 RXCS_RETRYCNT_52 = 0x00000D00,
512 RXCS_RETRYCNT_56 = 0x00000E00,
513 RXCS_RETRYCNT_60 = 0x00000F00,
514
515 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
516 RXCS_FIFOTHNP_128QW |
517 RXCS_DMAREQSZ_128B |
518 RXCS_RETRYGAP_256ns |
519 RXCS_RETRYCNT_32,
520 };
521
522 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
523
524 /*
525 * RX MAC Control/Status Bits
526 */
527 enum jme_rxmcs_bits {
528 RXMCS_ALLFRAME = 0x00000800,
529 RXMCS_BRDFRAME = 0x00000400,
530 RXMCS_MULFRAME = 0x00000200,
531 RXMCS_UNIFRAME = 0x00000100,
532 RXMCS_ALLMULFRAME = 0x00000080,
533 RXMCS_MULFILTERED = 0x00000040,
534 RXMCS_RXCOLLDEC = 0x00000020,
535 RXMCS_FLOWCTRL = 0x00000008,
536 RXMCS_VTAGRM = 0x00000004,
537 RXMCS_PREPAD = 0x00000002,
538 RXMCS_CHECKSUM = 0x00000001,
539
540 RXMCS_DEFAULT = RXMCS_VTAGRM |
541 RXMCS_FLOWCTRL |
542 RXMCS_CHECKSUM,
543 };
544
545 /*
546 * Wakeup Frame setup interface registers
547 */
548 #define WAKEUP_FRAME_NR 8
549 #define WAKEUP_FRAME_MASK_DWNR 4
550
551 enum jme_wfoi_bit_masks {
552 WFOI_MASK_SEL = 0x00000070,
553 WFOI_CRC_SEL = 0x00000008,
554 WFOI_FRAME_SEL = 0x00000007,
555 };
556
557 enum jme_wfoi_shifts {
558 WFOI_MASK_SHIFT = 4,
559 };
560
561 /*
562 * SMI Related definitions
563 */
564 enum jme_smi_bit_mask {
565 SMI_DATA_MASK = 0xFFFF0000,
566 SMI_REG_ADDR_MASK = 0x0000F800,
567 SMI_PHY_ADDR_MASK = 0x000007C0,
568 SMI_OP_WRITE = 0x00000020,
569 /* Set to 1, after req done it'll be cleared to 0 */
570 SMI_OP_REQ = 0x00000010,
571 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
572 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
573 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
574 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
575 };
576
577 enum jme_smi_bit_shift {
578 SMI_DATA_SHIFT = 16,
579 SMI_REG_ADDR_SHIFT = 11,
580 SMI_PHY_ADDR_SHIFT = 6,
581 };
582
smi_reg_addr(int x)583 static inline uint32_t smi_reg_addr(int x)
584 {
585 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
586 }
587
smi_phy_addr(int x)588 static inline uint32_t smi_phy_addr(int x)
589 {
590 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
591 }
592
593 #define JME_PHY_TIMEOUT 100 /* 100 msec */
594 #define JME_PHY_REG_NR 32
595
596 /*
597 * Global Host Control
598 */
599 enum jme_ghc_bit_mask {
600 GHC_SWRST = 0x40000000,
601 GHC_DPX = 0x00000040,
602 GHC_SPEED = 0x00000030,
603 GHC_LINK_POLL = 0x00000001,
604 };
605
606 enum jme_ghc_speed_val {
607 GHC_SPEED_10M = 0x00000010,
608 GHC_SPEED_100M = 0x00000020,
609 GHC_SPEED_1000M = 0x00000030,
610 };
611
612 enum jme_ghc_to_clk {
613 GHC_TO_CLK_OFF = 0x00000000,
614 GHC_TO_CLK_GPHY = 0x00400000,
615 GHC_TO_CLK_PCIE = 0x00800000,
616 GHC_TO_CLK_INVALID = 0x00C00000,
617 };
618
619 enum jme_ghc_txmac_clk {
620 GHC_TXMAC_CLK_OFF = 0x00000000,
621 GHC_TXMAC_CLK_GPHY = 0x00100000,
622 GHC_TXMAC_CLK_PCIE = 0x00200000,
623 GHC_TXMAC_CLK_INVALID = 0x00300000,
624 };
625
626 /*
627 * Power management control and status register
628 */
629 enum jme_pmcs_bit_masks {
630 PMCS_WF7DET = 0x80000000,
631 PMCS_WF6DET = 0x40000000,
632 PMCS_WF5DET = 0x20000000,
633 PMCS_WF4DET = 0x10000000,
634 PMCS_WF3DET = 0x08000000,
635 PMCS_WF2DET = 0x04000000,
636 PMCS_WF1DET = 0x02000000,
637 PMCS_WF0DET = 0x01000000,
638 PMCS_LFDET = 0x00040000,
639 PMCS_LRDET = 0x00020000,
640 PMCS_MFDET = 0x00010000,
641 PMCS_WF7EN = 0x00008000,
642 PMCS_WF6EN = 0x00004000,
643 PMCS_WF5EN = 0x00002000,
644 PMCS_WF4EN = 0x00001000,
645 PMCS_WF3EN = 0x00000800,
646 PMCS_WF2EN = 0x00000400,
647 PMCS_WF1EN = 0x00000200,
648 PMCS_WF0EN = 0x00000100,
649 PMCS_LFEN = 0x00000004,
650 PMCS_LREN = 0x00000002,
651 PMCS_MFEN = 0x00000001,
652 };
653
654 /*
655 * Giga PHY Status Registers
656 */
657 enum jme_phy_link_bit_mask {
658 PHY_LINK_SPEED_MASK = 0x0000C000,
659 PHY_LINK_DUPLEX = 0x00002000,
660 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
661 PHY_LINK_UP = 0x00000400,
662 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
663 PHY_LINK_MDI_STAT = 0x00000040,
664 };
665
666 enum jme_phy_link_speed_val {
667 PHY_LINK_SPEED_10M = 0x00000000,
668 PHY_LINK_SPEED_100M = 0x00004000,
669 PHY_LINK_SPEED_1000M = 0x00008000,
670 };
671
672 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
673
674 /*
675 * SMB Control and Status
676 */
677 enum jme_smbcsr_bit_mask {
678 SMBCSR_CNACK = 0x00020000,
679 SMBCSR_RELOAD = 0x00010000,
680 SMBCSR_EEPROMD = 0x00000020,
681 SMBCSR_INITDONE = 0x00000010,
682 SMBCSR_BUSY = 0x0000000F,
683 };
684
685 enum jme_smbintf_bit_mask {
686 SMBINTF_HWDATR = 0xFF000000,
687 SMBINTF_HWDATW = 0x00FF0000,
688 SMBINTF_HWADDR = 0x0000FF00,
689 SMBINTF_HWRWN = 0x00000020,
690 SMBINTF_HWCMD = 0x00000010,
691 SMBINTF_FASTM = 0x00000008,
692 SMBINTF_GPIOSCL = 0x00000004,
693 SMBINTF_GPIOSDA = 0x00000002,
694 SMBINTF_GPIOEN = 0x00000001,
695 };
696
697 enum jme_smbintf_vals {
698 SMBINTF_HWRWN_READ = 0x00000020,
699 SMBINTF_HWRWN_WRITE = 0x00000000,
700 };
701
702 enum jme_smbintf_shifts {
703 SMBINTF_HWDATR_SHIFT = 24,
704 SMBINTF_HWDATW_SHIFT = 16,
705 SMBINTF_HWADDR_SHIFT = 8,
706 };
707
708 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
709 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
710 #define JME_SMB_LEN 256
711 #define JME_EEPROM_MAGIC 0x250
712
713 /*
714 * Timer Control/Status Register
715 */
716 enum jme_tmcsr_bit_masks {
717 TMCSR_SWIT = 0x80000000,
718 TMCSR_EN = 0x01000000,
719 TMCSR_CNT = 0x00FFFFFF,
720 };
721
722 /*
723 * General Purpose REG-0
724 */
725 enum jme_gpreg0_masks {
726 GPREG0_DISSH = 0xFF000000,
727 GPREG0_PCIRLMT = 0x00300000,
728 GPREG0_PCCNOMUTCLR = 0x00040000,
729 GPREG0_LNKINTPOLL = 0x00001000,
730 GPREG0_PCCTMR = 0x00000300,
731 GPREG0_PHYADDR = 0x0000001F,
732 };
733
734 enum jme_gpreg0_vals {
735 GPREG0_DISSH_DW7 = 0x80000000,
736 GPREG0_DISSH_DW6 = 0x40000000,
737 GPREG0_DISSH_DW5 = 0x20000000,
738 GPREG0_DISSH_DW4 = 0x10000000,
739 GPREG0_DISSH_DW3 = 0x08000000,
740 GPREG0_DISSH_DW2 = 0x04000000,
741 GPREG0_DISSH_DW1 = 0x02000000,
742 GPREG0_DISSH_DW0 = 0x01000000,
743 GPREG0_DISSH_ALL = 0xFF000000,
744
745 GPREG0_PCIRLMT_8 = 0x00000000,
746 GPREG0_PCIRLMT_6 = 0x00100000,
747 GPREG0_PCIRLMT_5 = 0x00200000,
748 GPREG0_PCIRLMT_4 = 0x00300000,
749
750 GPREG0_PCCTMR_16ns = 0x00000000,
751 GPREG0_PCCTMR_256ns = 0x00000100,
752 GPREG0_PCCTMR_1us = 0x00000200,
753 GPREG0_PCCTMR_1ms = 0x00000300,
754
755 GPREG0_PHYADDR_1 = 0x00000001,
756
757 GPREG0_DEFAULT = GPREG0_DISSH_ALL |
758 GPREG0_PCIRLMT_4 |
759 GPREG0_PCCTMR_1us |
760 GPREG0_PHYADDR_1,
761 };
762
763 /*
764 * General Purpose REG-1
765 * Note: All theses bits defined here are for
766 * Chip mode revision 0x11 only
767 */
768 enum jme_gpreg1_masks {
769 GPREG1_INTRDELAYUNIT = 0x00000018,
770 GPREG1_INTRDELAYENABLE = 0x00000007,
771 };
772
773 enum jme_gpreg1_vals {
774 GPREG1_RSSPATCH = 0x00000040,
775 GPREG1_HALFMODEPATCH = 0x00000020,
776
777 GPREG1_INTDLYUNIT_16NS = 0x00000000,
778 GPREG1_INTDLYUNIT_256NS = 0x00000008,
779 GPREG1_INTDLYUNIT_1US = 0x00000010,
780 GPREG1_INTDLYUNIT_16US = 0x00000018,
781
782 GPREG1_INTDLYEN_1U = 0x00000001,
783 GPREG1_INTDLYEN_2U = 0x00000002,
784 GPREG1_INTDLYEN_3U = 0x00000003,
785 GPREG1_INTDLYEN_4U = 0x00000004,
786 GPREG1_INTDLYEN_5U = 0x00000005,
787 GPREG1_INTDLYEN_6U = 0x00000006,
788 GPREG1_INTDLYEN_7U = 0x00000007,
789
790 GPREG1_DEFAULT = 0x00000000,
791 };
792
793 /*
794 * Interrupt Status Bits
795 */
796 enum jme_interrupt_bits {
797 INTR_SWINTR = 0x80000000,
798 INTR_TMINTR = 0x40000000,
799 INTR_LINKCH = 0x20000000,
800 INTR_PAUSERCV = 0x10000000,
801 INTR_MAGICRCV = 0x08000000,
802 INTR_WAKERCV = 0x04000000,
803 INTR_PCCRX0TO = 0x02000000,
804 INTR_PCCRX1TO = 0x01000000,
805 INTR_PCCRX2TO = 0x00800000,
806 INTR_PCCRX3TO = 0x00400000,
807 INTR_PCCTXTO = 0x00200000,
808 INTR_PCCRX0 = 0x00100000,
809 INTR_PCCRX1 = 0x00080000,
810 INTR_PCCRX2 = 0x00040000,
811 INTR_PCCRX3 = 0x00020000,
812 INTR_PCCTX = 0x00010000,
813 INTR_RX3EMP = 0x00008000,
814 INTR_RX2EMP = 0x00004000,
815 INTR_RX1EMP = 0x00002000,
816 INTR_RX0EMP = 0x00001000,
817 INTR_RX3 = 0x00000800,
818 INTR_RX2 = 0x00000400,
819 INTR_RX1 = 0x00000200,
820 INTR_RX0 = 0x00000100,
821 INTR_TX7 = 0x00000080,
822 INTR_TX6 = 0x00000040,
823 INTR_TX5 = 0x00000020,
824 INTR_TX4 = 0x00000010,
825 INTR_TX3 = 0x00000008,
826 INTR_TX2 = 0x00000004,
827 INTR_TX1 = 0x00000002,
828 INTR_TX0 = 0x00000001,
829 };
830
831 static const uint32_t INTR_ENABLE = INTR_LINKCH |
832 INTR_RX0EMP |
833 INTR_RX0 |
834 INTR_TX0;
835
836 /*
837 * PCC Control Registers
838 */
839 enum jme_pccrx_masks {
840 PCCRXTO_MASK = 0xFFFF0000,
841 PCCRX_MASK = 0x0000FF00,
842 };
843
844 enum jme_pcctx_masks {
845 PCCTXTO_MASK = 0xFFFF0000,
846 PCCTX_MASK = 0x0000FF00,
847 PCCTX_QS_MASK = 0x000000FF,
848 };
849
850 enum jme_pccrx_shifts {
851 PCCRXTO_SHIFT = 16,
852 PCCRX_SHIFT = 8,
853 };
854
855 enum jme_pcctx_shifts {
856 PCCTXTO_SHIFT = 16,
857 PCCTX_SHIFT = 8,
858 };
859
860 enum jme_pcctx_bits {
861 PCCTXQ0_EN = 0x00000001,
862 PCCTXQ1_EN = 0x00000002,
863 PCCTXQ2_EN = 0x00000004,
864 PCCTXQ3_EN = 0x00000008,
865 PCCTXQ4_EN = 0x00000010,
866 PCCTXQ5_EN = 0x00000020,
867 PCCTXQ6_EN = 0x00000040,
868 PCCTXQ7_EN = 0x00000080,
869 };
870
871 /*
872 * Chip Mode Register
873 */
874 enum jme_chipmode_bit_masks {
875 CM_FPGAVER_MASK = 0xFFFF0000,
876 CM_CHIPREV_MASK = 0x0000FF00,
877 CM_CHIPMODE_MASK = 0x0000000F,
878 };
879
880 enum jme_chipmode_shifts {
881 CM_FPGAVER_SHIFT = 16,
882 CM_CHIPREV_SHIFT = 8,
883 };
884
885 /*
886 * Workaround
887 */
is_buggy250(unsigned short device,unsigned int chiprev)888 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
889 {
890 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
891 }
892
893 /*
894 * Read/Write I/O Registers
895 */
jread32(struct jme_adapter * jme,uint32_t reg)896 static inline uint32_t jread32(struct jme_adapter *jme, uint32_t reg)
897 {
898 return readl(jme->regs + reg);
899 }
900
jwrite32(struct jme_adapter * jme,uint32_t reg,uint32_t val)901 static inline void jwrite32(struct jme_adapter *jme, uint32_t reg, uint32_t val)
902 {
903 writel(val, jme->regs + reg);
904 }
905
jwrite32f(struct jme_adapter * jme,uint32_t reg,uint32_t val)906 static void jwrite32f(struct jme_adapter *jme, uint32_t reg, uint32_t val)
907 {
908 /*
909 * Read after write should cause flush
910 */
911 writel(val, jme->regs + reg);
912 readl(jme->regs + reg);
913 }
914
915 #endif
916