1 /**************************************************************************
2 *
3 * GPL common net driver for Solarflare network cards
4 *
5 * Written by Michael Brown <mbrown@fensystems.co.uk>
6 *
7 * Copyright Fen Systems Ltd. 2005
8 * Copyright Level 5 Networks Inc. 2005
9 * Copyright Solarflare Communications Inc. 2013-2017
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or any later version.
15 *
16 * You can also choose to distribute this program under the terms of
17 * the Unmodified Binary Distribution Licence (as given in the file
18 * COPYING.UBDL), provided that you have satisfied its requirements.
19 *
20 ***************************************************************************/
21 #ifndef EFX_COMMON_H
22 #define EFX_COMMON_H
23
24 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
25
26 #define __packed __attribute__((__packed__))
27 #define __force /*nothing*/
28
29 typedef uint16_t __le16;
30 typedef uint32_t __le32;
31 typedef uint64_t __le64;
32
33 #define BUILD_BUG_ON_ZERO(e) (sizeof(struct{int: -!!(e); }))
34 #define BUILD_BUG_ON(e) ((void)BUILD_BUG_ON_ZERO(e))
35
36 #include <stdbool.h>
37 #include <ipxe/io.h>
38 #include <ipxe/netdevice.h>
39 #include "efx_bitfield.h"
40 #include "mcdi.h"
41
42 #ifndef ARRAY_SIZE
43 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
44 #endif
45
46 /**************************************************************************
47 *
48 * Hardware data structures and sizing
49 *
50 ***************************************************************************/
51 typedef efx_qword_t efx_rx_desc_t;
52 typedef efx_qword_t efx_tx_desc_t;
53 typedef efx_qword_t efx_event_t;
54
55 #define EFX_BUF_ALIGN 4096
56 #define EFX_RXD_SIZE 512
57 #define EFX_RXD_MASK (EFX_RXD_SIZE - 1)
58 #define EFX_TXD_SIZE 512
59 #define EFX_TXD_MASK (EFX_TXD_SIZE - 1)
60 #define EFX_EVQ_SIZE 512
61 #define EFX_EVQ_MASK (EFX_EVQ_SIZE - 1)
62
63 /* There is space for 512 rx descriptors available. This number can be
64 * anything between 1 and 512 in powers of 2. This value will affect the
65 * network performance. During a test we were able to push 239 descriptors
66 * before we ran out of space.
67 */
68 #define EFX_NUM_RX_DESC 64
69 #define EFX_NUM_RX_DESC_MASK (EFX_NUM_RX_DESC - 1)
70
71 /* The packet size is usually 1500 bytes hence we choose 1600 as the buf size,
72 * which is (1500+metadata)
73 */
74 #define EFX_RX_BUF_SIZE 1600
75
76 /* Settings for the state field in efx_nic.
77 */
78 #define EFX_STATE_POLLING 1
79
80 typedef unsigned long long dma_addr_t;
81
82 /** A buffer table allocation backing a tx dma, rx dma or eventq */
83 struct efx_special_buffer {
84 dma_addr_t dma_addr;
85 int id;
86 };
87
88 /** A transmit queue */
89 struct efx_tx_queue {
90 /* The hardware ring */
91 efx_tx_desc_t *ring;
92
93 /* The software ring storing io_buffers. */
94 struct io_buffer *buf[EFX_TXD_SIZE];
95
96 /* The buffer table reservation pushed to hardware */
97 struct efx_special_buffer entry;
98
99 /* Software descriptor write ptr */
100 unsigned int write_ptr;
101
102 /* Hardware descriptor read ptr */
103 unsigned int read_ptr;
104 };
105
106 /** A receive queue */
107 struct efx_rx_queue {
108 /* The hardware ring */
109 efx_rx_desc_t *ring;
110
111 /* The software ring storing io_buffers */
112 struct io_buffer *buf[EFX_NUM_RX_DESC];
113
114 /* The buffer table reservation pushed to hardware */
115 struct efx_special_buffer entry;
116
117 /* Descriptor write ptr, into both the hardware and software rings */
118 unsigned int write_ptr;
119
120 /* Hardware completion ptr */
121 unsigned int read_ptr;
122
123 /* The value of RX_CONT in the previous RX event */
124 unsigned int rx_cont_prev;
125 };
126
127 /** An event queue */
128 struct efx_ev_queue {
129 /* The hardware ring to push to hardware.
130 * Must be the first entry in the structure.
131 */
132 efx_event_t *ring;
133
134 /* The buffer table reservation pushed to hardware */
135 struct efx_special_buffer entry;
136
137 /* Pointers into the ring */
138 unsigned int read_ptr;
139 };
140
141 /* Hardware revisions */
142 enum efx_revision {
143 EFX_HUNTINGTON,
144 };
145
146 /** Hardware access */
147 struct efx_nic {
148 struct net_device *netdev;
149 enum efx_revision revision;
150 const struct efx_nic_type *type;
151
152 int port;
153 u32 state;
154
155 /** Memory and IO base */
156 void *membase;
157 unsigned long mmio_start;
158 unsigned long mmio_len;
159
160 /* Buffer table allocation head */
161 int buffer_head;
162
163 /* Queues */
164 struct efx_rx_queue rxq;
165 struct efx_tx_queue txq;
166 struct efx_ev_queue evq;
167
168 unsigned int rx_prefix_size;
169
170 /** INT_REG_KER */
171 int int_en;
172 efx_oword_t int_ker __aligned;
173
174 /* Set to true if firmware supports the workaround for bug35388 */
175 bool workaround_35388;
176
177 };
178
179
180 /** Efx device type definition */
181 struct efx_nic_type {
182 int (*mcdi_rpc)(struct efx_nic *efx, unsigned int cmd,
183 const efx_dword_t *inbuf, size_t inlen,
184 efx_dword_t *outbuf, size_t outlen,
185 size_t *outlen_actual, bool quiet);
186 };
187
188 extern const struct efx_nic_type hunt_nic_type;
189
190 #define EFX_MAC_FRAME_LEN(_mtu) \
191 (((_mtu) \
192 + /* EtherII already included */ \
193 + 4 /* FCS */ \
194 /* No VLAN supported */ \
195 + 16 /* bug16772 */ \
196 + 7) & ~7)
197
198 /*******************************************************************************
199 *
200 *
201 * Hardware API
202 *
203 *
204 ******************************************************************************/
_efx_writel(struct efx_nic * efx,uint32_t value,unsigned int reg)205 static inline void _efx_writel(struct efx_nic *efx, uint32_t value,
206 unsigned int reg)
207 {
208 writel((value), (efx)->membase + (reg));
209 }
210
_efx_readl(struct efx_nic * efx,unsigned int reg)211 static inline uint32_t _efx_readl(struct efx_nic *efx, unsigned int reg)
212 {
213 return readl((efx)->membase + (reg));
214 }
215
216 #define efx_writel_table(efx, value, index, reg) \
217 efx_writel(efx, value, (reg) + ((index) * reg##_STEP))
218
219 #define efx_writel_page(efx, value, index, reg) \
220 efx_writel(efx, value, (reg) + ((index) * 0x2000))
221
222 /* Hardware access */
223 extern void efx_writel(struct efx_nic *efx, efx_dword_t *value,
224 unsigned int reg);
225 extern void efx_readl(struct efx_nic *efx, efx_dword_t *value,
226 unsigned int reg);
227
228 /* Initialisation */
229 extern void efx_probe(struct net_device *netdev, enum efx_revision rev);
230 extern void efx_remove(struct net_device *netdev);
231
232 #endif /* EFX_COMMON_H */
233