1 /* 2 * Copyright (C) 2006 Atmel Corporation 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 #ifndef __ASM_AVR32_PTRACE_H 23 #define __ASM_AVR32_PTRACE_H 24 25 /* 26 * Status Register bits 27 */ 28 #define SR_H 0x40000000 29 #define SR_R 0x20000000 30 #define SR_J 0x10000000 31 #define SR_DM 0x08000000 32 #define SR_D 0x04000000 33 #define MODE_NMI 0x01c00000 34 #define MODE_EXCEPTION 0x01800000 35 #define MODE_INT3 0x01400000 36 #define MODE_INT2 0x01000000 37 #define MODE_INT1 0x00c00000 38 #define MODE_INT0 0x00800000 39 #define MODE_SUPERVISOR 0x00400000 40 #define MODE_USER 0x00000000 41 #define MODE_MASK 0x01c00000 42 #define SR_EM 0x00200000 43 #define SR_I3M 0x00100000 44 #define SR_I2M 0x00080000 45 #define SR_I1M 0x00040000 46 #define SR_I0M 0x00020000 47 #define SR_GM 0x00010000 48 49 #define MODE_SHIFT 22 50 #define SR_EM_BIT 21 51 #define SR_I3M_BIT 20 52 #define SR_I2M_BIT 19 53 #define SR_I1M_BIT 18 54 #define SR_I0M_BIT 17 55 #define SR_GM_BIT 16 56 57 /* The user-visible part */ 58 #define SR_Q 0x00000010 59 #define SR_V 0x00000008 60 #define SR_N 0x00000004 61 #define SR_Z 0x00000002 62 #define SR_C 0x00000001 63 64 /* 65 * The order is defined by the stdsp instruction. r0 is stored first, so it 66 * gets the highest address. 67 * 68 * Registers 0-12 are general-purpose registers (r12 is normally used for 69 * the function return value). 70 * Register 13 is the stack pointer 71 * Register 14 is the link register 72 * Register 15 is the program counter 73 */ 74 #define FRAME_SIZE_FULL 72 75 #define REG_R12_ORIG 68 76 #define REG_R0 64 77 #define REG_R1 60 78 #define REG_R2 56 79 #define REG_R3 52 80 #define REG_R4 48 81 #define REG_R5 44 82 #define REG_R6 40 83 #define REG_R7 36 84 #define REG_R8 32 85 #define REG_R9 28 86 #define REG_R10 34 87 #define REG_R11 20 88 #define REG_R12 16 89 #define REG_SP 12 90 #define REG_LR 8 91 92 #define FRAME_SIZE_MIN 8 93 #define REG_PC 4 94 #define REG_SR 0 95 96 #ifndef __ASSEMBLY__ 97 struct pt_regs { 98 /* These are always saved */ 99 unsigned long sr; 100 unsigned long pc; 101 102 /* These are sometimes saved */ 103 unsigned long lr; 104 unsigned long sp; 105 unsigned long r12; 106 unsigned long r11; 107 unsigned long r10; 108 unsigned long r9; 109 unsigned long r8; 110 unsigned long r7; 111 unsigned long r6; 112 unsigned long r5; 113 unsigned long r4; 114 unsigned long r3; 115 unsigned long r2; 116 unsigned long r1; 117 unsigned long r0; 118 119 /* Only saved on system call */ 120 unsigned long r12_orig; 121 }; 122 123 #ifdef __KERNEL__ 124 # define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER) 125 # define instruction_pointer(regs) ((regs)->pc) 126 extern void show_regs (struct pt_regs *); 127 valid_user_regs(struct pt_regs * regs)128static __inline__ int valid_user_regs(struct pt_regs *regs) 129 { 130 /* 131 * Some of the Java bits might be acceptable if/when we 132 * implement some support for that stuff... 133 */ 134 if ((regs->sr & 0xffff0000) == 0) 135 return 1; 136 137 /* 138 * Force status register flags to be sane and report this 139 * illegal behaviour... 140 */ 141 regs->sr &= 0x0000ffff; 142 return 0; 143 } 144 #endif 145 146 #endif /* ! __ASSEMBLY__ */ 147 148 #endif /* __ASM_AVR32_PTRACE_H */ 149