1 /*
2 * U-boot - traps.c Routines related to interrupts and exceptions
3 *
4 * Copyright (c) 2005-2008 Analog Devices Inc.
5 *
6 * This file is based on
7 * No original Copyright holder listed,
8 * Probabily original (C) Roman Zippel (assigned DJD, 1999)
9 *
10 * Copyright 2003 Metrowerks - for Blackfin
11 * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
12 * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
13 *
14 * (C) Copyright 2000-2004
15 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
16 *
17 * Licensed under the GPL-2 or later.
18 */
19
20 #include <common.h>
21 #include <kgdb.h>
22 #include <linux/types.h>
23 #include <asm/traps.h>
24 #include <asm/cplb.h>
25 #include <asm/io.h>
26 #include <asm/mach-common/bits/core.h>
27 #include <asm/mach-common/bits/mpu.h>
28 #include <asm/mach-common/bits/trace.h>
29 #include <asm/deferred.h>
30 #include "cpu.h"
31
32 #define trace_buffer_save(x) \
33 do { \
34 (x) = bfin_read_TBUFCTL(); \
35 bfin_write_TBUFCTL((x) & ~TBUFEN); \
36 } while (0)
37
38 #define trace_buffer_restore(x) \
39 bfin_write_TBUFCTL((x))
40
41 /* The purpose of this map is to provide a mapping of address<->cplb settings
42 * rather than an exact map of what is actually addressable on the part. This
43 * map covers all current Blackfin parts. If you try to access an address that
44 * is in this map but not actually on the part, you won't get an exception and
45 * reboot, you'll get an external hardware addressing error and reboot. Since
46 * only the ends matter (you did something wrong and the board reset), the means
47 * are largely irrelevant.
48 */
49 struct memory_map {
50 uint32_t start, end;
51 uint32_t data_flags, inst_flags;
52 };
53 const struct memory_map const bfin_memory_map[] = {
54 { /* external memory */
55 .start = 0x00000000,
56 .end = 0x20000000,
57 .data_flags = SDRAM_DGENERIC,
58 .inst_flags = SDRAM_IGENERIC,
59 },
60 { /* async banks */
61 .start = 0x20000000,
62 .end = 0x30000000,
63 .data_flags = SDRAM_EBIU,
64 .inst_flags = SDRAM_INON_CHBL,
65 },
66 { /* everything on chip */
67 .start = 0xE0000000,
68 .end = 0xFFFFFFFF,
69 .data_flags = L1_DMEMORY,
70 .inst_flags = L1_IMEMORY,
71 }
72 };
73
74 #ifdef CONFIG_EXCEPTION_DEFER
75 unsigned int deferred_regs[deferred_regs_last];
76 #endif
77
78 /*
79 * Handle all exceptions while running in EVT3 or EVT5
80 */
trap_c(struct pt_regs * regs,uint32_t level)81 int trap_c(struct pt_regs *regs, uint32_t level)
82 {
83 uint32_t ret = 0;
84 uint32_t trapnr = (regs->seqstat & EXCAUSE);
85 bool data = false;
86
87 switch (trapnr) {
88 /* 0x26 - Data CPLB Miss */
89 case VEC_CPLB_M:
90
91 if (ANOMALY_05000261) {
92 static uint32_t last_cplb_fault_retx;
93 /*
94 * Work around an anomaly: if we see a new DCPLB fault,
95 * return without doing anything. Then,
96 * if we get the same fault again, handle it.
97 */
98 if (last_cplb_fault_retx != regs->retx) {
99 last_cplb_fault_retx = regs->retx;
100 return ret;
101 }
102 }
103
104 data = true;
105 /* fall through */
106
107 /* 0x27 - Instruction CPLB Miss */
108 case VEC_CPLB_I_M: {
109 volatile uint32_t *CPLB_ADDR_BASE, *CPLB_DATA_BASE, *CPLB_ADDR, *CPLB_DATA;
110 uint32_t new_cplb_addr = 0, new_cplb_data = 0;
111 static size_t last_evicted;
112 size_t i;
113 unsigned long tflags;
114
115 #ifdef CONFIG_EXCEPTION_DEFER
116 /* This should never happen */
117 if (level == 5)
118 bfin_panic(regs);
119 #endif
120
121 /*
122 * Keep the trace buffer so that a miss here points people
123 * to the right place (their code). Crashes here rarely
124 * happen. If they do, only the Blackfin maintainer cares.
125 */
126 trace_buffer_save(tflags);
127
128 new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
129
130 for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) {
131 /* if the exception is inside this range, lets use it */
132 if (new_cplb_addr >= bfin_memory_map[i].start &&
133 new_cplb_addr < bfin_memory_map[i].end)
134 break;
135 }
136 if (i == ARRAY_SIZE(bfin_memory_map)) {
137 printf("%cCPLB exception outside of memory map at 0x%p\n",
138 (data ? 'D' : 'I'), (void *)new_cplb_addr);
139 bfin_panic(regs);
140 } else
141 debug("CPLB addr %p matches map 0x%p - 0x%p\n", new_cplb_addr, bfin_memory_map[i].start, bfin_memory_map[i].end);
142 new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags);
143
144 if (data) {
145 CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0;
146 CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0;
147 } else {
148 CPLB_ADDR_BASE = (uint32_t *)ICPLB_ADDR0;
149 CPLB_DATA_BASE = (uint32_t *)ICPLB_DATA0;
150 }
151
152 /* find the next unlocked entry and evict it */
153 i = last_evicted & 0xF;
154 debug("last evicted = %i\n", i);
155 CPLB_DATA = CPLB_DATA_BASE + i;
156 while (*CPLB_DATA & CPLB_LOCK) {
157 debug("skipping %i %p - %08X\n", i, CPLB_DATA, *CPLB_DATA);
158 i = (i + 1) & 0xF; /* wrap around */
159 CPLB_DATA = CPLB_DATA_BASE + i;
160 }
161 CPLB_ADDR = CPLB_ADDR_BASE + i;
162
163 debug("evicting entry %i: 0x%p 0x%08X\n", i, *CPLB_ADDR, *CPLB_DATA);
164 last_evicted = i + 1;
165
166 /* need to turn off cplbs whenever we muck with the cplb table */
167 #if ENDCPLB != ENICPLB
168 # error cplb enable bit violates my sanity
169 #endif
170 uint32_t mem_control = (data ? DMEM_CONTROL : IMEM_CONTROL);
171 bfin_write32(mem_control, bfin_read32(mem_control) & ~ENDCPLB);
172 *CPLB_ADDR = new_cplb_addr;
173 *CPLB_DATA = new_cplb_data;
174 bfin_write32(mem_control, bfin_read32(mem_control) | ENDCPLB);
175 SSYNC();
176
177 /* dump current table for debugging purposes */
178 CPLB_ADDR = CPLB_ADDR_BASE;
179 CPLB_DATA = CPLB_DATA_BASE;
180 for (i = 0; i < 16; ++i)
181 debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++);
182
183 trace_buffer_restore(tflags);
184 break;
185 }
186 #ifdef CONFIG_CMD_KGDB
187 /* Single step
188 * if we are in IRQ5, just ignore, otherwise defer, and handle it in kgdb
189 */
190 case VEC_STEP:
191 if (level == 3) {
192 /* If we just returned from an interrupt, the single step
193 * event is for the RTI instruction.
194 */
195 if (regs->retx == regs->pc)
196 break;
197 /* we just return if we are single stepping through IRQ5 */
198 if (regs->ipend & 0x20)
199 break;
200 /* Otherwise, turn single stepping off & fall through,
201 * which defers to IRQ5
202 */
203 regs->syscfg &= ~1;
204 }
205 /* fall through */
206 #endif
207 default:
208 #ifdef CONFIG_CMD_KGDB
209 if (level == 3) {
210 /* We need to handle this at EVT5, so try again */
211 ret = 1;
212 break;
213 }
214 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
215 return 0;
216 #endif
217 bfin_panic(regs);
218 }
219 return ret;
220 }
221
222 #ifdef CONFIG_DEBUG_DUMP
223 # define ENABLE_DUMP 1
224 #else
225 # define ENABLE_DUMP 0
226 #endif
227
228 #ifndef CONFIG_KALLSYMS
symbol_lookup(unsigned long addr,unsigned long * caddr)229 const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
230 {
231 *caddr = addr;
232 return "N/A";
233 }
234 #endif
235
decode_address(char * buf,unsigned long address)236 static void decode_address(char *buf, unsigned long address)
237 {
238 unsigned long sym_addr;
239 void *paddr = (void *)address;
240 const char *sym = symbol_lookup(address, &sym_addr);
241
242 if (sym) {
243 sprintf(buf, "<0x%p> { %s + 0x%lx }", paddr, sym, address - sym_addr);
244 return;
245 }
246
247 if (!address)
248 sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr);
249 else if (address >= CONFIG_SYS_MONITOR_BASE &&
250 address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
251 sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr);
252 else
253 sprintf(buf, "<0x%p> /* unknown address */", paddr);
254 }
255
strhwerrcause(uint16_t hwerrcause)256 static char *strhwerrcause(uint16_t hwerrcause)
257 {
258 switch (hwerrcause) {
259 case 0x02: return "system mmr error";
260 case 0x03: return "external memory addressing error";
261 case 0x12: return "performance monitor overflow";
262 case 0x18: return "raise 5 instruction";
263 default: return "undef";
264 }
265 }
266
strexcause(uint16_t excause)267 static char *strexcause(uint16_t excause)
268 {
269 switch (excause) {
270 case 0x00 ... 0xf: return "custom exception";
271 case 0x10: return "single step";
272 case 0x11: return "trace buffer full";
273 case 0x21: return "undef inst";
274 case 0x22: return "illegal inst";
275 case 0x23: return "dcplb prot violation";
276 case 0x24: return "misaligned data";
277 case 0x25: return "unrecoverable event";
278 case 0x26: return "dcplb miss";
279 case 0x27: return "multiple dcplb hit";
280 case 0x28: return "emulation watchpoint";
281 case 0x2a: return "misaligned inst";
282 case 0x2b: return "icplb prot violation";
283 case 0x2c: return "icplb miss";
284 case 0x2d: return "multiple icplb hit";
285 case 0x2e: return "illegal use of supervisor resource";
286 default: return "undef";
287 }
288 }
289
dump(struct pt_regs * fp)290 void dump(struct pt_regs *fp)
291 {
292 char buf[150];
293 int i;
294 uint16_t hwerrcause, excause;
295
296 if (!ENABLE_DUMP)
297 return;
298
299 #ifndef CONFIG_CMD_KGDB
300 /* fp->ipend is normally garbage, so load it ourself */
301 fp->ipend = bfin_read_IPEND();
302 #endif
303
304 hwerrcause = (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P;
305 excause = (fp->seqstat & EXCAUSE) >> EXCAUSE_P;
306
307 printf("SEQUENCER STATUS:\n");
308 printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
309 fp->seqstat, fp->ipend, fp->syscfg);
310 printf(" HWERRCAUSE: 0x%x: %s\n", hwerrcause, strhwerrcause(hwerrcause));
311 printf(" EXCAUSE : 0x%x: %s\n", excause, strexcause(excause));
312 for (i = 6; i <= 15; ++i) {
313 if (fp->ipend & (1 << i)) {
314 decode_address(buf, bfin_read32(EVT0 + 4*i));
315 printf(" physical IVG%i asserted : %s\n", i, buf);
316 }
317 }
318 decode_address(buf, fp->rete);
319 printf(" RETE: %s\n", buf);
320 decode_address(buf, fp->retn);
321 printf(" RETN: %s\n", buf);
322 decode_address(buf, fp->retx);
323 printf(" RETX: %s\n", buf);
324 decode_address(buf, fp->rets);
325 printf(" RETS: %s\n", buf);
326 /* we lie and store RETI in "pc" */
327 decode_address(buf, fp->pc);
328 printf(" RETI: %s\n", buf);
329
330 if (fp->seqstat & EXCAUSE) {
331 decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
332 printf("DCPLB_FAULT_ADDR: %s\n", buf);
333 decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
334 printf("ICPLB_FAULT_ADDR: %s\n", buf);
335 }
336
337 printf("\nPROCESSOR STATE:\n");
338 printf(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
339 fp->r0, fp->r1, fp->r2, fp->r3);
340 printf(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
341 fp->r4, fp->r5, fp->r6, fp->r7);
342 printf(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
343 fp->p0, fp->p1, fp->p2, fp->p3);
344 printf(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
345 fp->p4, fp->p5, fp->fp, (unsigned long)fp);
346 printf(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
347 fp->lb0, fp->lt0, fp->lc0);
348 printf(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
349 fp->lb1, fp->lt1, fp->lc1);
350 printf(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
351 fp->b0, fp->l0, fp->m0, fp->i0);
352 printf(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
353 fp->b1, fp->l1, fp->m1, fp->i1);
354 printf(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
355 fp->b2, fp->l2, fp->m2, fp->i2);
356 printf(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
357 fp->b3, fp->l3, fp->m3, fp->i3);
358 printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
359 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
360
361 printf("USP : %08lx ASTAT: %08lx\n",
362 fp->usp, fp->astat);
363
364 printf("\n");
365 }
366
dump_bfin_trace_buffer(void)367 void dump_bfin_trace_buffer(void)
368 {
369 char buf[150];
370 unsigned long tflags;
371 int i = 0;
372
373 if (!ENABLE_DUMP)
374 return;
375
376 trace_buffer_save(tflags);
377
378 printf("Hardware Trace:\n");
379
380 if (bfin_read_TBUFSTAT() & TBUFCNT) {
381 for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
382 decode_address(buf, bfin_read_TBUF());
383 printf("%4i Target : %s\n", i, buf);
384 decode_address(buf, bfin_read_TBUF());
385 printf(" Source : %s\n", buf);
386 }
387 }
388
389 trace_buffer_restore(tflags);
390 }
391
bfin_panic(struct pt_regs * regs)392 void bfin_panic(struct pt_regs *regs)
393 {
394 if (ENABLE_DUMP) {
395 unsigned long tflags;
396 trace_buffer_save(tflags);
397 }
398
399 puts(
400 "\n"
401 "\n"
402 "\n"
403 "Ack! Something bad happened to the Blackfin!\n"
404 "\n"
405 );
406 dump(regs);
407 dump_bfin_trace_buffer();
408 puts("\n");
409 bfin_reset_or_hang();
410 }
411