1 /*
2 * (C) Copyright 2006 - 2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Copyright (c) 2005 Cisco Systems. All rights reserved.
6 * Roland Dreier <rolandd@cisco.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23 /* define DEBUG for debugging output (obviously ;-)) */
24 #if 0
25 #define DEBUG
26 #endif
27
28 #include <common.h>
29 #include <pci.h>
30 #include <ppc4xx.h>
31 #include <asm/processor.h>
32 #include <asm/io.h>
33 #include <asm/errno.h>
34
35 #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
36 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
37 defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE)
38
39 #include <asm/4xx_pcie.h>
40
41 enum {
42 PTYPE_ENDPOINT = 0x0,
43 PTYPE_LEGACY_ENDPOINT = 0x1,
44 PTYPE_ROOT_PORT = 0x4,
45
46 LNKW_X1 = 0x1,
47 LNKW_X4 = 0x4,
48 LNKW_X8 = 0x8
49 };
50
51 #ifndef CONFIG_SAM460EX
52 static struct pci_controller pcie_hose[CONFIG_SYS_PCIE_NR_PORTS];
53 #else
54 struct pci_controller pcie_hose[CONFIG_SYS_PCIE_NR_PORTS];
55 #endif
56
57 /*
58 * Per default, all cards are present, so we need to check if the
59 * link comes up.
60 */
__board_pcie_card_present(int port)61 int __board_pcie_card_present(int port)
62 {
63 return 1;
64 }
65 int board_pcie_card_present(int port)
66 __attribute__((weak, alias("__board_pcie_card_present")));
67
68 /*
69 * Some boards have runtime detection of the first and last PCIe
70 * slot used, so let's provide weak default functions for the
71 * common version.
72 */
__board_pcie_first(void)73 int __board_pcie_first(void)
74 {
75 return 0;
76 }
77 int board_pcie_first(void)
78 __attribute__((weak, alias("__board_pcie_first")));
79
__board_pcie_last(void)80 int __board_pcie_last(void)
81 {
82 return CONFIG_SYS_PCIE_NR_PORTS - 1;
83 }
84 int board_pcie_last(void)
85 __attribute__((weak, alias("__board_pcie_last")));
86
__board_pcie_setup_port(int port,int rootpoint)87 void __board_pcie_setup_port(int port, int rootpoint)
88 {
89 /* noting in this weak default implementation */
90 }
91 void board_pcie_setup_port(int port, int rootpoint)
92 __attribute__((weak, alias("__board_pcie_setup_port")));
93
pcie_setup_hoses(int busno)94 void pcie_setup_hoses(int busno)
95 {
96 struct pci_controller *hose;
97 int i, bus;
98 int ret = 0;
99 char *env;
100 unsigned int delay;
101 int first = board_pcie_first();
102 int last = board_pcie_last();
103
104 /*
105 * Assume we're called after the PCI(X) hose(s) are initialized,
106 * which takes bus ID 0... and therefore start numbering PCIe's
107 * from the next number.
108 */
109 bus = busno;
110
111 for (i = first; i <= last; i++) {
112 /*
113 * Some boards (e.g. Katmai) can detects via hardware
114 * if a PCIe card is plugged, so let's check this.
115 */
116 if (!board_pcie_card_present(i))
117 continue;
118
119 if (is_end_point(i)) {
120 board_pcie_setup_port(i, 0);
121 ret = ppc4xx_init_pcie_endport(i);
122 } else {
123 board_pcie_setup_port(i, 1);
124 ret = ppc4xx_init_pcie_rootport(i);
125 }
126 if (ret == -ENODEV)
127 continue;
128 if (ret) {
129 printf("PCIE%d: initialization as %s failed\n", i,
130 is_end_point(i) ? "endpoint" : "root-complex");
131 continue;
132 }
133
134 hose = &pcie_hose[i];
135 hose->first_busno = bus;
136 hose->last_busno = bus;
137 hose->current_busno = bus;
138
139 /* setup mem resource */
140 #ifdef CONFIG_SAM460EX
141 if (i == 1)
142 pci_set_region(hose->regions + 0,
143 CONFIG_SYS_PCIE_MEMBASE,
144 CONFIG_SYS_PCIE_MEMBASE,
145 2*CONFIG_SYS_PCIE_MEMSIZE,
146 PCI_REGION_MEM);
147 else
148 pci_set_region(hose->regions + 0,
149 CONFIG_SYS_PCIE_MEMBASE + 2*CONFIG_SYS_PCIE_MEMSIZE,
150 CONFIG_SYS_PCIE_MEMBASE + 2*CONFIG_SYS_PCIE_MEMSIZE,
151 CONFIG_SYS_PCIE_MEMSIZE,
152 PCI_REGION_MEM);
153
154 hose->region_count = 1;
155
156 pci_set_region(hose->regions + 1,
157 CONFIG_SYS_PCIE_IOBASE,
158 CONFIG_SYS_PCIE_IOBASE,
159 CONFIG_SYS_PCIE_IOSIZE,
160 PCI_REGION_IO);
161 hose->region_count = 2;
162 #else
163 pci_set_region(hose->regions + 0,
164 CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
165 CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
166 CONFIG_SYS_PCIE_MEMSIZE,
167 PCI_REGION_MEM);
168 hose->region_count = 1;
169 #endif
170
171 pci_register_hose(hose);
172
173 if (is_end_point(i)) {
174 ppc4xx_setup_pcie_endpoint(hose, i);
175 /*
176 * Reson for no scanning is endpoint can not generate
177 * upstream configuration accesses.
178 */
179 } else {
180 ppc4xx_setup_pcie_rootpoint(hose, i);
181 env = getenv ("pciscandelay");
182 if (env != NULL) {
183 delay = simple_strtoul(env, NULL, 10);
184 if (delay > 5)
185 printf("Warning, expect noticable delay before "
186 "PCIe scan due to 'pciscandelay' value!\n");
187 mdelay(delay * 1000);
188 }
189
190 /*
191 * Config access can only go down stream
192 */
193 hose->last_busno = pci_hose_scan(hose);
194 bus = hose->last_busno + 1;
195 }
196 }
197 }
198
validate_endpoint(struct pci_controller * hose)199 static int validate_endpoint(struct pci_controller *hose)
200 {
201 if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE)
202 return (is_end_point(0));
203 else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE)
204 return (is_end_point(1));
205 #if CONFIG_SYS_PCIE_NR_PORTS > 2
206 else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE)
207 return (is_end_point(2));
208 #endif
209
210 return 0;
211 }
212
pcie_get_base(struct pci_controller * hose,unsigned int devfn)213 static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
214 {
215 u8 *base = (u8*)hose->cfg_data;
216
217 /* use local configuration space for the first bus */
218 if (PCI_BUS(devfn) == 0) {
219 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE)
220 base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE;
221 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE)
222 base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE;
223 #if CONFIG_SYS_PCIE_NR_PORTS > 2
224 if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE)
225 base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE;
226 #endif
227 }
228
229 return base;
230 }
231
pcie_dmer_disable(void)232 static void pcie_dmer_disable(void)
233 {
234 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
235 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
236 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
237 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
238 #if CONFIG_SYS_PCIE_NR_PORTS > 2
239 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
240 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
241 #endif
242 }
243
pcie_dmer_enable(void)244 static void pcie_dmer_enable(void)
245 {
246 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE),
247 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
248 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
249 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
250 #if CONFIG_SYS_PCIE_NR_PORTS > 2
251 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
252 mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
253 #endif
254 }
255
pcie_read_config(struct pci_controller * hose,unsigned int devfn,int offset,int len,u32 * val)256 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
257 int offset, int len, u32 *val) {
258
259 u8 *address;
260 *val = 0;
261
262 if (validate_endpoint(hose))
263 return 0; /* No upstream config access */
264
265 /*
266 * Bus numbers are relative to hose->first_busno
267 */
268 devfn -= PCI_BDF(hose->first_busno, 0, 0);
269
270 /*
271 * NOTICE: configuration space ranges are currenlty mapped only for
272 * the first 16 buses, so such limit must be imposed. In case more
273 * buses are required the TLB settings in board/amcc/<board>/init.S
274 * need to be altered accordingly (one bus takes 1 MB of memory space).
275 */
276 if (PCI_BUS(devfn) >= 16)
277 return 0;
278
279 /*
280 * Only single device/single function is supported for the primary and
281 * secondary buses of the 440SPe host bridge.
282 */
283 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
284 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
285 return 0;
286
287 address = pcie_get_base(hose, devfn);
288 offset += devfn << 4;
289
290 /*
291 * Reading from configuration space of non-existing device can
292 * generate transaction errors. For the read duration we suppress
293 * assertion of machine check exceptions to avoid those.
294 */
295 pcie_dmer_disable ();
296
297 debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset);
298 switch (len) {
299 case 1:
300 *val = in_8(hose->cfg_data + offset);
301 break;
302 case 2:
303 *val = in_le16((u16 *)(hose->cfg_data + offset));
304 break;
305 default:
306 *val = in_le32((u32*)(hose->cfg_data + offset));
307 break;
308 }
309
310 pcie_dmer_enable ();
311
312 return 0;
313 }
314
pcie_write_config(struct pci_controller * hose,unsigned int devfn,int offset,int len,u32 val)315 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
316 int offset, int len, u32 val) {
317
318 u8 *address;
319
320 if (validate_endpoint(hose))
321 return 0; /* No upstream config access */
322
323 /*
324 * Bus numbers are relative to hose->first_busno
325 */
326 devfn -= PCI_BDF(hose->first_busno, 0, 0);
327
328 /*
329 * Same constraints as in pcie_read_config().
330 */
331 if (PCI_BUS(devfn) >= 16)
332 return 0;
333
334 if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
335 ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
336 return 0;
337
338 address = pcie_get_base(hose, devfn);
339 offset += devfn << 4;
340
341 /*
342 * Suppress MCK exceptions, similar to pcie_read_config()
343 */
344 pcie_dmer_disable ();
345
346 switch (len) {
347 case 1:
348 out_8(hose->cfg_data + offset, val);
349 break;
350 case 2:
351 out_le16((u16 *)(hose->cfg_data + offset), val);
352 break;
353 default:
354 out_le32((u32 *)(hose->cfg_data + offset), val);
355 break;
356 }
357
358 pcie_dmer_enable ();
359
360 return 0;
361 }
362
pcie_read_config_byte(struct pci_controller * hose,pci_dev_t dev,int offset,u8 * val)363 int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
364 {
365 u32 v;
366 int rv;
367
368 rv = pcie_read_config(hose, dev, offset, 1, &v);
369 *val = (u8)v;
370 return rv;
371 }
372
pcie_read_config_word(struct pci_controller * hose,pci_dev_t dev,int offset,u16 * val)373 int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
374 {
375 u32 v;
376 int rv;
377
378 rv = pcie_read_config(hose, dev, offset, 2, &v);
379 *val = (u16)v;
380 return rv;
381 }
382
pcie_read_config_dword(struct pci_controller * hose,pci_dev_t dev,int offset,u32 * val)383 int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
384 {
385 u32 v;
386 int rv;
387
388 rv = pcie_read_config(hose, dev, offset, 3, &v);
389 *val = (u32)v;
390 return rv;
391 }
392
pcie_write_config_byte(struct pci_controller * hose,pci_dev_t dev,int offset,u8 val)393 int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
394 {
395 return pcie_write_config(hose,(u32)dev,offset,1,val);
396 }
397
pcie_write_config_word(struct pci_controller * hose,pci_dev_t dev,int offset,u16 val)398 int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
399 {
400 return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
401 }
402
pcie_write_config_dword(struct pci_controller * hose,pci_dev_t dev,int offset,u32 val)403 int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
404 {
405 return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
406 }
407
408 #if defined(CONFIG_440SPE)
ppc4xx_setup_utl(u32 port)409 static void ppc4xx_setup_utl(u32 port) {
410
411 volatile void *utl_base = NULL;
412
413 /*
414 * Map UTL registers
415 */
416 switch (port) {
417 case 0:
418 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
419 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
420 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
421 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
422 break;
423
424 case 1:
425 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
426 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
427 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
428 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
429 break;
430
431 case 2:
432 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
433 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
434 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
435 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
436 break;
437 }
438 utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
439
440 /*
441 * Set buffer allocations and then assert VRB and TXE.
442 */
443 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
444 out_be32(utl_base + PEUTL_INTR, 0x02000000);
445 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
446 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
447 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
448 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
449 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
450 out_be32(utl_base + PEUTL_PCTL, 0x80800066);
451 }
452
check_error(void)453 static int check_error(void)
454 {
455 u32 valPE0, valPE1, valPE2;
456 int err = 0;
457
458 /* SDR0_PEGPLLLCT1 reset */
459 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000))
460 printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
461
462 valPE0 = SDR_READ(PESDR0_RCSSET);
463 valPE1 = SDR_READ(PESDR1_RCSSET);
464 valPE2 = SDR_READ(PESDR2_RCSSET);
465
466 /* SDR0_PExRCSSET rstgu */
467 if (!(valPE0 & 0x01000000) ||
468 !(valPE1 & 0x01000000) ||
469 !(valPE2 & 0x01000000)) {
470 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
471 err = -1;
472 }
473
474 /* SDR0_PExRCSSET rstdl */
475 if (!(valPE0 & 0x00010000) ||
476 !(valPE1 & 0x00010000) ||
477 !(valPE2 & 0x00010000)) {
478 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
479 err = -1;
480 }
481
482 /* SDR0_PExRCSSET rstpyn */
483 if ((valPE0 & 0x00001000) ||
484 (valPE1 & 0x00001000) ||
485 (valPE2 & 0x00001000)) {
486 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
487 err = -1;
488 }
489
490 /* SDR0_PExRCSSET hldplb */
491 if ((valPE0 & 0x10000000) ||
492 (valPE1 & 0x10000000) ||
493 (valPE2 & 0x10000000)) {
494 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
495 err = -1;
496 }
497
498 /* SDR0_PExRCSSET rdy */
499 if ((valPE0 & 0x00100000) ||
500 (valPE1 & 0x00100000) ||
501 (valPE2 & 0x00100000)) {
502 printf("PCIE: SDR0_PExRCSSET rdy error\n");
503 err = -1;
504 }
505
506 /* SDR0_PExRCSSET shutdown */
507 if ((valPE0 & 0x00000100) ||
508 (valPE1 & 0x00000100) ||
509 (valPE2 & 0x00000100)) {
510 printf("PCIE: SDR0_PExRCSSET shutdown error\n");
511 err = -1;
512 }
513 return err;
514 }
515
516 /*
517 * Initialize PCI Express core
518 */
ppc4xx_init_pcie(void)519 int ppc4xx_init_pcie(void)
520 {
521 int time_out = 20;
522
523 /* Set PLL clock receiver to LVPECL */
524 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
525
526 if (check_error()) {
527 printf("ERROR: failed to set PCIe reference clock receiver --"
528 "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1));
529
530 return -1;
531 }
532
533 /* Did resistance calibration work? */
534 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) {
535 printf("ERROR: PCIe resistance calibration failed --"
536 "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2));
537
538 return -1;
539 }
540 /* De-assert reset of PCIe PLL, wait for lock */
541 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
542 udelay(300); /* 300 uS is maximum time lock should take */
543
544 while (time_out) {
545 if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
546 time_out--;
547 udelay(20); /* Wait 20 uS more if needed */
548 } else
549 break;
550 }
551 if (!time_out) {
552 printf("ERROR: PCIe PLL VCO output not locked to ref clock --"
553 "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3));
554
555 return -1;
556 }
557 return 0;
558 }
559 #endif
560
561 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
ppc4xx_setup_utl(u32 port)562 static void ppc4xx_setup_utl(u32 port)
563 {
564 volatile void *utl_base = NULL;
565
566 /*
567 * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK
568 */
569 switch (port) {
570 case 0:
571 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
572 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE));
573 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */
574 #ifdef CONFIG_SAM460EX
575 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x38587828);
576 #else
577 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
578 #endif
579 break;
580
581 case 1:
582 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
583 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)
584 + 0x1000);
585 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */
586 #ifdef CONFIG_SAM460EX
587 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x38587828);
588 #else
589 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
590 #endif
591 break;
592 }
593 utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
594
595 /*
596 * Set buffer allocations and then assert VRB and TXE.
597 */
598 out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */
599 out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
600 out_be32(utl_base + PEUTL_INTR, 0x02000000);
601 out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */
602 out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */
603 out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000);
604 out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */
605 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
606 out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */
607 }
608
609 /*
610 * TODO: double check PCI express SDR based on the latest user manual
611 * Some registers specified here no longer exist.. has to be
612 * updated based on the final EAS spec.
613 */
check_error(void)614 static int check_error(void)
615 {
616 u32 valPE0, valPE1;
617 int err = 0;
618
619 valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0));
620 valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1));
621
622 /* SDR0_PExRCSSET rstgu */
623 if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) {
624 printf("PCIE: SDR0_PExRCSSET rstgu error\n");
625 err = -1;
626 }
627
628 /* SDR0_PExRCSSET rstdl */
629 if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) {
630 printf("PCIE: SDR0_PExRCSSET rstdl error\n");
631 err = -1;
632 }
633
634 /* SDR0_PExRCSSET rstpyn */
635 if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) {
636 printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
637 err = -1;
638 }
639
640 /* SDR0_PExRCSSET hldplb */
641 if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) {
642 printf("PCIE: SDR0_PExRCSSET hldplb error\n");
643 err = -1;
644 }
645
646 /* SDR0_PExRCSSET rdy */
647 if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) {
648 printf("PCIE: SDR0_PExRCSSET rdy error\n");
649 err = -1;
650 }
651
652 return err;
653 }
654
655 /*
656 * Initialize PCI Express core as described in User Manual
657 * TODO: double check PE SDR PLL Register with the updated user manual.
658 */
ppc4xx_init_pcie(void)659 int ppc4xx_init_pcie(void)
660 {
661 if (check_error())
662 return -1;
663
664 return 0;
665 }
666 #endif /* CONFIG_460EX */
667
668 #if defined(CONFIG_405EX)
ppc4xx_setup_utl(u32 port)669 static void ppc4xx_setup_utl(u32 port)
670 {
671 u32 utl_base;
672
673 /*
674 * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
675 */
676 switch (port) {
677 case 0:
678 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
679 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE);
680 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
681 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
682 break;
683
684 case 1:
685 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
686 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE);
687 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
688 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
689
690 break;
691 }
692 utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE;
693
694 /*
695 * Set buffer allocations and then assert VRB and TXE.
696 */
697 out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x04000000); // was 0x02000000
698 out_be32((u32 *)(utl_base + PEUTL_INTR), 0x04000000); // was 0x02000000
699 out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000);
700 out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000);
701 out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000);
702 out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000);
703 out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000);
704 out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066);
705
706 out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c);
707 out_be32((u32 *)(utl_base + PEUTL_RCSTA),
708 in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000);
709 }
710
ppc4xx_init_pcie(void)711 int ppc4xx_init_pcie(void)
712 {
713 /*
714 * Nothing to do on 405EX
715 */
716 return 0;
717 }
718 #endif /* CONFIG_405EX */
719
720 /*
721 * Board-specific pcie initialization
722 * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed
723 */
724
725 /*
726 * Initialize various parts of the PCI Express core for our port:
727 *
728 * - Set as a root port and enable max width
729 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
730 * - Set up UTL configuration.
731 * - Increase SERDES drive strength to levels suggested by AMCC.
732 * - De-assert RSTPYN, RSTDL and RSTGU.
733 *
734 * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it
735 * with default setting 0x11310000. The register has new fields,
736 * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
737 * hang.
738 */
739 #if defined(CONFIG_440SPE)
__ppc4xx_init_pcie_port_hw(int port,int rootport)740 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
741 {
742 u32 val = 1 << 24;
743 u32 utlset1;
744
745 if (rootport) {
746 val = PTYPE_ROOT_PORT << 20;
747 utlset1 = 0x21222222;
748 } else {
749 val = PTYPE_LEGACY_ENDPOINT << 20;
750 utlset1 = 0x20222222;
751 }
752
753 if (port == 0)
754 val |= LNKW_X8 << 12;
755 else
756 val |= LNKW_X4 << 12;
757
758 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
759 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
760 if (!ppc440spe_revB())
761 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000);
762 SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000);
763 SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000);
764 SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000);
765 SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000);
766 if (port == 0) {
767 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
768 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
769 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
770 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
771 }
772 SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) &
773 ~(1 << 24 | 1 << 16)) | 1 << 12);
774
775 return 0;
776 }
777 #endif /* CONFIG_440SPE */
778
779 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
__ppc4xx_init_pcie_port_hw(int port,int rootport)780 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
781 {
782 u32 val;
783 u32 utlset1;
784
785 if (rootport)
786 val = PTYPE_ROOT_PORT << 20;
787 else
788 val = PTYPE_LEGACY_ENDPOINT << 20;
789
790 if (port == 0) {
791 val |= LNKW_X1 << 12;
792 utlset1 = 0x20000000;
793 } else {
794 val |= LNKW_X4 << 12;
795 utlset1 = 0x20101101;
796 }
797
798 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
799 SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1);
800 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000);
801
802 switch (port) {
803 case 0:
804 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230);
805 SDR_WRITE(PESDR0_L0DRV, 0x00000130);
806 SDR_WRITE(PESDR0_L0CLK, 0x00000006);
807
808 SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000);
809 break;
810
811 case 1:
812 SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230);
813 SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230);
814 SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230);
815 SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230);
816 SDR_WRITE(PESDR1_L0DRV, 0x00000132); // was 0x...130
817 SDR_WRITE(PESDR1_L1DRV, 0x00000132);
818 SDR_WRITE(PESDR1_L2DRV, 0x00000132);
819 SDR_WRITE(PESDR1_L3DRV, 0x00000132);
820 SDR_WRITE(PESDR1_L0CLK, 0x00000006);
821 SDR_WRITE(PESDR1_L1CLK, 0x00000006);
822 SDR_WRITE(PESDR1_L2CLK, 0x00000006);
823 SDR_WRITE(PESDR1_L3CLK, 0x00000006);
824
825 SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000);
826 break;
827 }
828
829 SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) |
830 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
831
832 /* Poll for PHY reset */
833 switch (port) {
834 case 0:
835 while (!(SDR_READ(PESDR0_RSTSTA) & 0x1))
836 udelay(10);
837 break;
838 case 1:
839 while (!(SDR_READ(PESDR1_RSTSTA) & 0x1))
840 udelay(10);
841 break;
842 }
843
844 SDR_WRITE(SDRN_PESDR_RCSSET(port),
845 (SDR_READ(SDRN_PESDR_RCSSET(port)) &
846 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
847 PESDRx_RCSSET_RSTPYN);
848
849 return 0;
850 }
851 #endif /* CONFIG_440SPE */
852
853 #if defined(CONFIG_405EX)
__ppc4xx_init_pcie_port_hw(int port,int rootport)854 int __ppc4xx_init_pcie_port_hw(int port, int rootport)
855 {
856 u32 val;
857
858 if (rootport)
859 val = 0x00401000;
860 else
861 val = 0x00101000;
862
863 SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
864 SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000);
865 SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000);
866 SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000);
867 SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003);
868
869 /* Assert the PE0_PHY reset */
870 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000);
871 udelay(1000);
872
873 /* deassert the PE0_hotreset */
874 if (is_end_point(port))
875 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000);
876 else
877 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000);
878
879 /* poll for phy !reset */
880 while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000))
881 ;
882
883 /* deassert the PE0_gpl_utl_reset */
884 SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);
885
886 if (port == 0)
887 mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */
888 else
889 mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */
890
891 return 0;
892 }
893 #endif /* CONFIG_405EX */
894
895 int ppc4xx_init_pcie_port_hw(int port, int rootport)
896 __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
897
898 /*
899 * We map PCI Express configuration access into the 512MB regions
900 *
901 * NOTICE: revB is very strict about PLB real addressess and ranges to
902 * be mapped for config space; it seems to only work with d_nnnn_nnnn
903 * range (hangs the core upon config transaction attempts when set
904 * otherwise) while revA uses c_nnnn_nnnn.
905 *
906 * For 440SPe revA:
907 * PCIE0: 0xc_4000_0000
908 * PCIE1: 0xc_8000_0000
909 * PCIE2: 0xc_c000_0000
910 *
911 * For 440SPe revB:
912 * PCIE0: 0xd_0000_0000
913 * PCIE1: 0xd_2000_0000
914 * PCIE2: 0xd_4000_0000
915 *
916 * For 405EX:
917 * PCIE0: 0xa000_0000
918 * PCIE1: 0xc000_0000
919 *
920 * For 460EX/GT:
921 * PCIE0: 0xd_0000_0000
922 * PCIE1: 0xd_2000_0000
923 */
ppc4xx_get_cfgaddr(int port)924 static inline u64 ppc4xx_get_cfgaddr(int port)
925 {
926 #if defined(CONFIG_405EX)
927 if (port == 0)
928 return (u64)CONFIG_SYS_PCIE0_CFGBASE;
929 else
930 return (u64)CONFIG_SYS_PCIE1_CFGBASE;
931 #endif
932 #if defined(CONFIG_440SPE)
933 if (ppc440spe_revB()) {
934 switch (port) {
935 default: /* to satisfy compiler */
936 case 0:
937 return 0x0000000d00000000ULL;
938 case 1:
939 return 0x0000000d20000000ULL;
940 case 2:
941 return 0x0000000d40000000ULL;
942 }
943 } else {
944 switch (port) {
945 default: /* to satisfy compiler */
946 case 0:
947 return 0x0000000c40000000ULL;
948 case 1:
949 return 0x0000000c80000000ULL;
950 case 2:
951 return 0x0000000cc0000000ULL;
952 }
953 }
954 #endif
955 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
956 if (port == 0)
957 return 0x0000000d00000000ULL;
958 else
959 return 0x0000000d20000000ULL;
960 #endif
961 }
962
963 /*
964 * 4xx boards as endpoint and root point setup
965 * and
966 * testing inbound and out bound windows
967 *
968 * 4xx boards can be plugged into another 4xx boards or you can get PCI-E
969 * cable which can be used to setup loop back from one port to another port.
970 * Please rememeber that unless there is a endpoint plugged in to root port it
971 * will not initialize. It is the same in case of endpoint , unless there is
972 * root port attached it will not initialize.
973 *
974 * In this release of software all the PCI-E ports are configured as either
975 * endpoint or rootpoint.In future we will have support for selective ports
976 * setup as endpoint and root point in single board.
977 *
978 * Once your board came up as root point , you can verify by reading
979 * /proc/bus/pci/devices. Where you can see the configuration registers
980 * of endpoint device attached to the port.
981 *
982 * Enpoint cofiguration can be verified by connecting 4xx board to any
983 * host or another 4xx board. Then try to scan the device. In case of
984 * linux use "lspci" or appripriate os command.
985 *
986 * How do I verify the inbound and out bound windows ? (4xx to 4xx)
987 * in this configuration inbound and outbound windows are setup to access
988 * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
989 * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
990 * This is waere your POM(PLB out bound memory window) mapped. then
991 * read the data from other 4xx board's u-boot prompt at address
992 * 0x9000 0000(SRAM). Data should match.
993 * In case of inbound , write data to u-boot command prompt at 0xb000 0000
994 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
995 * data at 0x9000 0000(SRAM).Data should match.
996 */
ppc4xx_init_pcie_port(int port,int rootport)997 int ppc4xx_init_pcie_port(int port, int rootport)
998 {
999 static int core_init;
1000 volatile u32 val = 0;
1001 int attempts;
1002 u64 addr;
1003 u32 low, high;
1004
1005 if (!core_init) {
1006 if (ppc4xx_init_pcie())
1007 return -1;
1008 ++core_init;
1009 }
1010
1011 /*
1012 * Initialize various parts of the PCI Express core for our port
1013 */
1014 ppc4xx_init_pcie_port_hw(port, rootport);
1015
1016 /*
1017 * Notice: the following delay has critical impact on device
1018 * initialization - if too short (<50ms) the link doesn't get up.
1019 */
1020 mdelay(100);
1021
1022 val = SDR_READ(SDRN_PESDR_RCSSTS(port));
1023 if (val & (1 << 20)) {
1024 printf("PCIE%d: PGRST failed %08x\n", port, val);
1025 return -1;
1026 }
1027
1028 /*
1029 * Verify link is up
1030 */
1031 val = SDR_READ(SDRN_PESDR_LOOP(port));
1032 if (!(val & 0x00001000)) {
1033 printf("PCIE%d: link is not up.\n", port);
1034 return -ENODEV;
1035 }
1036
1037 /*
1038 * Setup UTL registers - but only on revA!
1039 * We use default settings for revB chip.
1040 */
1041 if (!ppc440spe_revB())
1042 ppc4xx_setup_utl(port);
1043
1044 /*
1045 * We map PCI Express configuration access into the 512MB regions
1046 */
1047 addr = ppc4xx_get_cfgaddr(port);
1048 low = U64_TO_U32_LOW(addr);
1049 high = U64_TO_U32_HIGH(addr);
1050
1051 switch (port) {
1052 case 0:
1053 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high);
1054 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low);
1055 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
1056 break;
1057 case 1:
1058 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high);
1059 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
1060 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
1061 break;
1062 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1063 case 2:
1064 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
1065 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
1066 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
1067 break;
1068 #endif
1069 }
1070
1071 /*
1072 * Check for VC0 active and assert RDY.
1073 */
1074 attempts = 10;
1075 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) {
1076 if (!(attempts--)) {
1077 printf("PCIE%d: VC0 not active\n", port);
1078 return -1;
1079 }
1080 mdelay(1000);
1081 }
1082 SDR_WRITE(SDRN_PESDR_RCSSET(port),
1083 SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20);
1084 mdelay(100);
1085
1086 return 0;
1087 }
1088
ppc4xx_init_pcie_rootport(int port)1089 int ppc4xx_init_pcie_rootport(int port)
1090 {
1091 return ppc4xx_init_pcie_port(port, 1);
1092 }
1093
ppc4xx_init_pcie_endport(int port)1094 int ppc4xx_init_pcie_endport(int port)
1095 {
1096 return ppc4xx_init_pcie_port(port, 0);
1097 }
1098
ppc4xx_setup_pcie_rootpoint(struct pci_controller * hose,int port)1099 void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
1100 {
1101 volatile void *mbase = NULL;
1102 volatile void *rmbase = NULL;
1103
1104 pci_set_ops(hose,
1105 pcie_read_config_byte,
1106 pcie_read_config_word,
1107 pcie_read_config_dword,
1108 pcie_write_config_byte,
1109 pcie_write_config_word,
1110 pcie_write_config_dword);
1111
1112 switch (port) {
1113 case 0:
1114 mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
1115 rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE;
1116 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
1117 break;
1118 case 1:
1119 mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
1120 rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE;
1121 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
1122 break;
1123 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1124 case 2:
1125 mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
1126 rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE;
1127 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
1128 break;
1129 #endif
1130 }
1131
1132 /*
1133 * Set bus numbers on our root port
1134 */
1135 out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
1136 out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
1137 out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
1138
1139 /*
1140 * Set up outbound translation to hose->mem_space from PLB
1141 * addresses at an offset of 0xd_0000_0000. We set the low
1142 * bits of the mask to 11 to turn off splitting into 8
1143 * subregions and to enable the outbound translation.
1144 */
1145 #ifdef CONFIG_SAM460EX
1146 if (port == 1)
1147 {
1148 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
1149 out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE);
1150 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
1151 in_le32(mbase + PECFG_POM0LAL));
1152
1153 out_le32(mbase + PECFG_POM2LAH, 0x00000000);
1154 out_le32(mbase + PECFG_POM2LAL, CONFIG_SYS_PCIE_MEMBASE);
1155 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM2LAH),
1156 in_le32(mbase + PECFG_POM2LAL));
1157 }
1158
1159 if (port == 0)
1160 {
1161 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
1162 out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE + 2*CONFIG_SYS_PCIE_MEMSIZE);
1163 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
1164 in_le32(mbase + PECFG_POM0LAL));
1165
1166 out_le32(mbase + PECFG_POM2LAH, 0x00000000);
1167 out_le32(mbase + PECFG_POM2LAL, CONFIG_SYS_PCIE_MEMBASE + 2*CONFIG_SYS_PCIE_MEMSIZE);
1168 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM2LAH),
1169 in_le32(mbase + PECFG_POM2LAL));
1170 }
1171 #else
1172 out_le32(mbase + PECFG_POM0LAH, 0x00000000);
1173 out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE +
1174 port * CONFIG_SYS_PCIE_MEMSIZE);
1175 debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
1176 in_le32(mbase + PECFG_POM0LAL));
1177 #endif
1178
1179 switch (port) {
1180 case 0:
1181 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
1182 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE + 2*CONFIG_SYS_PCIE_MEMSIZE);
1183 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
1184 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
1185 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1186 debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1187 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
1188 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
1189 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)),
1190 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
1191 break;
1192 case 1:
1193 #ifdef CONFIG_SAM460EX
1194 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
1195 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE);
1196 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1197 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
1198 ~(2*CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1199 debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1200 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
1201 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
1202 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
1203 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
1204 #else
1205 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
1206 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
1207 port * CONFIG_SYS_PCIE_MEMSIZE);
1208 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1209 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
1210 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1211 debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1212 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
1213 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
1214 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
1215 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
1216 #endif
1217 break;
1218 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1219 case 2:
1220 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
1221 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
1222 port * CONFIG_SYS_PCIE_MEMSIZE);
1223 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
1224 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
1225 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1226 debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
1227 mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
1228 mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
1229 mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)),
1230 mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2)));
1231 break;
1232 #endif
1233 }
1234
1235 /* Set up 4GB inbound memory window at 0 */
1236 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
1237 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
1238 out_le32(mbase + PECFG_BAR0HMPA, 0x7ffffff);
1239 #ifdef CONFIG_SAM460EX
1240 out_le32(mbase + PECFG_BAR0LMPA, 0x08); // prefetch enabled
1241 #else
1242 out_le32(mbase + PECFG_BAR0LMPA, 0);
1243 #endif
1244
1245 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1246 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1247 out_le32(mbase + PECFG_PIM0LAL, 0);
1248 out_le32(mbase + PECFG_PIM0LAH, 0);
1249 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1250 out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
1251 out_le32(mbase + PECFG_PIMEN, 0x1);
1252
1253 /* Enable I/O, Mem, and Busmaster cycles */
1254 out_le16((u16 *)(mbase + PCI_COMMAND),
1255 in_le16((u16 *)(mbase + PCI_COMMAND)) |
1256 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1257
1258 /* Set Device and Vendor Id */
1259 out_le16(mbase + 0x200, 0xacbe);
1260 out_le16(mbase + 0x202, 0x0000 + port);
1261
1262 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1263 out_le32(mbase + 0x208, 0x06040001);
1264
1265 printf("PCIE%d: successfully set as root-complex\n", port);
1266 }
1267
ppc4xx_setup_pcie_endpoint(struct pci_controller * hose,int port)1268 int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
1269 {
1270 volatile void *mbase = NULL;
1271 int attempts = 0;
1272
1273 pci_set_ops(hose,
1274 pcie_read_config_byte,
1275 pcie_read_config_word,
1276 pcie_read_config_dword,
1277 pcie_write_config_byte,
1278 pcie_write_config_word,
1279 pcie_write_config_dword);
1280
1281 switch (port) {
1282 case 0:
1283 mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
1284 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
1285 break;
1286 case 1:
1287 mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
1288 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
1289 break;
1290 #if defined(CONFIG_SYS_PCIE2_CFGBASE)
1291 case 2:
1292 mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
1293 hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
1294 break;
1295 #endif
1296 }
1297
1298 /*
1299 * Set up outbound translation to hose->mem_space from PLB
1300 * addresses at an offset of 0xd_0000_0000. We set the low
1301 * bits of the mask to 11 to turn off splitting into 8
1302 * subregions and to enable the outbound translation.
1303 */
1304 out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
1305 out_le32(mbase + PECFG_POM0LAL, 0x00001000);
1306
1307 switch (port) {
1308 case 0:
1309 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
1310 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
1311 port * CONFIG_SYS_PCIE_MEMSIZE);
1312 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
1313 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
1314 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1315 break;
1316 case 1:
1317 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
1318 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
1319 port * CONFIG_SYS_PCIE_MEMSIZE);
1320 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
1321 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
1322 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1323 break;
1324 #if CONFIG_SYS_PCIE_NR_PORTS > 2
1325 case 2:
1326 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
1327 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
1328 port * CONFIG_SYS_PCIE_MEMSIZE);
1329 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
1330 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
1331 ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
1332 break;
1333 #endif
1334 }
1335
1336 /* Set up 64MB inbound memory window at 0 */
1337 out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
1338 out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
1339
1340 out_le32(mbase + PECFG_PIM01SAH, 0xffffffff);
1341 out_le32(mbase + PECFG_PIM01SAL, 0xfc000000);
1342
1343 /* Setup BAR0 */
1344 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff);
1345 out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64);
1346
1347 /* Disable BAR1 & BAR2 */
1348 out_le32(mbase + PECFG_BAR1MPA, 0);
1349 out_le32(mbase + PECFG_BAR2HMPA, 0);
1350 out_le32(mbase + PECFG_BAR2LMPA, 0);
1351
1352 out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE));
1353 out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE));
1354 out_le32(mbase + PECFG_PIMEN, 0x1);
1355
1356 /* Enable I/O, Mem, and Busmaster cycles */
1357 out_le16((u16 *)(mbase + PCI_COMMAND),
1358 in_le16((u16 *)(mbase + PCI_COMMAND)) |
1359 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1360 out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */
1361 out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */
1362
1363 /* Set Class Code to Processor/PPC */
1364 out_le32(mbase + 0x208, 0x0b200001);
1365
1366 attempts = 10;
1367 while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) {
1368 if (!(attempts--)) {
1369 printf("PCIE%d: BME not active\n", port);
1370 return -1;
1371 }
1372 mdelay(1000);
1373 }
1374
1375 printf("PCIE%d: successfully set as endpoint\n", port);
1376
1377 return 0;
1378 }
1379 #endif /* CONFIG_440SPE && CONFIG_PCI */
1380