1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * Configuration and status register (CSR) type definitions for 6 * Octeon fpa. 7 */ 8 9 #ifndef __CVMX_FPA_DEFS_H__ 10 #define __CVMX_FPA_DEFS_H__ 11 12 #define CVMX_FPA_ADDR_RANGE_ERROR CVMX_FPA_ADDR_RANGE_ERROR_FUNC() CVMX_FPA_ADDR_RANGE_ERROR_FUNC(void)13static inline u64 CVMX_FPA_ADDR_RANGE_ERROR_FUNC(void) 14 { 15 switch (cvmx_get_octeon_family()) { 16 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 17 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 18 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 19 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 20 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 21 return 0x0001180028000458ull; 22 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 23 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 24 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 25 return 0x0001280000000458ull; 26 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 27 return 0x0001280000000458ull; 28 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 29 return 0x0001280000000458ull; 30 } 31 return 0x0001280000000458ull; 32 } 33 34 #define CVMX_FPA_AURAX_CFG(offset) (0x0001280020100000ull + ((offset) & 1023) * 8) 35 #define CVMX_FPA_AURAX_CNT(offset) (0x0001280020200000ull + ((offset) & 1023) * 8) 36 #define CVMX_FPA_AURAX_CNT_ADD(offset) (0x0001280020300000ull + ((offset) & 1023) * 8) 37 #define CVMX_FPA_AURAX_CNT_LEVELS(offset) (0x0001280020800000ull + ((offset) & 1023) * 8) 38 #define CVMX_FPA_AURAX_CNT_LIMIT(offset) (0x0001280020400000ull + ((offset) & 1023) * 8) 39 #define CVMX_FPA_AURAX_CNT_THRESHOLD(offset) (0x0001280020500000ull + ((offset) & 1023) * 8) 40 #define CVMX_FPA_AURAX_INT(offset) (0x0001280020600000ull + ((offset) & 1023) * 8) 41 #define CVMX_FPA_AURAX_POOL(offset) (0x0001280020000000ull + ((offset) & 1023) * 8) 42 #define CVMX_FPA_AURAX_POOL_LEVELS(offset) (0x0001280020700000ull + ((offset) & 1023) * 8) 43 #define CVMX_FPA_BIST_STATUS CVMX_FPA_BIST_STATUS_FUNC() CVMX_FPA_BIST_STATUS_FUNC(void)44static inline u64 CVMX_FPA_BIST_STATUS_FUNC(void) 45 { 46 switch (cvmx_get_octeon_family()) { 47 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 48 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 49 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 50 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 51 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 52 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 53 return 0x00011800280000E8ull; 54 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 55 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 56 return 0x00012800000000E8ull; 57 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 58 return 0x00012800000000E8ull; 59 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 60 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 61 return 0x00012800000000E8ull; 62 } 63 return 0x00012800000000E8ull; 64 } 65 66 #ifndef CVMX_FPA_CLK_COUNT // test-only (also in octeon_ddr.h) 67 #define CVMX_FPA_CLK_COUNT (0x00012800000000F0ull) 68 #endif 69 #define CVMX_FPA_CTL_STATUS (0x0001180028000050ull) 70 #define CVMX_FPA_ECC_CTL (0x0001280000000058ull) 71 #define CVMX_FPA_ECC_INT (0x0001280000000068ull) 72 #define CVMX_FPA_ERR_INT (0x0001280000000040ull) 73 #define CVMX_FPA_FPF0_MARKS (0x0001180028000000ull) 74 #define CVMX_FPA_FPF0_SIZE (0x0001180028000058ull) 75 #define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1) 76 #define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2) 77 #define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3) 78 #define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4) 79 #define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5) 80 #define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6) 81 #define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7) 82 #define CVMX_FPA_FPF8_MARKS (0x0001180028000240ull) 83 #define CVMX_FPA_FPF8_SIZE (0x0001180028000248ull) 84 #define CVMX_FPA_FPFX_MARKS(offset) (0x0001180028000008ull + ((offset) & 7) * 8 - 8 * 1) 85 #define CVMX_FPA_FPFX_SIZE(offset) (0x0001180028000060ull + ((offset) & 7) * 8 - 8 * 1) 86 #define CVMX_FPA_GEN_CFG (0x0001280000000050ull) 87 #define CVMX_FPA_INT_ENB (0x0001180028000048ull) 88 #define CVMX_FPA_INT_SUM (0x0001180028000040ull) 89 #define CVMX_FPA_PACKET_THRESHOLD (0x0001180028000460ull) 90 #define CVMX_FPA_POOLX_AVAILABLE(offset) (0x0001280010300000ull + ((offset) & 63) * 8) 91 #define CVMX_FPA_POOLX_CFG(offset) (0x0001280010000000ull + ((offset) & 63) * 8) CVMX_FPA_POOLX_END_ADDR(unsigned long offset)92static inline u64 CVMX_FPA_POOLX_END_ADDR(unsigned long offset) 93 { 94 switch (cvmx_get_octeon_family()) { 95 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 96 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 97 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 98 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 99 return 0x0001180028000358ull + (offset) * 8; 100 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 101 return 0x0001180028000358ull + (offset) * 8; 102 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 103 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 104 return 0x0001280010600000ull + (offset) * 8; 105 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 106 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 107 return 0x0001280010600000ull + (offset) * 8; 108 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 109 return 0x0001280010600000ull + (offset) * 8; 110 } 111 return 0x0001280010600000ull + (offset) * 8; 112 } 113 114 #define CVMX_FPA_POOLX_FPF_MARKS(offset) (0x0001280010100000ull + ((offset) & 63) * 8) 115 #define CVMX_FPA_POOLX_INT(offset) (0x0001280010A00000ull + ((offset) & 63) * 8) 116 #define CVMX_FPA_POOLX_OP_PC(offset) (0x0001280010F00000ull + ((offset) & 63) * 8) 117 #define CVMX_FPA_POOLX_STACK_ADDR(offset) (0x0001280010900000ull + ((offset) & 63) * 8) 118 #define CVMX_FPA_POOLX_STACK_BASE(offset) (0x0001280010700000ull + ((offset) & 63) * 8) 119 #define CVMX_FPA_POOLX_STACK_END(offset) (0x0001280010800000ull + ((offset) & 63) * 8) CVMX_FPA_POOLX_START_ADDR(unsigned long offset)120static inline u64 CVMX_FPA_POOLX_START_ADDR(unsigned long offset) 121 { 122 switch (cvmx_get_octeon_family()) { 123 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 124 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 125 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 126 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 127 return 0x0001180028000258ull + (offset) * 8; 128 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 129 return 0x0001180028000258ull + (offset) * 8; 130 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 131 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 132 return 0x0001280010500000ull + (offset) * 8; 133 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 134 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 135 return 0x0001280010500000ull + (offset) * 8; 136 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 137 return 0x0001280010500000ull + (offset) * 8; 138 } 139 return 0x0001280010500000ull + (offset) * 8; 140 } 141 CVMX_FPA_POOLX_THRESHOLD(unsigned long offset)142static inline u64 CVMX_FPA_POOLX_THRESHOLD(unsigned long offset) 143 { 144 switch (cvmx_get_octeon_family()) { 145 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 146 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 147 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 148 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 149 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 150 return 0x0001180028000140ull + (offset) * 8; 151 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 152 return 0x0001180028000140ull + (offset) * 8; 153 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 154 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 155 return 0x0001280010400000ull + (offset) * 8; 156 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 157 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) 158 return 0x0001280010400000ull + (offset) * 8; 159 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) 160 return 0x0001280010400000ull + (offset) * 8; 161 } 162 return 0x0001280010400000ull + (offset) * 8; 163 } 164 165 #define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0) 166 #define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1) 167 #define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2) 168 #define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3) 169 #define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4) 170 #define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5) 171 #define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6) 172 #define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7) 173 #define CVMX_FPA_QUE8_PAGE_INDEX (0x0001180028000250ull) 174 #define CVMX_FPA_QUEX_AVAILABLE(offset) (0x0001180028000098ull + ((offset) & 15) * 8) 175 #define CVMX_FPA_QUEX_PAGE_INDEX(offset) (0x00011800280000F0ull + ((offset) & 7) * 8) 176 #define CVMX_FPA_QUE_ACT (0x0001180028000138ull) 177 #define CVMX_FPA_QUE_EXP (0x0001180028000130ull) 178 #define CVMX_FPA_RD_LATENCY_PC (0x0001280000000610ull) 179 #define CVMX_FPA_RD_REQ_PC (0x0001280000000600ull) 180 #define CVMX_FPA_RED_DELAY (0x0001280000000100ull) 181 #define CVMX_FPA_SFT_RST (0x0001280000000000ull) 182 #define CVMX_FPA_WART_CTL (0x00011800280000D8ull) 183 #define CVMX_FPA_WART_STATUS (0x00011800280000E0ull) 184 #define CVMX_FPA_WQE_THRESHOLD (0x0001180028000468ull) 185 186 /** 187 * cvmx_fpa_addr_range_error 188 * 189 * When any FPA_POOL()_INT[RANGE] error occurs, this register is latched with additional 190 * error information. 191 */ 192 union cvmx_fpa_addr_range_error { 193 u64 u64; 194 struct cvmx_fpa_addr_range_error_s { 195 u64 reserved_0_63 : 64; 196 } s; 197 struct cvmx_fpa_addr_range_error_cn61xx { 198 u64 reserved_38_63 : 26; 199 u64 pool : 5; 200 u64 addr : 33; 201 } cn61xx; 202 struct cvmx_fpa_addr_range_error_cn61xx cn66xx; 203 struct cvmx_fpa_addr_range_error_cn61xx cn68xx; 204 struct cvmx_fpa_addr_range_error_cn61xx cn68xxp1; 205 struct cvmx_fpa_addr_range_error_cn61xx cn70xx; 206 struct cvmx_fpa_addr_range_error_cn61xx cn70xxp1; 207 struct cvmx_fpa_addr_range_error_cn73xx { 208 u64 reserved_54_63 : 10; 209 u64 pool : 6; 210 u64 reserved_42_47 : 6; 211 u64 addr : 42; 212 } cn73xx; 213 struct cvmx_fpa_addr_range_error_cn73xx cn78xx; 214 struct cvmx_fpa_addr_range_error_cn73xx cn78xxp1; 215 struct cvmx_fpa_addr_range_error_cn61xx cnf71xx; 216 struct cvmx_fpa_addr_range_error_cn73xx cnf75xx; 217 }; 218 219 typedef union cvmx_fpa_addr_range_error cvmx_fpa_addr_range_error_t; 220 221 /** 222 * cvmx_fpa_aura#_cfg 223 * 224 * This register configures aura backpressure, etc. 225 * 226 */ 227 union cvmx_fpa_aurax_cfg { 228 u64 u64; 229 struct cvmx_fpa_aurax_cfg_s { 230 u64 reserved_10_63 : 54; 231 u64 ptr_dis : 1; 232 u64 avg_con : 9; 233 } s; 234 struct cvmx_fpa_aurax_cfg_s cn73xx; 235 struct cvmx_fpa_aurax_cfg_s cn78xx; 236 struct cvmx_fpa_aurax_cfg_s cn78xxp1; 237 struct cvmx_fpa_aurax_cfg_s cnf75xx; 238 }; 239 240 typedef union cvmx_fpa_aurax_cfg cvmx_fpa_aurax_cfg_t; 241 242 /** 243 * cvmx_fpa_aura#_cnt 244 */ 245 union cvmx_fpa_aurax_cnt { 246 u64 u64; 247 struct cvmx_fpa_aurax_cnt_s { 248 u64 reserved_40_63 : 24; 249 u64 cnt : 40; 250 } s; 251 struct cvmx_fpa_aurax_cnt_s cn73xx; 252 struct cvmx_fpa_aurax_cnt_s cn78xx; 253 struct cvmx_fpa_aurax_cnt_s cn78xxp1; 254 struct cvmx_fpa_aurax_cnt_s cnf75xx; 255 }; 256 257 typedef union cvmx_fpa_aurax_cnt cvmx_fpa_aurax_cnt_t; 258 259 /** 260 * cvmx_fpa_aura#_cnt_add 261 */ 262 union cvmx_fpa_aurax_cnt_add { 263 u64 u64; 264 struct cvmx_fpa_aurax_cnt_add_s { 265 u64 reserved_40_63 : 24; 266 u64 cnt : 40; 267 } s; 268 struct cvmx_fpa_aurax_cnt_add_s cn73xx; 269 struct cvmx_fpa_aurax_cnt_add_s cn78xx; 270 struct cvmx_fpa_aurax_cnt_add_s cn78xxp1; 271 struct cvmx_fpa_aurax_cnt_add_s cnf75xx; 272 }; 273 274 typedef union cvmx_fpa_aurax_cnt_add cvmx_fpa_aurax_cnt_add_t; 275 276 /** 277 * cvmx_fpa_aura#_cnt_levels 278 */ 279 union cvmx_fpa_aurax_cnt_levels { 280 u64 u64; 281 struct cvmx_fpa_aurax_cnt_levels_s { 282 u64 reserved_41_63 : 23; 283 u64 drop_dis : 1; 284 u64 bp_ena : 1; 285 u64 red_ena : 1; 286 u64 shift : 6; 287 u64 bp : 8; 288 u64 drop : 8; 289 u64 pass : 8; 290 u64 level : 8; 291 } s; 292 struct cvmx_fpa_aurax_cnt_levels_s cn73xx; 293 struct cvmx_fpa_aurax_cnt_levels_s cn78xx; 294 struct cvmx_fpa_aurax_cnt_levels_s cn78xxp1; 295 struct cvmx_fpa_aurax_cnt_levels_s cnf75xx; 296 }; 297 298 typedef union cvmx_fpa_aurax_cnt_levels cvmx_fpa_aurax_cnt_levels_t; 299 300 /** 301 * cvmx_fpa_aura#_cnt_limit 302 */ 303 union cvmx_fpa_aurax_cnt_limit { 304 u64 u64; 305 struct cvmx_fpa_aurax_cnt_limit_s { 306 u64 reserved_40_63 : 24; 307 u64 limit : 40; 308 } s; 309 struct cvmx_fpa_aurax_cnt_limit_s cn73xx; 310 struct cvmx_fpa_aurax_cnt_limit_s cn78xx; 311 struct cvmx_fpa_aurax_cnt_limit_s cn78xxp1; 312 struct cvmx_fpa_aurax_cnt_limit_s cnf75xx; 313 }; 314 315 typedef union cvmx_fpa_aurax_cnt_limit cvmx_fpa_aurax_cnt_limit_t; 316 317 /** 318 * cvmx_fpa_aura#_cnt_threshold 319 */ 320 union cvmx_fpa_aurax_cnt_threshold { 321 u64 u64; 322 struct cvmx_fpa_aurax_cnt_threshold_s { 323 u64 reserved_40_63 : 24; 324 u64 thresh : 40; 325 } s; 326 struct cvmx_fpa_aurax_cnt_threshold_s cn73xx; 327 struct cvmx_fpa_aurax_cnt_threshold_s cn78xx; 328 struct cvmx_fpa_aurax_cnt_threshold_s cn78xxp1; 329 struct cvmx_fpa_aurax_cnt_threshold_s cnf75xx; 330 }; 331 332 typedef union cvmx_fpa_aurax_cnt_threshold cvmx_fpa_aurax_cnt_threshold_t; 333 334 /** 335 * cvmx_fpa_aura#_int 336 */ 337 union cvmx_fpa_aurax_int { 338 u64 u64; 339 struct cvmx_fpa_aurax_int_s { 340 u64 reserved_1_63 : 63; 341 u64 thresh : 1; 342 } s; 343 struct cvmx_fpa_aurax_int_s cn73xx; 344 struct cvmx_fpa_aurax_int_s cn78xx; 345 struct cvmx_fpa_aurax_int_s cn78xxp1; 346 struct cvmx_fpa_aurax_int_s cnf75xx; 347 }; 348 349 typedef union cvmx_fpa_aurax_int cvmx_fpa_aurax_int_t; 350 351 /** 352 * cvmx_fpa_aura#_pool 353 * 354 * Provides the mapping from each aura to the pool number. 355 * 356 */ 357 union cvmx_fpa_aurax_pool { 358 u64 u64; 359 struct cvmx_fpa_aurax_pool_s { 360 u64 reserved_6_63 : 58; 361 u64 pool : 6; 362 } s; 363 struct cvmx_fpa_aurax_pool_s cn73xx; 364 struct cvmx_fpa_aurax_pool_s cn78xx; 365 struct cvmx_fpa_aurax_pool_s cn78xxp1; 366 struct cvmx_fpa_aurax_pool_s cnf75xx; 367 }; 368 369 typedef union cvmx_fpa_aurax_pool cvmx_fpa_aurax_pool_t; 370 371 /** 372 * cvmx_fpa_aura#_pool_levels 373 */ 374 union cvmx_fpa_aurax_pool_levels { 375 u64 u64; 376 struct cvmx_fpa_aurax_pool_levels_s { 377 u64 reserved_41_63 : 23; 378 u64 drop_dis : 1; 379 u64 bp_ena : 1; 380 u64 red_ena : 1; 381 u64 shift : 6; 382 u64 bp : 8; 383 u64 drop : 8; 384 u64 pass : 8; 385 u64 level : 8; 386 } s; 387 struct cvmx_fpa_aurax_pool_levels_s cn73xx; 388 struct cvmx_fpa_aurax_pool_levels_s cn78xx; 389 struct cvmx_fpa_aurax_pool_levels_s cn78xxp1; 390 struct cvmx_fpa_aurax_pool_levels_s cnf75xx; 391 }; 392 393 typedef union cvmx_fpa_aurax_pool_levels cvmx_fpa_aurax_pool_levels_t; 394 395 /** 396 * cvmx_fpa_bist_status 397 * 398 * This register provides the result of the BIST run on the FPA memories. 399 * 400 */ 401 union cvmx_fpa_bist_status { 402 u64 u64; 403 struct cvmx_fpa_bist_status_s { 404 u64 reserved_0_63 : 64; 405 } s; 406 struct cvmx_fpa_bist_status_cn30xx { 407 u64 reserved_5_63 : 59; 408 u64 frd : 1; 409 u64 fpf0 : 1; 410 u64 fpf1 : 1; 411 u64 ffr : 1; 412 u64 fdr : 1; 413 } cn30xx; 414 struct cvmx_fpa_bist_status_cn30xx cn31xx; 415 struct cvmx_fpa_bist_status_cn30xx cn38xx; 416 struct cvmx_fpa_bist_status_cn30xx cn38xxp2; 417 struct cvmx_fpa_bist_status_cn30xx cn50xx; 418 struct cvmx_fpa_bist_status_cn30xx cn52xx; 419 struct cvmx_fpa_bist_status_cn30xx cn52xxp1; 420 struct cvmx_fpa_bist_status_cn30xx cn56xx; 421 struct cvmx_fpa_bist_status_cn30xx cn56xxp1; 422 struct cvmx_fpa_bist_status_cn30xx cn58xx; 423 struct cvmx_fpa_bist_status_cn30xx cn58xxp1; 424 struct cvmx_fpa_bist_status_cn30xx cn61xx; 425 struct cvmx_fpa_bist_status_cn30xx cn63xx; 426 struct cvmx_fpa_bist_status_cn30xx cn63xxp1; 427 struct cvmx_fpa_bist_status_cn30xx cn66xx; 428 struct cvmx_fpa_bist_status_cn30xx cn68xx; 429 struct cvmx_fpa_bist_status_cn30xx cn68xxp1; 430 struct cvmx_fpa_bist_status_cn30xx cn70xx; 431 struct cvmx_fpa_bist_status_cn30xx cn70xxp1; 432 struct cvmx_fpa_bist_status_cn73xx { 433 u64 reserved_38_63 : 26; 434 u64 status : 38; 435 } cn73xx; 436 struct cvmx_fpa_bist_status_cn73xx cn78xx; 437 struct cvmx_fpa_bist_status_cn73xx cn78xxp1; 438 struct cvmx_fpa_bist_status_cn30xx cnf71xx; 439 struct cvmx_fpa_bist_status_cn73xx cnf75xx; 440 }; 441 442 typedef union cvmx_fpa_bist_status cvmx_fpa_bist_status_t; 443 444 /** 445 * cvmx_fpa_clk_count 446 * 447 * This register counts the number of coprocessor-clock cycles since the deassertion of reset. 448 * 449 */ 450 union cvmx_fpa_clk_count { 451 u64 u64; 452 struct cvmx_fpa_clk_count_s { 453 u64 clk_cnt : 64; 454 } s; 455 struct cvmx_fpa_clk_count_s cn73xx; 456 struct cvmx_fpa_clk_count_s cn78xx; 457 struct cvmx_fpa_clk_count_s cn78xxp1; 458 struct cvmx_fpa_clk_count_s cnf75xx; 459 }; 460 461 typedef union cvmx_fpa_clk_count cvmx_fpa_clk_count_t; 462 463 /** 464 * cvmx_fpa_ctl_status 465 * 466 * The FPA's interrupt enable register. 467 * 468 */ 469 union cvmx_fpa_ctl_status { 470 u64 u64; 471 struct cvmx_fpa_ctl_status_s { 472 u64 reserved_21_63 : 43; 473 u64 free_en : 1; 474 u64 ret_off : 1; 475 u64 req_off : 1; 476 u64 reset : 1; 477 u64 use_ldt : 1; 478 u64 use_stt : 1; 479 u64 enb : 1; 480 u64 mem1_err : 7; 481 u64 mem0_err : 7; 482 } s; 483 struct cvmx_fpa_ctl_status_cn30xx { 484 u64 reserved_18_63 : 46; 485 u64 reset : 1; 486 u64 use_ldt : 1; 487 u64 use_stt : 1; 488 u64 enb : 1; 489 u64 mem1_err : 7; 490 u64 mem0_err : 7; 491 } cn30xx; 492 struct cvmx_fpa_ctl_status_cn30xx cn31xx; 493 struct cvmx_fpa_ctl_status_cn30xx cn38xx; 494 struct cvmx_fpa_ctl_status_cn30xx cn38xxp2; 495 struct cvmx_fpa_ctl_status_cn30xx cn50xx; 496 struct cvmx_fpa_ctl_status_cn30xx cn52xx; 497 struct cvmx_fpa_ctl_status_cn30xx cn52xxp1; 498 struct cvmx_fpa_ctl_status_cn30xx cn56xx; 499 struct cvmx_fpa_ctl_status_cn30xx cn56xxp1; 500 struct cvmx_fpa_ctl_status_cn30xx cn58xx; 501 struct cvmx_fpa_ctl_status_cn30xx cn58xxp1; 502 struct cvmx_fpa_ctl_status_s cn61xx; 503 struct cvmx_fpa_ctl_status_s cn63xx; 504 struct cvmx_fpa_ctl_status_cn30xx cn63xxp1; 505 struct cvmx_fpa_ctl_status_s cn66xx; 506 struct cvmx_fpa_ctl_status_s cn68xx; 507 struct cvmx_fpa_ctl_status_s cn68xxp1; 508 struct cvmx_fpa_ctl_status_s cn70xx; 509 struct cvmx_fpa_ctl_status_s cn70xxp1; 510 struct cvmx_fpa_ctl_status_s cnf71xx; 511 }; 512 513 typedef union cvmx_fpa_ctl_status cvmx_fpa_ctl_status_t; 514 515 /** 516 * cvmx_fpa_ecc_ctl 517 * 518 * This register allows inserting ECC errors for testing. 519 * 520 */ 521 union cvmx_fpa_ecc_ctl { 522 u64 u64; 523 struct cvmx_fpa_ecc_ctl_s { 524 u64 reserved_62_63 : 2; 525 u64 ram_flip1 : 20; 526 u64 reserved_41_41 : 1; 527 u64 ram_flip0 : 20; 528 u64 reserved_20_20 : 1; 529 u64 ram_cdis : 20; 530 } s; 531 struct cvmx_fpa_ecc_ctl_s cn73xx; 532 struct cvmx_fpa_ecc_ctl_s cn78xx; 533 struct cvmx_fpa_ecc_ctl_s cn78xxp1; 534 struct cvmx_fpa_ecc_ctl_s cnf75xx; 535 }; 536 537 typedef union cvmx_fpa_ecc_ctl cvmx_fpa_ecc_ctl_t; 538 539 /** 540 * cvmx_fpa_ecc_int 541 * 542 * This register contains ECC error interrupt summary bits. 543 * 544 */ 545 union cvmx_fpa_ecc_int { 546 u64 u64; 547 struct cvmx_fpa_ecc_int_s { 548 u64 reserved_52_63 : 12; 549 u64 ram_dbe : 20; 550 u64 reserved_20_31 : 12; 551 u64 ram_sbe : 20; 552 } s; 553 struct cvmx_fpa_ecc_int_s cn73xx; 554 struct cvmx_fpa_ecc_int_s cn78xx; 555 struct cvmx_fpa_ecc_int_s cn78xxp1; 556 struct cvmx_fpa_ecc_int_s cnf75xx; 557 }; 558 559 typedef union cvmx_fpa_ecc_int cvmx_fpa_ecc_int_t; 560 561 /** 562 * cvmx_fpa_err_int 563 * 564 * This register contains the global (non-pool) error interrupt summary bits of the FPA. 565 * 566 */ 567 union cvmx_fpa_err_int { 568 u64 u64; 569 struct cvmx_fpa_err_int_s { 570 u64 reserved_4_63 : 60; 571 u64 hw_sub : 1; 572 u64 hw_add : 1; 573 u64 cnt_sub : 1; 574 u64 cnt_add : 1; 575 } s; 576 struct cvmx_fpa_err_int_s cn73xx; 577 struct cvmx_fpa_err_int_s cn78xx; 578 struct cvmx_fpa_err_int_s cn78xxp1; 579 struct cvmx_fpa_err_int_s cnf75xx; 580 }; 581 582 typedef union cvmx_fpa_err_int cvmx_fpa_err_int_t; 583 584 /** 585 * cvmx_fpa_fpf#_marks 586 * 587 * "The high and low watermark register that determines when we write and read free pages from 588 * L2C 589 * for Queue 1. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend 590 * value 591 * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)" 592 */ 593 union cvmx_fpa_fpfx_marks { 594 u64 u64; 595 struct cvmx_fpa_fpfx_marks_s { 596 u64 reserved_22_63 : 42; 597 u64 fpf_wr : 11; 598 u64 fpf_rd : 11; 599 } s; 600 struct cvmx_fpa_fpfx_marks_s cn38xx; 601 struct cvmx_fpa_fpfx_marks_s cn38xxp2; 602 struct cvmx_fpa_fpfx_marks_s cn56xx; 603 struct cvmx_fpa_fpfx_marks_s cn56xxp1; 604 struct cvmx_fpa_fpfx_marks_s cn58xx; 605 struct cvmx_fpa_fpfx_marks_s cn58xxp1; 606 struct cvmx_fpa_fpfx_marks_s cn61xx; 607 struct cvmx_fpa_fpfx_marks_s cn63xx; 608 struct cvmx_fpa_fpfx_marks_s cn63xxp1; 609 struct cvmx_fpa_fpfx_marks_s cn66xx; 610 struct cvmx_fpa_fpfx_marks_s cn68xx; 611 struct cvmx_fpa_fpfx_marks_s cn68xxp1; 612 struct cvmx_fpa_fpfx_marks_s cn70xx; 613 struct cvmx_fpa_fpfx_marks_s cn70xxp1; 614 struct cvmx_fpa_fpfx_marks_s cnf71xx; 615 }; 616 617 typedef union cvmx_fpa_fpfx_marks cvmx_fpa_fpfx_marks_t; 618 619 /** 620 * cvmx_fpa_fpf#_size 621 * 622 * "FPA_FPFX_SIZE = FPA's Queue 1-7 Free Page FIFO Size 623 * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 624 * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 625 * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048." 626 */ 627 union cvmx_fpa_fpfx_size { 628 u64 u64; 629 struct cvmx_fpa_fpfx_size_s { 630 u64 reserved_11_63 : 53; 631 u64 fpf_siz : 11; 632 } s; 633 struct cvmx_fpa_fpfx_size_s cn38xx; 634 struct cvmx_fpa_fpfx_size_s cn38xxp2; 635 struct cvmx_fpa_fpfx_size_s cn56xx; 636 struct cvmx_fpa_fpfx_size_s cn56xxp1; 637 struct cvmx_fpa_fpfx_size_s cn58xx; 638 struct cvmx_fpa_fpfx_size_s cn58xxp1; 639 struct cvmx_fpa_fpfx_size_s cn61xx; 640 struct cvmx_fpa_fpfx_size_s cn63xx; 641 struct cvmx_fpa_fpfx_size_s cn63xxp1; 642 struct cvmx_fpa_fpfx_size_s cn66xx; 643 struct cvmx_fpa_fpfx_size_s cn68xx; 644 struct cvmx_fpa_fpfx_size_s cn68xxp1; 645 struct cvmx_fpa_fpfx_size_s cn70xx; 646 struct cvmx_fpa_fpfx_size_s cn70xxp1; 647 struct cvmx_fpa_fpfx_size_s cnf71xx; 648 }; 649 650 typedef union cvmx_fpa_fpfx_size cvmx_fpa_fpfx_size_t; 651 652 /** 653 * cvmx_fpa_fpf0_marks 654 * 655 * "The high and low watermark register that determines when we write and read free pages from 656 * L2C 657 * for Queue 0. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend 658 * value 659 * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75)" 660 */ 661 union cvmx_fpa_fpf0_marks { 662 u64 u64; 663 struct cvmx_fpa_fpf0_marks_s { 664 u64 reserved_24_63 : 40; 665 u64 fpf_wr : 12; 666 u64 fpf_rd : 12; 667 } s; 668 struct cvmx_fpa_fpf0_marks_s cn38xx; 669 struct cvmx_fpa_fpf0_marks_s cn38xxp2; 670 struct cvmx_fpa_fpf0_marks_s cn56xx; 671 struct cvmx_fpa_fpf0_marks_s cn56xxp1; 672 struct cvmx_fpa_fpf0_marks_s cn58xx; 673 struct cvmx_fpa_fpf0_marks_s cn58xxp1; 674 struct cvmx_fpa_fpf0_marks_s cn61xx; 675 struct cvmx_fpa_fpf0_marks_s cn63xx; 676 struct cvmx_fpa_fpf0_marks_s cn63xxp1; 677 struct cvmx_fpa_fpf0_marks_s cn66xx; 678 struct cvmx_fpa_fpf0_marks_s cn68xx; 679 struct cvmx_fpa_fpf0_marks_s cn68xxp1; 680 struct cvmx_fpa_fpf0_marks_s cn70xx; 681 struct cvmx_fpa_fpf0_marks_s cn70xxp1; 682 struct cvmx_fpa_fpf0_marks_s cnf71xx; 683 }; 684 685 typedef union cvmx_fpa_fpf0_marks cvmx_fpa_fpf0_marks_t; 686 687 /** 688 * cvmx_fpa_fpf0_size 689 * 690 * "The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 691 * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 692 * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048." 693 */ 694 union cvmx_fpa_fpf0_size { 695 u64 u64; 696 struct cvmx_fpa_fpf0_size_s { 697 u64 reserved_12_63 : 52; 698 u64 fpf_siz : 12; 699 } s; 700 struct cvmx_fpa_fpf0_size_s cn38xx; 701 struct cvmx_fpa_fpf0_size_s cn38xxp2; 702 struct cvmx_fpa_fpf0_size_s cn56xx; 703 struct cvmx_fpa_fpf0_size_s cn56xxp1; 704 struct cvmx_fpa_fpf0_size_s cn58xx; 705 struct cvmx_fpa_fpf0_size_s cn58xxp1; 706 struct cvmx_fpa_fpf0_size_s cn61xx; 707 struct cvmx_fpa_fpf0_size_s cn63xx; 708 struct cvmx_fpa_fpf0_size_s cn63xxp1; 709 struct cvmx_fpa_fpf0_size_s cn66xx; 710 struct cvmx_fpa_fpf0_size_s cn68xx; 711 struct cvmx_fpa_fpf0_size_s cn68xxp1; 712 struct cvmx_fpa_fpf0_size_s cn70xx; 713 struct cvmx_fpa_fpf0_size_s cn70xxp1; 714 struct cvmx_fpa_fpf0_size_s cnf71xx; 715 }; 716 717 typedef union cvmx_fpa_fpf0_size cvmx_fpa_fpf0_size_t; 718 719 /** 720 * cvmx_fpa_fpf8_marks 721 * 722 * Reserved through 0x238 for additional thresholds 723 * 724 * FPA_FPF8_MARKS = FPA's Queue 8 Free Page FIFO Read Write Marks 725 * 726 * The high and low watermark register that determines when we write and read free pages from L2C 727 * for Queue 8. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value 728 * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75) 729 */ 730 union cvmx_fpa_fpf8_marks { 731 u64 u64; 732 struct cvmx_fpa_fpf8_marks_s { 733 u64 reserved_22_63 : 42; 734 u64 fpf_wr : 11; 735 u64 fpf_rd : 11; 736 } s; 737 struct cvmx_fpa_fpf8_marks_s cn68xx; 738 struct cvmx_fpa_fpf8_marks_s cn68xxp1; 739 }; 740 741 typedef union cvmx_fpa_fpf8_marks cvmx_fpa_fpf8_marks_t; 742 743 /** 744 * cvmx_fpa_fpf8_size 745 * 746 * FPA_FPF8_SIZE = FPA's Queue 8 Free Page FIFO Size 747 * 748 * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 749 * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 750 * The sum of the 9 (0-8) FPA_FPF#_SIZE registers must be limited to 2048. 751 */ 752 union cvmx_fpa_fpf8_size { 753 u64 u64; 754 struct cvmx_fpa_fpf8_size_s { 755 u64 reserved_12_63 : 52; 756 u64 fpf_siz : 12; 757 } s; 758 struct cvmx_fpa_fpf8_size_s cn68xx; 759 struct cvmx_fpa_fpf8_size_s cn68xxp1; 760 }; 761 762 typedef union cvmx_fpa_fpf8_size cvmx_fpa_fpf8_size_t; 763 764 /** 765 * cvmx_fpa_gen_cfg 766 * 767 * This register provides FPA control and status information. 768 * 769 */ 770 union cvmx_fpa_gen_cfg { 771 u64 u64; 772 struct cvmx_fpa_gen_cfg_s { 773 u64 reserved_12_63 : 52; 774 u64 halfrate : 1; 775 u64 ocla_bp : 1; 776 u64 lvl_dly : 6; 777 u64 pools : 2; 778 u64 avg_en : 1; 779 u64 clk_override : 1; 780 } s; 781 struct cvmx_fpa_gen_cfg_s cn73xx; 782 struct cvmx_fpa_gen_cfg_s cn78xx; 783 struct cvmx_fpa_gen_cfg_s cn78xxp1; 784 struct cvmx_fpa_gen_cfg_s cnf75xx; 785 }; 786 787 typedef union cvmx_fpa_gen_cfg cvmx_fpa_gen_cfg_t; 788 789 /** 790 * cvmx_fpa_int_enb 791 * 792 * The FPA's interrupt enable register. 793 * 794 */ 795 union cvmx_fpa_int_enb { 796 u64 u64; 797 struct cvmx_fpa_int_enb_s { 798 u64 reserved_50_63 : 14; 799 u64 paddr_e : 1; 800 u64 reserved_44_48 : 5; 801 u64 free7 : 1; 802 u64 free6 : 1; 803 u64 free5 : 1; 804 u64 free4 : 1; 805 u64 free3 : 1; 806 u64 free2 : 1; 807 u64 free1 : 1; 808 u64 free0 : 1; 809 u64 pool7th : 1; 810 u64 pool6th : 1; 811 u64 pool5th : 1; 812 u64 pool4th : 1; 813 u64 pool3th : 1; 814 u64 pool2th : 1; 815 u64 pool1th : 1; 816 u64 pool0th : 1; 817 u64 q7_perr : 1; 818 u64 q7_coff : 1; 819 u64 q7_und : 1; 820 u64 q6_perr : 1; 821 u64 q6_coff : 1; 822 u64 q6_und : 1; 823 u64 q5_perr : 1; 824 u64 q5_coff : 1; 825 u64 q5_und : 1; 826 u64 q4_perr : 1; 827 u64 q4_coff : 1; 828 u64 q4_und : 1; 829 u64 q3_perr : 1; 830 u64 q3_coff : 1; 831 u64 q3_und : 1; 832 u64 q2_perr : 1; 833 u64 q2_coff : 1; 834 u64 q2_und : 1; 835 u64 q1_perr : 1; 836 u64 q1_coff : 1; 837 u64 q1_und : 1; 838 u64 q0_perr : 1; 839 u64 q0_coff : 1; 840 u64 q0_und : 1; 841 u64 fed1_dbe : 1; 842 u64 fed1_sbe : 1; 843 u64 fed0_dbe : 1; 844 u64 fed0_sbe : 1; 845 } s; 846 struct cvmx_fpa_int_enb_cn30xx { 847 u64 reserved_28_63 : 36; 848 u64 q7_perr : 1; 849 u64 q7_coff : 1; 850 u64 q7_und : 1; 851 u64 q6_perr : 1; 852 u64 q6_coff : 1; 853 u64 q6_und : 1; 854 u64 q5_perr : 1; 855 u64 q5_coff : 1; 856 u64 q5_und : 1; 857 u64 q4_perr : 1; 858 u64 q4_coff : 1; 859 u64 q4_und : 1; 860 u64 q3_perr : 1; 861 u64 q3_coff : 1; 862 u64 q3_und : 1; 863 u64 q2_perr : 1; 864 u64 q2_coff : 1; 865 u64 q2_und : 1; 866 u64 q1_perr : 1; 867 u64 q1_coff : 1; 868 u64 q1_und : 1; 869 u64 q0_perr : 1; 870 u64 q0_coff : 1; 871 u64 q0_und : 1; 872 u64 fed1_dbe : 1; 873 u64 fed1_sbe : 1; 874 u64 fed0_dbe : 1; 875 u64 fed0_sbe : 1; 876 } cn30xx; 877 struct cvmx_fpa_int_enb_cn30xx cn31xx; 878 struct cvmx_fpa_int_enb_cn30xx cn38xx; 879 struct cvmx_fpa_int_enb_cn30xx cn38xxp2; 880 struct cvmx_fpa_int_enb_cn30xx cn50xx; 881 struct cvmx_fpa_int_enb_cn30xx cn52xx; 882 struct cvmx_fpa_int_enb_cn30xx cn52xxp1; 883 struct cvmx_fpa_int_enb_cn30xx cn56xx; 884 struct cvmx_fpa_int_enb_cn30xx cn56xxp1; 885 struct cvmx_fpa_int_enb_cn30xx cn58xx; 886 struct cvmx_fpa_int_enb_cn30xx cn58xxp1; 887 struct cvmx_fpa_int_enb_cn61xx { 888 u64 reserved_50_63 : 14; 889 u64 paddr_e : 1; 890 u64 res_44 : 5; 891 u64 free7 : 1; 892 u64 free6 : 1; 893 u64 free5 : 1; 894 u64 free4 : 1; 895 u64 free3 : 1; 896 u64 free2 : 1; 897 u64 free1 : 1; 898 u64 free0 : 1; 899 u64 pool7th : 1; 900 u64 pool6th : 1; 901 u64 pool5th : 1; 902 u64 pool4th : 1; 903 u64 pool3th : 1; 904 u64 pool2th : 1; 905 u64 pool1th : 1; 906 u64 pool0th : 1; 907 u64 q7_perr : 1; 908 u64 q7_coff : 1; 909 u64 q7_und : 1; 910 u64 q6_perr : 1; 911 u64 q6_coff : 1; 912 u64 q6_und : 1; 913 u64 q5_perr : 1; 914 u64 q5_coff : 1; 915 u64 q5_und : 1; 916 u64 q4_perr : 1; 917 u64 q4_coff : 1; 918 u64 q4_und : 1; 919 u64 q3_perr : 1; 920 u64 q3_coff : 1; 921 u64 q3_und : 1; 922 u64 q2_perr : 1; 923 u64 q2_coff : 1; 924 u64 q2_und : 1; 925 u64 q1_perr : 1; 926 u64 q1_coff : 1; 927 u64 q1_und : 1; 928 u64 q0_perr : 1; 929 u64 q0_coff : 1; 930 u64 q0_und : 1; 931 u64 fed1_dbe : 1; 932 u64 fed1_sbe : 1; 933 u64 fed0_dbe : 1; 934 u64 fed0_sbe : 1; 935 } cn61xx; 936 struct cvmx_fpa_int_enb_cn63xx { 937 u64 reserved_44_63 : 20; 938 u64 free7 : 1; 939 u64 free6 : 1; 940 u64 free5 : 1; 941 u64 free4 : 1; 942 u64 free3 : 1; 943 u64 free2 : 1; 944 u64 free1 : 1; 945 u64 free0 : 1; 946 u64 pool7th : 1; 947 u64 pool6th : 1; 948 u64 pool5th : 1; 949 u64 pool4th : 1; 950 u64 pool3th : 1; 951 u64 pool2th : 1; 952 u64 pool1th : 1; 953 u64 pool0th : 1; 954 u64 q7_perr : 1; 955 u64 q7_coff : 1; 956 u64 q7_und : 1; 957 u64 q6_perr : 1; 958 u64 q6_coff : 1; 959 u64 q6_und : 1; 960 u64 q5_perr : 1; 961 u64 q5_coff : 1; 962 u64 q5_und : 1; 963 u64 q4_perr : 1; 964 u64 q4_coff : 1; 965 u64 q4_und : 1; 966 u64 q3_perr : 1; 967 u64 q3_coff : 1; 968 u64 q3_und : 1; 969 u64 q2_perr : 1; 970 u64 q2_coff : 1; 971 u64 q2_und : 1; 972 u64 q1_perr : 1; 973 u64 q1_coff : 1; 974 u64 q1_und : 1; 975 u64 q0_perr : 1; 976 u64 q0_coff : 1; 977 u64 q0_und : 1; 978 u64 fed1_dbe : 1; 979 u64 fed1_sbe : 1; 980 u64 fed0_dbe : 1; 981 u64 fed0_sbe : 1; 982 } cn63xx; 983 struct cvmx_fpa_int_enb_cn30xx cn63xxp1; 984 struct cvmx_fpa_int_enb_cn61xx cn66xx; 985 struct cvmx_fpa_int_enb_cn68xx { 986 u64 reserved_50_63 : 14; 987 u64 paddr_e : 1; 988 u64 pool8th : 1; 989 u64 q8_perr : 1; 990 u64 q8_coff : 1; 991 u64 q8_und : 1; 992 u64 free8 : 1; 993 u64 free7 : 1; 994 u64 free6 : 1; 995 u64 free5 : 1; 996 u64 free4 : 1; 997 u64 free3 : 1; 998 u64 free2 : 1; 999 u64 free1 : 1; 1000 u64 free0 : 1; 1001 u64 pool7th : 1; 1002 u64 pool6th : 1; 1003 u64 pool5th : 1; 1004 u64 pool4th : 1; 1005 u64 pool3th : 1; 1006 u64 pool2th : 1; 1007 u64 pool1th : 1; 1008 u64 pool0th : 1; 1009 u64 q7_perr : 1; 1010 u64 q7_coff : 1; 1011 u64 q7_und : 1; 1012 u64 q6_perr : 1; 1013 u64 q6_coff : 1; 1014 u64 q6_und : 1; 1015 u64 q5_perr : 1; 1016 u64 q5_coff : 1; 1017 u64 q5_und : 1; 1018 u64 q4_perr : 1; 1019 u64 q4_coff : 1; 1020 u64 q4_und : 1; 1021 u64 q3_perr : 1; 1022 u64 q3_coff : 1; 1023 u64 q3_und : 1; 1024 u64 q2_perr : 1; 1025 u64 q2_coff : 1; 1026 u64 q2_und : 1; 1027 u64 q1_perr : 1; 1028 u64 q1_coff : 1; 1029 u64 q1_und : 1; 1030 u64 q0_perr : 1; 1031 u64 q0_coff : 1; 1032 u64 q0_und : 1; 1033 u64 fed1_dbe : 1; 1034 u64 fed1_sbe : 1; 1035 u64 fed0_dbe : 1; 1036 u64 fed0_sbe : 1; 1037 } cn68xx; 1038 struct cvmx_fpa_int_enb_cn68xx cn68xxp1; 1039 struct cvmx_fpa_int_enb_cn61xx cn70xx; 1040 struct cvmx_fpa_int_enb_cn61xx cn70xxp1; 1041 struct cvmx_fpa_int_enb_cn61xx cnf71xx; 1042 }; 1043 1044 typedef union cvmx_fpa_int_enb cvmx_fpa_int_enb_t; 1045 1046 /** 1047 * cvmx_fpa_int_sum 1048 * 1049 * Contains the different interrupt summary bits of the FPA. 1050 * 1051 */ 1052 union cvmx_fpa_int_sum { 1053 u64 u64; 1054 struct cvmx_fpa_int_sum_s { 1055 u64 reserved_50_63 : 14; 1056 u64 paddr_e : 1; 1057 u64 pool8th : 1; 1058 u64 q8_perr : 1; 1059 u64 q8_coff : 1; 1060 u64 q8_und : 1; 1061 u64 free8 : 1; 1062 u64 free7 : 1; 1063 u64 free6 : 1; 1064 u64 free5 : 1; 1065 u64 free4 : 1; 1066 u64 free3 : 1; 1067 u64 free2 : 1; 1068 u64 free1 : 1; 1069 u64 free0 : 1; 1070 u64 pool7th : 1; 1071 u64 pool6th : 1; 1072 u64 pool5th : 1; 1073 u64 pool4th : 1; 1074 u64 pool3th : 1; 1075 u64 pool2th : 1; 1076 u64 pool1th : 1; 1077 u64 pool0th : 1; 1078 u64 q7_perr : 1; 1079 u64 q7_coff : 1; 1080 u64 q7_und : 1; 1081 u64 q6_perr : 1; 1082 u64 q6_coff : 1; 1083 u64 q6_und : 1; 1084 u64 q5_perr : 1; 1085 u64 q5_coff : 1; 1086 u64 q5_und : 1; 1087 u64 q4_perr : 1; 1088 u64 q4_coff : 1; 1089 u64 q4_und : 1; 1090 u64 q3_perr : 1; 1091 u64 q3_coff : 1; 1092 u64 q3_und : 1; 1093 u64 q2_perr : 1; 1094 u64 q2_coff : 1; 1095 u64 q2_und : 1; 1096 u64 q1_perr : 1; 1097 u64 q1_coff : 1; 1098 u64 q1_und : 1; 1099 u64 q0_perr : 1; 1100 u64 q0_coff : 1; 1101 u64 q0_und : 1; 1102 u64 fed1_dbe : 1; 1103 u64 fed1_sbe : 1; 1104 u64 fed0_dbe : 1; 1105 u64 fed0_sbe : 1; 1106 } s; 1107 struct cvmx_fpa_int_sum_cn30xx { 1108 u64 reserved_28_63 : 36; 1109 u64 q7_perr : 1; 1110 u64 q7_coff : 1; 1111 u64 q7_und : 1; 1112 u64 q6_perr : 1; 1113 u64 q6_coff : 1; 1114 u64 q6_und : 1; 1115 u64 q5_perr : 1; 1116 u64 q5_coff : 1; 1117 u64 q5_und : 1; 1118 u64 q4_perr : 1; 1119 u64 q4_coff : 1; 1120 u64 q4_und : 1; 1121 u64 q3_perr : 1; 1122 u64 q3_coff : 1; 1123 u64 q3_und : 1; 1124 u64 q2_perr : 1; 1125 u64 q2_coff : 1; 1126 u64 q2_und : 1; 1127 u64 q1_perr : 1; 1128 u64 q1_coff : 1; 1129 u64 q1_und : 1; 1130 u64 q0_perr : 1; 1131 u64 q0_coff : 1; 1132 u64 q0_und : 1; 1133 u64 fed1_dbe : 1; 1134 u64 fed1_sbe : 1; 1135 u64 fed0_dbe : 1; 1136 u64 fed0_sbe : 1; 1137 } cn30xx; 1138 struct cvmx_fpa_int_sum_cn30xx cn31xx; 1139 struct cvmx_fpa_int_sum_cn30xx cn38xx; 1140 struct cvmx_fpa_int_sum_cn30xx cn38xxp2; 1141 struct cvmx_fpa_int_sum_cn30xx cn50xx; 1142 struct cvmx_fpa_int_sum_cn30xx cn52xx; 1143 struct cvmx_fpa_int_sum_cn30xx cn52xxp1; 1144 struct cvmx_fpa_int_sum_cn30xx cn56xx; 1145 struct cvmx_fpa_int_sum_cn30xx cn56xxp1; 1146 struct cvmx_fpa_int_sum_cn30xx cn58xx; 1147 struct cvmx_fpa_int_sum_cn30xx cn58xxp1; 1148 struct cvmx_fpa_int_sum_cn61xx { 1149 u64 reserved_50_63 : 14; 1150 u64 paddr_e : 1; 1151 u64 reserved_44_48 : 5; 1152 u64 free7 : 1; 1153 u64 free6 : 1; 1154 u64 free5 : 1; 1155 u64 free4 : 1; 1156 u64 free3 : 1; 1157 u64 free2 : 1; 1158 u64 free1 : 1; 1159 u64 free0 : 1; 1160 u64 pool7th : 1; 1161 u64 pool6th : 1; 1162 u64 pool5th : 1; 1163 u64 pool4th : 1; 1164 u64 pool3th : 1; 1165 u64 pool2th : 1; 1166 u64 pool1th : 1; 1167 u64 pool0th : 1; 1168 u64 q7_perr : 1; 1169 u64 q7_coff : 1; 1170 u64 q7_und : 1; 1171 u64 q6_perr : 1; 1172 u64 q6_coff : 1; 1173 u64 q6_und : 1; 1174 u64 q5_perr : 1; 1175 u64 q5_coff : 1; 1176 u64 q5_und : 1; 1177 u64 q4_perr : 1; 1178 u64 q4_coff : 1; 1179 u64 q4_und : 1; 1180 u64 q3_perr : 1; 1181 u64 q3_coff : 1; 1182 u64 q3_und : 1; 1183 u64 q2_perr : 1; 1184 u64 q2_coff : 1; 1185 u64 q2_und : 1; 1186 u64 q1_perr : 1; 1187 u64 q1_coff : 1; 1188 u64 q1_und : 1; 1189 u64 q0_perr : 1; 1190 u64 q0_coff : 1; 1191 u64 q0_und : 1; 1192 u64 fed1_dbe : 1; 1193 u64 fed1_sbe : 1; 1194 u64 fed0_dbe : 1; 1195 u64 fed0_sbe : 1; 1196 } cn61xx; 1197 struct cvmx_fpa_int_sum_cn63xx { 1198 u64 reserved_44_63 : 20; 1199 u64 free7 : 1; 1200 u64 free6 : 1; 1201 u64 free5 : 1; 1202 u64 free4 : 1; 1203 u64 free3 : 1; 1204 u64 free2 : 1; 1205 u64 free1 : 1; 1206 u64 free0 : 1; 1207 u64 pool7th : 1; 1208 u64 pool6th : 1; 1209 u64 pool5th : 1; 1210 u64 pool4th : 1; 1211 u64 pool3th : 1; 1212 u64 pool2th : 1; 1213 u64 pool1th : 1; 1214 u64 pool0th : 1; 1215 u64 q7_perr : 1; 1216 u64 q7_coff : 1; 1217 u64 q7_und : 1; 1218 u64 q6_perr : 1; 1219 u64 q6_coff : 1; 1220 u64 q6_und : 1; 1221 u64 q5_perr : 1; 1222 u64 q5_coff : 1; 1223 u64 q5_und : 1; 1224 u64 q4_perr : 1; 1225 u64 q4_coff : 1; 1226 u64 q4_und : 1; 1227 u64 q3_perr : 1; 1228 u64 q3_coff : 1; 1229 u64 q3_und : 1; 1230 u64 q2_perr : 1; 1231 u64 q2_coff : 1; 1232 u64 q2_und : 1; 1233 u64 q1_perr : 1; 1234 u64 q1_coff : 1; 1235 u64 q1_und : 1; 1236 u64 q0_perr : 1; 1237 u64 q0_coff : 1; 1238 u64 q0_und : 1; 1239 u64 fed1_dbe : 1; 1240 u64 fed1_sbe : 1; 1241 u64 fed0_dbe : 1; 1242 u64 fed0_sbe : 1; 1243 } cn63xx; 1244 struct cvmx_fpa_int_sum_cn30xx cn63xxp1; 1245 struct cvmx_fpa_int_sum_cn61xx cn66xx; 1246 struct cvmx_fpa_int_sum_s cn68xx; 1247 struct cvmx_fpa_int_sum_s cn68xxp1; 1248 struct cvmx_fpa_int_sum_cn61xx cn70xx; 1249 struct cvmx_fpa_int_sum_cn61xx cn70xxp1; 1250 struct cvmx_fpa_int_sum_cn61xx cnf71xx; 1251 }; 1252 1253 typedef union cvmx_fpa_int_sum cvmx_fpa_int_sum_t; 1254 1255 /** 1256 * cvmx_fpa_packet_threshold 1257 * 1258 * When the value of FPA_QUE0_AVAILABLE[QUE_SIZ] is Less than the value of this register a low 1259 * pool count signal is sent to the 1260 * PCIe packet instruction engine (to make it stop reading instructions) and to the Packet- 1261 * Arbiter informing it to not give grants 1262 * to packets MAC with the exception of the PCIe MAC. 1263 */ 1264 union cvmx_fpa_packet_threshold { 1265 u64 u64; 1266 struct cvmx_fpa_packet_threshold_s { 1267 u64 reserved_32_63 : 32; 1268 u64 thresh : 32; 1269 } s; 1270 struct cvmx_fpa_packet_threshold_s cn61xx; 1271 struct cvmx_fpa_packet_threshold_s cn63xx; 1272 struct cvmx_fpa_packet_threshold_s cn66xx; 1273 struct cvmx_fpa_packet_threshold_s cn68xx; 1274 struct cvmx_fpa_packet_threshold_s cn68xxp1; 1275 struct cvmx_fpa_packet_threshold_s cn70xx; 1276 struct cvmx_fpa_packet_threshold_s cn70xxp1; 1277 struct cvmx_fpa_packet_threshold_s cnf71xx; 1278 }; 1279 1280 typedef union cvmx_fpa_packet_threshold cvmx_fpa_packet_threshold_t; 1281 1282 /** 1283 * cvmx_fpa_pool#_available 1284 */ 1285 union cvmx_fpa_poolx_available { 1286 u64 u64; 1287 struct cvmx_fpa_poolx_available_s { 1288 u64 reserved_36_63 : 28; 1289 u64 count : 36; 1290 } s; 1291 struct cvmx_fpa_poolx_available_s cn73xx; 1292 struct cvmx_fpa_poolx_available_s cn78xx; 1293 struct cvmx_fpa_poolx_available_s cn78xxp1; 1294 struct cvmx_fpa_poolx_available_s cnf75xx; 1295 }; 1296 1297 typedef union cvmx_fpa_poolx_available cvmx_fpa_poolx_available_t; 1298 1299 /** 1300 * cvmx_fpa_pool#_cfg 1301 */ 1302 union cvmx_fpa_poolx_cfg { 1303 u64 u64; 1304 struct cvmx_fpa_poolx_cfg_s { 1305 u64 reserved_43_63 : 21; 1306 u64 buf_size : 11; 1307 u64 reserved_31_31 : 1; 1308 u64 buf_offset : 15; 1309 u64 reserved_5_15 : 11; 1310 u64 l_type : 2; 1311 u64 s_type : 1; 1312 u64 nat_align : 1; 1313 u64 ena : 1; 1314 } s; 1315 struct cvmx_fpa_poolx_cfg_s cn73xx; 1316 struct cvmx_fpa_poolx_cfg_s cn78xx; 1317 struct cvmx_fpa_poolx_cfg_s cn78xxp1; 1318 struct cvmx_fpa_poolx_cfg_s cnf75xx; 1319 }; 1320 1321 typedef union cvmx_fpa_poolx_cfg cvmx_fpa_poolx_cfg_t; 1322 1323 /** 1324 * cvmx_fpa_pool#_end_addr 1325 * 1326 * Pointers sent to this pool after alignment must be equal to or less than this address. 1327 * 1328 */ 1329 union cvmx_fpa_poolx_end_addr { 1330 u64 u64; 1331 struct cvmx_fpa_poolx_end_addr_s { 1332 u64 reserved_0_63 : 64; 1333 } s; 1334 struct cvmx_fpa_poolx_end_addr_cn61xx { 1335 u64 reserved_33_63 : 31; 1336 u64 addr : 33; 1337 } cn61xx; 1338 struct cvmx_fpa_poolx_end_addr_cn61xx cn66xx; 1339 struct cvmx_fpa_poolx_end_addr_cn61xx cn68xx; 1340 struct cvmx_fpa_poolx_end_addr_cn61xx cn68xxp1; 1341 struct cvmx_fpa_poolx_end_addr_cn61xx cn70xx; 1342 struct cvmx_fpa_poolx_end_addr_cn61xx cn70xxp1; 1343 struct cvmx_fpa_poolx_end_addr_cn73xx { 1344 u64 reserved_42_63 : 22; 1345 u64 addr : 35; 1346 u64 reserved_0_6 : 7; 1347 } cn73xx; 1348 struct cvmx_fpa_poolx_end_addr_cn73xx cn78xx; 1349 struct cvmx_fpa_poolx_end_addr_cn73xx cn78xxp1; 1350 struct cvmx_fpa_poolx_end_addr_cn61xx cnf71xx; 1351 struct cvmx_fpa_poolx_end_addr_cn73xx cnf75xx; 1352 }; 1353 1354 typedef union cvmx_fpa_poolx_end_addr cvmx_fpa_poolx_end_addr_t; 1355 1356 /** 1357 * cvmx_fpa_pool#_fpf_marks 1358 * 1359 * The low watermark register that determines when we read free pages from L2C. 1360 * 1361 */ 1362 union cvmx_fpa_poolx_fpf_marks { 1363 u64 u64; 1364 struct cvmx_fpa_poolx_fpf_marks_s { 1365 u64 reserved_27_63 : 37; 1366 u64 fpf_rd : 11; 1367 u64 reserved_11_15 : 5; 1368 u64 fpf_level : 11; 1369 } s; 1370 struct cvmx_fpa_poolx_fpf_marks_s cn73xx; 1371 struct cvmx_fpa_poolx_fpf_marks_s cn78xx; 1372 struct cvmx_fpa_poolx_fpf_marks_s cn78xxp1; 1373 struct cvmx_fpa_poolx_fpf_marks_s cnf75xx; 1374 }; 1375 1376 typedef union cvmx_fpa_poolx_fpf_marks cvmx_fpa_poolx_fpf_marks_t; 1377 1378 /** 1379 * cvmx_fpa_pool#_int 1380 * 1381 * This register indicates pool interrupts. 1382 * 1383 */ 1384 union cvmx_fpa_poolx_int { 1385 u64 u64; 1386 struct cvmx_fpa_poolx_int_s { 1387 u64 reserved_4_63 : 60; 1388 u64 thresh : 1; 1389 u64 range : 1; 1390 u64 crcerr : 1; 1391 u64 ovfls : 1; 1392 } s; 1393 struct cvmx_fpa_poolx_int_s cn73xx; 1394 struct cvmx_fpa_poolx_int_s cn78xx; 1395 struct cvmx_fpa_poolx_int_s cn78xxp1; 1396 struct cvmx_fpa_poolx_int_s cnf75xx; 1397 }; 1398 1399 typedef union cvmx_fpa_poolx_int cvmx_fpa_poolx_int_t; 1400 1401 /** 1402 * cvmx_fpa_pool#_op_pc 1403 */ 1404 union cvmx_fpa_poolx_op_pc { 1405 u64 u64; 1406 struct cvmx_fpa_poolx_op_pc_s { 1407 u64 count : 64; 1408 } s; 1409 struct cvmx_fpa_poolx_op_pc_s cn73xx; 1410 struct cvmx_fpa_poolx_op_pc_s cn78xx; 1411 struct cvmx_fpa_poolx_op_pc_s cn78xxp1; 1412 struct cvmx_fpa_poolx_op_pc_s cnf75xx; 1413 }; 1414 1415 typedef union cvmx_fpa_poolx_op_pc cvmx_fpa_poolx_op_pc_t; 1416 1417 /** 1418 * cvmx_fpa_pool#_stack_addr 1419 */ 1420 union cvmx_fpa_poolx_stack_addr { 1421 u64 u64; 1422 struct cvmx_fpa_poolx_stack_addr_s { 1423 u64 reserved_42_63 : 22; 1424 u64 addr : 35; 1425 u64 reserved_0_6 : 7; 1426 } s; 1427 struct cvmx_fpa_poolx_stack_addr_s cn73xx; 1428 struct cvmx_fpa_poolx_stack_addr_s cn78xx; 1429 struct cvmx_fpa_poolx_stack_addr_s cn78xxp1; 1430 struct cvmx_fpa_poolx_stack_addr_s cnf75xx; 1431 }; 1432 1433 typedef union cvmx_fpa_poolx_stack_addr cvmx_fpa_poolx_stack_addr_t; 1434 1435 /** 1436 * cvmx_fpa_pool#_stack_base 1437 */ 1438 union cvmx_fpa_poolx_stack_base { 1439 u64 u64; 1440 struct cvmx_fpa_poolx_stack_base_s { 1441 u64 reserved_42_63 : 22; 1442 u64 addr : 35; 1443 u64 reserved_0_6 : 7; 1444 } s; 1445 struct cvmx_fpa_poolx_stack_base_s cn73xx; 1446 struct cvmx_fpa_poolx_stack_base_s cn78xx; 1447 struct cvmx_fpa_poolx_stack_base_s cn78xxp1; 1448 struct cvmx_fpa_poolx_stack_base_s cnf75xx; 1449 }; 1450 1451 typedef union cvmx_fpa_poolx_stack_base cvmx_fpa_poolx_stack_base_t; 1452 1453 /** 1454 * cvmx_fpa_pool#_stack_end 1455 */ 1456 union cvmx_fpa_poolx_stack_end { 1457 u64 u64; 1458 struct cvmx_fpa_poolx_stack_end_s { 1459 u64 reserved_42_63 : 22; 1460 u64 addr : 35; 1461 u64 reserved_0_6 : 7; 1462 } s; 1463 struct cvmx_fpa_poolx_stack_end_s cn73xx; 1464 struct cvmx_fpa_poolx_stack_end_s cn78xx; 1465 struct cvmx_fpa_poolx_stack_end_s cn78xxp1; 1466 struct cvmx_fpa_poolx_stack_end_s cnf75xx; 1467 }; 1468 1469 typedef union cvmx_fpa_poolx_stack_end cvmx_fpa_poolx_stack_end_t; 1470 1471 /** 1472 * cvmx_fpa_pool#_start_addr 1473 * 1474 * Pointers sent to this pool after alignment must be equal to or greater than this address. 1475 * 1476 */ 1477 union cvmx_fpa_poolx_start_addr { 1478 u64 u64; 1479 struct cvmx_fpa_poolx_start_addr_s { 1480 u64 reserved_0_63 : 64; 1481 } s; 1482 struct cvmx_fpa_poolx_start_addr_cn61xx { 1483 u64 reserved_33_63 : 31; 1484 u64 addr : 33; 1485 } cn61xx; 1486 struct cvmx_fpa_poolx_start_addr_cn61xx cn66xx; 1487 struct cvmx_fpa_poolx_start_addr_cn61xx cn68xx; 1488 struct cvmx_fpa_poolx_start_addr_cn61xx cn68xxp1; 1489 struct cvmx_fpa_poolx_start_addr_cn61xx cn70xx; 1490 struct cvmx_fpa_poolx_start_addr_cn61xx cn70xxp1; 1491 struct cvmx_fpa_poolx_start_addr_cn73xx { 1492 u64 reserved_42_63 : 22; 1493 u64 addr : 35; 1494 u64 reserved_0_6 : 7; 1495 } cn73xx; 1496 struct cvmx_fpa_poolx_start_addr_cn73xx cn78xx; 1497 struct cvmx_fpa_poolx_start_addr_cn73xx cn78xxp1; 1498 struct cvmx_fpa_poolx_start_addr_cn61xx cnf71xx; 1499 struct cvmx_fpa_poolx_start_addr_cn73xx cnf75xx; 1500 }; 1501 1502 typedef union cvmx_fpa_poolx_start_addr cvmx_fpa_poolx_start_addr_t; 1503 1504 /** 1505 * cvmx_fpa_pool#_threshold 1506 * 1507 * FPA_POOLX_THRESHOLD = FPA's Pool 0-7 Threshold 1508 * When the value of FPA_QUEX_AVAILABLE is equal to FPA_POOLX_THRESHOLD[THRESH] when a pointer is 1509 * allocated 1510 * or deallocated, set interrupt FPA_INT_SUM[POOLXTH]. 1511 */ 1512 union cvmx_fpa_poolx_threshold { 1513 u64 u64; 1514 struct cvmx_fpa_poolx_threshold_s { 1515 u64 reserved_36_63 : 28; 1516 u64 thresh : 36; 1517 } s; 1518 struct cvmx_fpa_poolx_threshold_cn61xx { 1519 u64 reserved_29_63 : 35; 1520 u64 thresh : 29; 1521 } cn61xx; 1522 struct cvmx_fpa_poolx_threshold_cn61xx cn63xx; 1523 struct cvmx_fpa_poolx_threshold_cn61xx cn66xx; 1524 struct cvmx_fpa_poolx_threshold_cn68xx { 1525 u64 reserved_32_63 : 32; 1526 u64 thresh : 32; 1527 } cn68xx; 1528 struct cvmx_fpa_poolx_threshold_cn68xx cn68xxp1; 1529 struct cvmx_fpa_poolx_threshold_cn61xx cn70xx; 1530 struct cvmx_fpa_poolx_threshold_cn61xx cn70xxp1; 1531 struct cvmx_fpa_poolx_threshold_s cn73xx; 1532 struct cvmx_fpa_poolx_threshold_s cn78xx; 1533 struct cvmx_fpa_poolx_threshold_s cn78xxp1; 1534 struct cvmx_fpa_poolx_threshold_cn61xx cnf71xx; 1535 struct cvmx_fpa_poolx_threshold_s cnf75xx; 1536 }; 1537 1538 typedef union cvmx_fpa_poolx_threshold cvmx_fpa_poolx_threshold_t; 1539 1540 /** 1541 * cvmx_fpa_que#_available 1542 * 1543 * FPA_QUEX_PAGES_AVAILABLE = FPA's Queue 0-7 Free Page Available Register 1544 * The number of page pointers that are available in the FPA and local DRAM. 1545 */ 1546 union cvmx_fpa_quex_available { 1547 u64 u64; 1548 struct cvmx_fpa_quex_available_s { 1549 u64 reserved_32_63 : 32; 1550 u64 que_siz : 32; 1551 } s; 1552 struct cvmx_fpa_quex_available_cn30xx { 1553 u64 reserved_29_63 : 35; 1554 u64 que_siz : 29; 1555 } cn30xx; 1556 struct cvmx_fpa_quex_available_cn30xx cn31xx; 1557 struct cvmx_fpa_quex_available_cn30xx cn38xx; 1558 struct cvmx_fpa_quex_available_cn30xx cn38xxp2; 1559 struct cvmx_fpa_quex_available_cn30xx cn50xx; 1560 struct cvmx_fpa_quex_available_cn30xx cn52xx; 1561 struct cvmx_fpa_quex_available_cn30xx cn52xxp1; 1562 struct cvmx_fpa_quex_available_cn30xx cn56xx; 1563 struct cvmx_fpa_quex_available_cn30xx cn56xxp1; 1564 struct cvmx_fpa_quex_available_cn30xx cn58xx; 1565 struct cvmx_fpa_quex_available_cn30xx cn58xxp1; 1566 struct cvmx_fpa_quex_available_cn30xx cn61xx; 1567 struct cvmx_fpa_quex_available_cn30xx cn63xx; 1568 struct cvmx_fpa_quex_available_cn30xx cn63xxp1; 1569 struct cvmx_fpa_quex_available_cn30xx cn66xx; 1570 struct cvmx_fpa_quex_available_s cn68xx; 1571 struct cvmx_fpa_quex_available_s cn68xxp1; 1572 struct cvmx_fpa_quex_available_cn30xx cn70xx; 1573 struct cvmx_fpa_quex_available_cn30xx cn70xxp1; 1574 struct cvmx_fpa_quex_available_cn30xx cnf71xx; 1575 }; 1576 1577 typedef union cvmx_fpa_quex_available cvmx_fpa_quex_available_t; 1578 1579 /** 1580 * cvmx_fpa_que#_page_index 1581 * 1582 * The present index page for queue 0 of the FPA. 1583 * This number reflects the number of pages of pointers that have been written to memory 1584 * for this queue. 1585 */ 1586 union cvmx_fpa_quex_page_index { 1587 u64 u64; 1588 struct cvmx_fpa_quex_page_index_s { 1589 u64 reserved_25_63 : 39; 1590 u64 pg_num : 25; 1591 } s; 1592 struct cvmx_fpa_quex_page_index_s cn30xx; 1593 struct cvmx_fpa_quex_page_index_s cn31xx; 1594 struct cvmx_fpa_quex_page_index_s cn38xx; 1595 struct cvmx_fpa_quex_page_index_s cn38xxp2; 1596 struct cvmx_fpa_quex_page_index_s cn50xx; 1597 struct cvmx_fpa_quex_page_index_s cn52xx; 1598 struct cvmx_fpa_quex_page_index_s cn52xxp1; 1599 struct cvmx_fpa_quex_page_index_s cn56xx; 1600 struct cvmx_fpa_quex_page_index_s cn56xxp1; 1601 struct cvmx_fpa_quex_page_index_s cn58xx; 1602 struct cvmx_fpa_quex_page_index_s cn58xxp1; 1603 struct cvmx_fpa_quex_page_index_s cn61xx; 1604 struct cvmx_fpa_quex_page_index_s cn63xx; 1605 struct cvmx_fpa_quex_page_index_s cn63xxp1; 1606 struct cvmx_fpa_quex_page_index_s cn66xx; 1607 struct cvmx_fpa_quex_page_index_s cn68xx; 1608 struct cvmx_fpa_quex_page_index_s cn68xxp1; 1609 struct cvmx_fpa_quex_page_index_s cn70xx; 1610 struct cvmx_fpa_quex_page_index_s cn70xxp1; 1611 struct cvmx_fpa_quex_page_index_s cnf71xx; 1612 }; 1613 1614 typedef union cvmx_fpa_quex_page_index cvmx_fpa_quex_page_index_t; 1615 1616 /** 1617 * cvmx_fpa_que8_page_index 1618 * 1619 * FPA_QUE8_PAGE_INDEX = FPA's Queue7 Page Index 1620 * 1621 * The present index page for queue 7 of the FPA. 1622 * This number reflects the number of pages of pointers that have been written to memory 1623 * for this queue. 1624 * Because the address space is 38-bits the number of 128 byte pages could cause this register value to wrap. 1625 */ 1626 union cvmx_fpa_que8_page_index { 1627 u64 u64; 1628 struct cvmx_fpa_que8_page_index_s { 1629 u64 reserved_25_63 : 39; 1630 u64 pg_num : 25; 1631 } s; 1632 struct cvmx_fpa_que8_page_index_s cn68xx; 1633 struct cvmx_fpa_que8_page_index_s cn68xxp1; 1634 }; 1635 1636 typedef union cvmx_fpa_que8_page_index cvmx_fpa_que8_page_index_t; 1637 1638 /** 1639 * cvmx_fpa_que_act 1640 * 1641 * "When a INT_SUM[PERR#] occurs this will be latched with the value read from L2C. 1642 * This is latched on the first error and will not latch again unitl all errors are cleared." 1643 */ 1644 union cvmx_fpa_que_act { 1645 u64 u64; 1646 struct cvmx_fpa_que_act_s { 1647 u64 reserved_29_63 : 35; 1648 u64 act_que : 3; 1649 u64 act_indx : 26; 1650 } s; 1651 struct cvmx_fpa_que_act_s cn30xx; 1652 struct cvmx_fpa_que_act_s cn31xx; 1653 struct cvmx_fpa_que_act_s cn38xx; 1654 struct cvmx_fpa_que_act_s cn38xxp2; 1655 struct cvmx_fpa_que_act_s cn50xx; 1656 struct cvmx_fpa_que_act_s cn52xx; 1657 struct cvmx_fpa_que_act_s cn52xxp1; 1658 struct cvmx_fpa_que_act_s cn56xx; 1659 struct cvmx_fpa_que_act_s cn56xxp1; 1660 struct cvmx_fpa_que_act_s cn58xx; 1661 struct cvmx_fpa_que_act_s cn58xxp1; 1662 struct cvmx_fpa_que_act_s cn61xx; 1663 struct cvmx_fpa_que_act_s cn63xx; 1664 struct cvmx_fpa_que_act_s cn63xxp1; 1665 struct cvmx_fpa_que_act_s cn66xx; 1666 struct cvmx_fpa_que_act_s cn68xx; 1667 struct cvmx_fpa_que_act_s cn68xxp1; 1668 struct cvmx_fpa_que_act_s cn70xx; 1669 struct cvmx_fpa_que_act_s cn70xxp1; 1670 struct cvmx_fpa_que_act_s cnf71xx; 1671 }; 1672 1673 typedef union cvmx_fpa_que_act cvmx_fpa_que_act_t; 1674 1675 /** 1676 * cvmx_fpa_que_exp 1677 * 1678 * "When a INT_SUM[PERR#] occurs this will be latched with the expected value. 1679 * This is latched on the first error and will not latch again unitl all errors are cleared." 1680 */ 1681 union cvmx_fpa_que_exp { 1682 u64 u64; 1683 struct cvmx_fpa_que_exp_s { 1684 u64 reserved_29_63 : 35; 1685 u64 exp_que : 3; 1686 u64 exp_indx : 26; 1687 } s; 1688 struct cvmx_fpa_que_exp_s cn30xx; 1689 struct cvmx_fpa_que_exp_s cn31xx; 1690 struct cvmx_fpa_que_exp_s cn38xx; 1691 struct cvmx_fpa_que_exp_s cn38xxp2; 1692 struct cvmx_fpa_que_exp_s cn50xx; 1693 struct cvmx_fpa_que_exp_s cn52xx; 1694 struct cvmx_fpa_que_exp_s cn52xxp1; 1695 struct cvmx_fpa_que_exp_s cn56xx; 1696 struct cvmx_fpa_que_exp_s cn56xxp1; 1697 struct cvmx_fpa_que_exp_s cn58xx; 1698 struct cvmx_fpa_que_exp_s cn58xxp1; 1699 struct cvmx_fpa_que_exp_s cn61xx; 1700 struct cvmx_fpa_que_exp_s cn63xx; 1701 struct cvmx_fpa_que_exp_s cn63xxp1; 1702 struct cvmx_fpa_que_exp_s cn66xx; 1703 struct cvmx_fpa_que_exp_s cn68xx; 1704 struct cvmx_fpa_que_exp_s cn68xxp1; 1705 struct cvmx_fpa_que_exp_s cn70xx; 1706 struct cvmx_fpa_que_exp_s cn70xxp1; 1707 struct cvmx_fpa_que_exp_s cnf71xx; 1708 }; 1709 1710 typedef union cvmx_fpa_que_exp cvmx_fpa_que_exp_t; 1711 1712 /** 1713 * cvmx_fpa_rd_latency_pc 1714 */ 1715 union cvmx_fpa_rd_latency_pc { 1716 u64 u64; 1717 struct cvmx_fpa_rd_latency_pc_s { 1718 u64 count : 64; 1719 } s; 1720 struct cvmx_fpa_rd_latency_pc_s cn73xx; 1721 struct cvmx_fpa_rd_latency_pc_s cn78xx; 1722 struct cvmx_fpa_rd_latency_pc_s cn78xxp1; 1723 struct cvmx_fpa_rd_latency_pc_s cnf75xx; 1724 }; 1725 1726 typedef union cvmx_fpa_rd_latency_pc cvmx_fpa_rd_latency_pc_t; 1727 1728 /** 1729 * cvmx_fpa_rd_req_pc 1730 */ 1731 union cvmx_fpa_rd_req_pc { 1732 u64 u64; 1733 struct cvmx_fpa_rd_req_pc_s { 1734 u64 count : 64; 1735 } s; 1736 struct cvmx_fpa_rd_req_pc_s cn73xx; 1737 struct cvmx_fpa_rd_req_pc_s cn78xx; 1738 struct cvmx_fpa_rd_req_pc_s cn78xxp1; 1739 struct cvmx_fpa_rd_req_pc_s cnf75xx; 1740 }; 1741 1742 typedef union cvmx_fpa_rd_req_pc cvmx_fpa_rd_req_pc_t; 1743 1744 /** 1745 * cvmx_fpa_red_delay 1746 */ 1747 union cvmx_fpa_red_delay { 1748 u64 u64; 1749 struct cvmx_fpa_red_delay_s { 1750 u64 reserved_14_63 : 50; 1751 u64 avg_dly : 14; 1752 } s; 1753 struct cvmx_fpa_red_delay_s cn73xx; 1754 struct cvmx_fpa_red_delay_s cn78xx; 1755 struct cvmx_fpa_red_delay_s cn78xxp1; 1756 struct cvmx_fpa_red_delay_s cnf75xx; 1757 }; 1758 1759 typedef union cvmx_fpa_red_delay cvmx_fpa_red_delay_t; 1760 1761 /** 1762 * cvmx_fpa_sft_rst 1763 * 1764 * Allows soft reset. 1765 * 1766 */ 1767 union cvmx_fpa_sft_rst { 1768 u64 u64; 1769 struct cvmx_fpa_sft_rst_s { 1770 u64 busy : 1; 1771 u64 reserved_1_62 : 62; 1772 u64 rst : 1; 1773 } s; 1774 struct cvmx_fpa_sft_rst_s cn73xx; 1775 struct cvmx_fpa_sft_rst_s cn78xx; 1776 struct cvmx_fpa_sft_rst_s cn78xxp1; 1777 struct cvmx_fpa_sft_rst_s cnf75xx; 1778 }; 1779 1780 typedef union cvmx_fpa_sft_rst cvmx_fpa_sft_rst_t; 1781 1782 /** 1783 * cvmx_fpa_wart_ctl 1784 * 1785 * FPA_WART_CTL = FPA's WART Control 1786 * 1787 * Control and status for the WART block. 1788 */ 1789 union cvmx_fpa_wart_ctl { 1790 u64 u64; 1791 struct cvmx_fpa_wart_ctl_s { 1792 u64 reserved_16_63 : 48; 1793 u64 ctl : 16; 1794 } s; 1795 struct cvmx_fpa_wart_ctl_s cn30xx; 1796 struct cvmx_fpa_wart_ctl_s cn31xx; 1797 struct cvmx_fpa_wart_ctl_s cn38xx; 1798 struct cvmx_fpa_wart_ctl_s cn38xxp2; 1799 struct cvmx_fpa_wart_ctl_s cn50xx; 1800 struct cvmx_fpa_wart_ctl_s cn52xx; 1801 struct cvmx_fpa_wart_ctl_s cn52xxp1; 1802 struct cvmx_fpa_wart_ctl_s cn56xx; 1803 struct cvmx_fpa_wart_ctl_s cn56xxp1; 1804 struct cvmx_fpa_wart_ctl_s cn58xx; 1805 struct cvmx_fpa_wart_ctl_s cn58xxp1; 1806 }; 1807 1808 typedef union cvmx_fpa_wart_ctl cvmx_fpa_wart_ctl_t; 1809 1810 /** 1811 * cvmx_fpa_wart_status 1812 * 1813 * FPA_WART_STATUS = FPA's WART Status 1814 * 1815 * Control and status for the WART block. 1816 */ 1817 union cvmx_fpa_wart_status { 1818 u64 u64; 1819 struct cvmx_fpa_wart_status_s { 1820 u64 reserved_32_63 : 32; 1821 u64 status : 32; 1822 } s; 1823 struct cvmx_fpa_wart_status_s cn30xx; 1824 struct cvmx_fpa_wart_status_s cn31xx; 1825 struct cvmx_fpa_wart_status_s cn38xx; 1826 struct cvmx_fpa_wart_status_s cn38xxp2; 1827 struct cvmx_fpa_wart_status_s cn50xx; 1828 struct cvmx_fpa_wart_status_s cn52xx; 1829 struct cvmx_fpa_wart_status_s cn52xxp1; 1830 struct cvmx_fpa_wart_status_s cn56xx; 1831 struct cvmx_fpa_wart_status_s cn56xxp1; 1832 struct cvmx_fpa_wart_status_s cn58xx; 1833 struct cvmx_fpa_wart_status_s cn58xxp1; 1834 }; 1835 1836 typedef union cvmx_fpa_wart_status cvmx_fpa_wart_status_t; 1837 1838 /** 1839 * cvmx_fpa_wqe_threshold 1840 * 1841 * "When the value of FPA_QUE#_AVAILABLE[QUE_SIZ] (\# is determined by the value of 1842 * IPD_WQE_FPA_QUEUE) is Less than the value of this 1843 * register a low pool count signal is sent to the PCIe packet instruction engine (to make it 1844 * stop reading instructions) and to the 1845 * Packet-Arbiter informing it to not give grants to packets MAC with the exception of the PCIe 1846 * MAC." 1847 */ 1848 union cvmx_fpa_wqe_threshold { 1849 u64 u64; 1850 struct cvmx_fpa_wqe_threshold_s { 1851 u64 reserved_32_63 : 32; 1852 u64 thresh : 32; 1853 } s; 1854 struct cvmx_fpa_wqe_threshold_s cn61xx; 1855 struct cvmx_fpa_wqe_threshold_s cn63xx; 1856 struct cvmx_fpa_wqe_threshold_s cn66xx; 1857 struct cvmx_fpa_wqe_threshold_s cn68xx; 1858 struct cvmx_fpa_wqe_threshold_s cn68xxp1; 1859 struct cvmx_fpa_wqe_threshold_s cn70xx; 1860 struct cvmx_fpa_wqe_threshold_s cn70xxp1; 1861 struct cvmx_fpa_wqe_threshold_s cnf71xx; 1862 }; 1863 1864 typedef union cvmx_fpa_wqe_threshold cvmx_fpa_wqe_threshold_t; 1865 1866 #endif 1867