1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * From Coreboot src/southbridge/intel/bd82x6x/early_me.c
4 *
5 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <log.h>
12 #include <sysreset.h>
13 #include <asm/pci.h>
14 #include <asm/cpu.h>
15 #include <asm/processor.h>
16 #include <asm/arch/me.h>
17 #include <asm/arch/pch.h>
18 #include <asm/io.h>
19 #include <linux/delay.h>
20
21 static const char *const me_ack_values[] = {
22 [ME_HFS_ACK_NO_DID] = "No DID Ack received",
23 [ME_HFS_ACK_RESET] = "Non-power cycle reset",
24 [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
25 [ME_HFS_ACK_S3] = "Go to S3",
26 [ME_HFS_ACK_S4] = "Go to S4",
27 [ME_HFS_ACK_S5] = "Go to S5",
28 [ME_HFS_ACK_GBL_RESET] = "Global Reset",
29 [ME_HFS_ACK_CONTINUE] = "Continue to boot"
30 };
31
intel_early_me_init(struct udevice * me_dev)32 int intel_early_me_init(struct udevice *me_dev)
33 {
34 int count;
35 struct me_uma uma;
36 struct me_hfs hfs;
37
38 debug("Intel ME early init\n");
39
40 /* Wait for ME UMA SIZE VALID bit to be set */
41 for (count = ME_RETRY; count > 0; --count) {
42 pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
43 if (uma.valid)
44 break;
45 udelay(ME_DELAY);
46 }
47 if (!count) {
48 printf("ERROR: ME is not ready!\n");
49 return -EBUSY;
50 }
51
52 /* Check for valid firmware */
53 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
54 if (hfs.fpt_bad) {
55 printf("WARNING: ME has bad firmware\n");
56 return -EBADF;
57 }
58
59 debug("Intel ME firmware is ready\n");
60
61 return 0;
62 }
63
intel_early_me_uma_size(struct udevice * me_dev)64 int intel_early_me_uma_size(struct udevice *me_dev)
65 {
66 struct me_uma uma;
67
68 pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
69 if (uma.valid) {
70 debug("ME: Requested %uMB UMA\n", uma.size);
71 return uma.size;
72 }
73
74 debug("ME: Invalid UMA size\n");
75 return -EINVAL;
76 }
77
set_global_reset(struct udevice * dev,int enable)78 static inline void set_global_reset(struct udevice *dev, int enable)
79 {
80 u32 etr3;
81
82 dm_pci_read_config32(dev, ETR3, &etr3);
83
84 /* Clear CF9 Without Resume Well Reset Enable */
85 etr3 &= ~ETR3_CWORWRE;
86
87 /* CF9GR indicates a Global Reset */
88 if (enable)
89 etr3 |= ETR3_CF9GR;
90 else
91 etr3 &= ~ETR3_CF9GR;
92
93 dm_pci_write_config32(dev, ETR3, etr3);
94 }
95
intel_early_me_init_done(struct udevice * dev,struct udevice * me_dev,uint status)96 int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
97 uint status)
98 {
99 int count;
100 u32 mebase_l, mebase_h;
101 struct me_hfs hfs;
102 struct me_did did = {
103 .init_done = ME_INIT_DONE,
104 .status = status
105 };
106
107 /* MEBASE from MESEG_BASE[35:20] */
108 dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L, &mebase_l);
109 dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H, &mebase_h);
110 mebase_h &= 0xf;
111 did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
112
113 /* Send message to ME */
114 debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n",
115 status, did.uma_base);
116
117 pci_write_dword_ptr(me_dev, &did, PCI_ME_H_GS);
118
119 /* Must wait for ME acknowledgement */
120 for (count = ME_RETRY; count > 0; --count) {
121 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
122 if (hfs.bios_msg_ack)
123 break;
124 udelay(ME_DELAY);
125 }
126 if (!count) {
127 printf("ERROR: ME failed to respond\n");
128 return -ETIMEDOUT;
129 }
130
131 /* Return the requested BIOS action */
132 debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
133
134 /* Check status after acknowledgement */
135 intel_me_status(me_dev);
136
137 switch (hfs.ack_data) {
138 case ME_HFS_ACK_CONTINUE:
139 /* Continue to boot */
140 return 0;
141 case ME_HFS_ACK_RESET:
142 /* Non-power cycle reset */
143 set_global_reset(dev, 0);
144 sysreset_walk_halt(SYSRESET_COLD);
145 break;
146 case ME_HFS_ACK_PWR_CYCLE:
147 /* Power cycle reset */
148 set_global_reset(dev, 0);
149 sysreset_walk_halt(SYSRESET_COLD);
150 break;
151 case ME_HFS_ACK_GBL_RESET:
152 /* Global reset */
153 set_global_reset(dev, 1);
154 sysreset_walk_halt(SYSRESET_COLD);
155 break;
156 case ME_HFS_ACK_S3:
157 case ME_HFS_ACK_S4:
158 case ME_HFS_ACK_S5:
159 break;
160 }
161
162 return -EINVAL;
163 }
164
165 static const struct udevice_id ivybridge_syscon_ids[] = {
166 { .compatible = "intel,me", .data = X86_SYSCON_ME },
167 { }
168 };
169
170 U_BOOT_DRIVER(syscon_intel_me) = {
171 .name = "intel_me_syscon",
172 .id = UCLASS_SYSCON,
173 .of_match = ivybridge_syscon_ids,
174 };
175