1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * MUSB OTG driver register defines
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
8 */
9
10 #ifndef __MUSB_REGS_H__
11 #define __MUSB_REGS_H__
12
13 #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
14
15 /*
16 * MUSB Register bits
17 */
18
19 /* POWER */
20 #define MUSB_POWER_ISOUPDATE 0x80
21 #define MUSB_POWER_SOFTCONN 0x40
22 #define MUSB_POWER_HSENAB 0x20
23 #define MUSB_POWER_HSMODE 0x10
24 #define MUSB_POWER_RESET 0x08
25 #define MUSB_POWER_RESUME 0x04
26 #define MUSB_POWER_SUSPENDM 0x02
27 #define MUSB_POWER_ENSUSPEND 0x01
28
29 /* INTRUSB */
30 #define MUSB_INTR_SUSPEND 0x01
31 #define MUSB_INTR_RESUME 0x02
32 #define MUSB_INTR_RESET 0x04
33 #define MUSB_INTR_BABBLE 0x04
34 #define MUSB_INTR_SOF 0x08
35 #define MUSB_INTR_CONNECT 0x10
36 #define MUSB_INTR_DISCONNECT 0x20
37 #define MUSB_INTR_SESSREQ 0x40
38 #define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */
39
40 /* DEVCTL */
41 #define MUSB_DEVCTL_BDEVICE 0x80
42 #define MUSB_DEVCTL_FSDEV 0x40
43 #define MUSB_DEVCTL_LSDEV 0x20
44 #define MUSB_DEVCTL_VBUS 0x18
45 #define MUSB_DEVCTL_VBUS_SHIFT 3
46 #define MUSB_DEVCTL_HM 0x04
47 #define MUSB_DEVCTL_HR 0x02
48 #define MUSB_DEVCTL_SESSION 0x01
49
50 /* MUSB ULPI VBUSCONTROL */
51 #define MUSB_ULPI_USE_EXTVBUS 0x01
52 #define MUSB_ULPI_USE_EXTVBUSIND 0x02
53 /* ULPI_REG_CONTROL */
54 #define MUSB_ULPI_REG_REQ (1 << 0)
55 #define MUSB_ULPI_REG_CMPLT (1 << 1)
56 #define MUSB_ULPI_RDN_WR (1 << 2)
57
58 /* TESTMODE */
59 #define MUSB_TEST_FORCE_HOST 0x80
60 #define MUSB_TEST_FIFO_ACCESS 0x40
61 #define MUSB_TEST_FORCE_FS 0x20
62 #define MUSB_TEST_FORCE_HS 0x10
63 #define MUSB_TEST_PACKET 0x08
64 #define MUSB_TEST_K 0x04
65 #define MUSB_TEST_J 0x02
66 #define MUSB_TEST_SE0_NAK 0x01
67
68 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
69 #define MUSB_FIFOSZ_DPB 0x10
70 /* Allocation size (8, 16, 32, ... 4096) */
71 #define MUSB_FIFOSZ_SIZE 0x0f
72
73 /* CSR0 */
74 #define MUSB_CSR0_FLUSHFIFO 0x0100
75 #define MUSB_CSR0_TXPKTRDY 0x0002
76 #define MUSB_CSR0_RXPKTRDY 0x0001
77
78 /* CSR0 in Peripheral mode */
79 #define MUSB_CSR0_P_SVDSETUPEND 0x0080
80 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
81 #define MUSB_CSR0_P_SENDSTALL 0x0020
82 #define MUSB_CSR0_P_SETUPEND 0x0010
83 #define MUSB_CSR0_P_DATAEND 0x0008
84 #define MUSB_CSR0_P_SENTSTALL 0x0004
85
86 /* CSR0 in Host mode */
87 #define MUSB_CSR0_H_DIS_PING 0x0800
88 #define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */
89 #define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */
90 #define MUSB_CSR0_H_NAKTIMEOUT 0x0080
91 #define MUSB_CSR0_H_STATUSPKT 0x0040
92 #define MUSB_CSR0_H_REQPKT 0x0020
93 #define MUSB_CSR0_H_ERROR 0x0010
94 #define MUSB_CSR0_H_SETUPPKT 0x0008
95 #define MUSB_CSR0_H_RXSTALL 0x0004
96
97 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
98 #define MUSB_CSR0_P_WZC_BITS \
99 (MUSB_CSR0_P_SENTSTALL)
100 #define MUSB_CSR0_H_WZC_BITS \
101 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
102 | MUSB_CSR0_RXPKTRDY)
103
104 /* TxType/RxType */
105 #define MUSB_TYPE_SPEED 0xc0
106 #define MUSB_TYPE_SPEED_SHIFT 6
107 #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
108 #define MUSB_TYPE_PROTO_SHIFT 4
109 #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
110
111 /* CONFIGDATA */
112 #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
113 #define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
114 #define MUSB_CONFIGDATA_BIGENDIAN 0x20
115 #define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
116 #define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
117 #define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
118 #define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
119 #define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
120
121 /* TXCSR in Peripheral and Host mode */
122 #define MUSB_TXCSR_AUTOSET 0x8000
123 #define MUSB_TXCSR_DMAENAB 0x1000
124 #define MUSB_TXCSR_FRCDATATOG 0x0800
125 #define MUSB_TXCSR_DMAMODE 0x0400
126 #define MUSB_TXCSR_CLRDATATOG 0x0040
127 #define MUSB_TXCSR_FLUSHFIFO 0x0008
128 #define MUSB_TXCSR_FIFONOTEMPTY 0x0002
129 #define MUSB_TXCSR_TXPKTRDY 0x0001
130
131 /* TXCSR in Peripheral mode */
132 #define MUSB_TXCSR_P_ISO 0x4000
133 #define MUSB_TXCSR_P_INCOMPTX 0x0080
134 #define MUSB_TXCSR_P_SENTSTALL 0x0020
135 #define MUSB_TXCSR_P_SENDSTALL 0x0010
136 #define MUSB_TXCSR_P_UNDERRUN 0x0004
137
138 /* TXCSR in Host mode */
139 #define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200
140 #define MUSB_TXCSR_H_DATATOGGLE 0x0100
141 #define MUSB_TXCSR_H_NAKTIMEOUT 0x0080
142 #define MUSB_TXCSR_H_RXSTALL 0x0020
143 #define MUSB_TXCSR_H_ERROR 0x0004
144
145 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
146 #define MUSB_TXCSR_P_WZC_BITS \
147 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
148 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
149 #define MUSB_TXCSR_H_WZC_BITS \
150 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
151 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
152
153 /* RXCSR in Peripheral and Host mode */
154 #define MUSB_RXCSR_AUTOCLEAR 0x8000
155 #define MUSB_RXCSR_DMAENAB 0x2000
156 #define MUSB_RXCSR_DISNYET 0x1000
157 #define MUSB_RXCSR_PID_ERR 0x1000
158 #define MUSB_RXCSR_DMAMODE 0x0800
159 #define MUSB_RXCSR_INCOMPRX 0x0100
160 #define MUSB_RXCSR_CLRDATATOG 0x0080
161 #define MUSB_RXCSR_FLUSHFIFO 0x0010
162 #define MUSB_RXCSR_DATAERROR 0x0008
163 #define MUSB_RXCSR_FIFOFULL 0x0002
164 #define MUSB_RXCSR_RXPKTRDY 0x0001
165
166 /* RXCSR in Peripheral mode */
167 #define MUSB_RXCSR_P_ISO 0x4000
168 #define MUSB_RXCSR_P_SENTSTALL 0x0040
169 #define MUSB_RXCSR_P_SENDSTALL 0x0020
170 #define MUSB_RXCSR_P_OVERRUN 0x0004
171
172 /* RXCSR in Host mode */
173 #define MUSB_RXCSR_H_AUTOREQ 0x4000
174 #define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400
175 #define MUSB_RXCSR_H_DATATOGGLE 0x0200
176 #define MUSB_RXCSR_H_RXSTALL 0x0040
177 #define MUSB_RXCSR_H_REQPKT 0x0020
178 #define MUSB_RXCSR_H_ERROR 0x0004
179
180 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
181 #define MUSB_RXCSR_P_WZC_BITS \
182 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
183 | MUSB_RXCSR_RXPKTRDY)
184 #define MUSB_RXCSR_H_WZC_BITS \
185 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
186 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
187
188 /* HUBADDR */
189 #define MUSB_HUBADDR_MULTI_TT 0x80
190
191
192 /* SUNXI has different reg addresses, but identical r/w functions */
193 #ifndef CONFIG_ARCH_SUNXI
194
195 /*
196 * Common USB registers
197 */
198
199 #define MUSB_FADDR 0x00 /* 8-bit */
200 #define MUSB_POWER 0x01 /* 8-bit */
201
202 #define MUSB_INTRTX 0x02 /* 16-bit */
203 #define MUSB_INTRRX 0x04
204 #define MUSB_INTRTXE 0x06
205 #define MUSB_INTRRXE 0x08
206 #define MUSB_INTRUSB 0x0A /* 8 bit */
207 #define MUSB_INTRUSBE 0x0B /* 8 bit */
208 #define MUSB_FRAME 0x0C
209 #define MUSB_INDEX 0x0E /* 8 bit */
210 #define MUSB_TESTMODE 0x0F /* 8 bit */
211
212 /* Get offset for a given FIFO from musb->mregs */
213 #if defined(CONFIG_USB_MUSB_TUSB6010) || \
214 defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
215 #define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
216 #else
217 #define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4))
218 #endif
219
220 /*
221 * Additional Control Registers
222 */
223
224 #define MUSB_DEVCTL 0x60 /* 8 bit */
225
226 /* These are always controlled through the INDEX register */
227 #define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
228 #define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
229 #define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
230 #define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
231
232 /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
233 #define MUSB_HWVERS 0x6C /* 8 bit */
234 #define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */
235 #define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */
236 #define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */
237 #define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */
238 #define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */
239 #define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */
240 #define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */
241
242 #define MUSB_EPINFO 0x78 /* 8 bit */
243 #define MUSB_RAMINFO 0x79 /* 8 bit */
244 #define MUSB_LINKINFO 0x7a /* 8 bit */
245 #define MUSB_VPLEN 0x7b /* 8 bit */
246 #define MUSB_HS_EOF1 0x7c /* 8 bit */
247 #define MUSB_FS_EOF1 0x7d /* 8 bit */
248 #define MUSB_LS_EOF1 0x7e /* 8 bit */
249
250 /* Offsets to endpoint registers */
251 #define MUSB_TXMAXP 0x00
252 #define MUSB_TXCSR 0x02
253 #define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
254 #define MUSB_RXMAXP 0x04
255 #define MUSB_RXCSR 0x06
256 #define MUSB_RXCOUNT 0x08
257 #define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
258 #define MUSB_TXTYPE 0x0A
259 #define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
260 #define MUSB_TXINTERVAL 0x0B
261 #define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
262 #define MUSB_RXTYPE 0x0C
263 #define MUSB_RXINTERVAL 0x0D
264 #define MUSB_FIFOSIZE 0x0F
265 #define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
266
267 /* Offsets to endpoint registers in indexed model (using INDEX register) */
268 #define MUSB_INDEXED_OFFSET(_epnum, _offset) \
269 (0x10 + (_offset))
270
271 /* Offsets to endpoint registers in flat models */
272 #define MUSB_FLAT_OFFSET(_epnum, _offset) \
273 (0x100 + (0x10*(_epnum)) + (_offset))
274
275 #if defined(CONFIG_USB_MUSB_TUSB6010) || \
276 defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
277 /* TUSB6010 EP0 configuration register is special */
278 #define MUSB_TUSB_OFFSET(_epnum, _offset) \
279 (0x10 + _offset)
280 #include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
281 #endif
282
283 #define MUSB_TXCSR_MODE 0x2000
284
285 /* "bus control"/target registers, for host side multipoint (external hubs) */
286 #define MUSB_TXFUNCADDR 0x00
287 #define MUSB_TXHUBADDR 0x02
288 #define MUSB_TXHUBPORT 0x03
289
290 #define MUSB_RXFUNCADDR 0x04
291 #define MUSB_RXHUBADDR 0x06
292 #define MUSB_RXHUBPORT 0x07
293
294 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
295 (0x80 + (8*(_epnum)) + (_offset))
296
297 #else /* CONFIG_ARCH_SUNXI */
298
299 /*
300 * Common USB registers
301 */
302
303 #define MUSB_FADDR 0x0098
304 #define MUSB_POWER 0x0040
305
306 #define MUSB_INTRTX 0x0044
307 #define MUSB_INTRRX 0x0046
308 #define MUSB_INTRTXE 0x0048
309 #define MUSB_INTRRXE 0x004A
310 #define MUSB_INTRUSB 0x004C
311 #define MUSB_INTRUSBE 0x0050
312 #define MUSB_FRAME 0x0054
313 #define MUSB_INDEX 0x0042
314 #define MUSB_TESTMODE 0x007C
315
316 /* Get offset for a given FIFO from musb->mregs */
317 #define MUSB_FIFO_OFFSET(epnum) (0x00 + ((epnum) * 4))
318
319 /*
320 * Additional Control Registers
321 */
322
323 #define MUSB_DEVCTL 0x0041
324
325 /* These are always controlled through the INDEX register */
326 #define MUSB_TXFIFOSZ 0x0090
327 #define MUSB_RXFIFOSZ 0x0094
328 #define MUSB_TXFIFOADD 0x0092
329 #define MUSB_RXFIFOADD 0x0096
330
331 #define MUSB_EPINFO 0x0078
332 #define MUSB_RAMINFO 0x0079
333 #define MUSB_LINKINFO 0x007A
334 #define MUSB_VPLEN 0x007B
335 #define MUSB_HS_EOF1 0x007C
336 #define MUSB_FS_EOF1 0x007D
337 #define MUSB_LS_EOF1 0x007E
338
339 /* Offsets to endpoint registers */
340 #define MUSB_TXMAXP 0x0080
341 #define MUSB_TXCSR 0x0082
342 #define MUSB_CSR0 0x0082
343 #define MUSB_RXMAXP 0x0084
344 #define MUSB_RXCSR 0x0086
345 #define MUSB_RXCOUNT 0x0088
346 #define MUSB_COUNT0 0x0088
347 #define MUSB_TXTYPE 0x008C
348 #define MUSB_TYPE0 0x008C
349 #define MUSB_TXINTERVAL 0x008D
350 #define MUSB_NAKLIMIT0 0x008D
351 #define MUSB_RXTYPE 0x008E
352 #define MUSB_RXINTERVAL 0x008F
353
354 #define MUSB_CONFIGDATA 0x00b0 /* musb_read_configdata adds 0x10 ! */
355 #define MUSB_FIFOSIZE 0x0090
356
357 /* Offsets to endpoint registers in indexed model (using INDEX register) */
358 #define MUSB_INDEXED_OFFSET(_epnum, _offset) (_offset)
359
360 #define MUSB_TXCSR_MODE 0x2000
361
362 /* "bus control"/target registers, for host side multipoint (external hubs) */
363 #define MUSB_TXFUNCADDR 0x0098
364 #define MUSB_TXHUBADDR 0x009A
365 #define MUSB_TXHUBPORT 0x009B
366
367 #define MUSB_RXFUNCADDR 0x009C
368 #define MUSB_RXHUBADDR 0x009E
369 #define MUSB_RXHUBPORT 0x009F
370
371 /* Endpoint is selected with MUSB_INDEX. */
372 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) (_offset)
373
374 #endif /* CONFIG_ARCH_SUNXI */
375
musb_write_txfifosz(void __iomem * mbase,u8 c_size)376 static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
377 {
378 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
379 }
380
musb_write_txfifoadd(void __iomem * mbase,u16 c_off)381 static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
382 {
383 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
384 }
385
musb_write_rxfifosz(void __iomem * mbase,u8 c_size)386 static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
387 {
388 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
389 }
390
musb_write_rxfifoadd(void __iomem * mbase,u16 c_off)391 static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
392 {
393 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
394 }
395
musb_write_ulpi_buscontrol(void __iomem * mbase,u8 val)396 static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
397 {
398 #ifndef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */
399 musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
400 #endif
401 }
402
musb_read_txfifosz(void __iomem * mbase)403 static inline u8 musb_read_txfifosz(void __iomem *mbase)
404 {
405 return musb_readb(mbase, MUSB_TXFIFOSZ);
406 }
407
musb_read_txfifoadd(void __iomem * mbase)408 static inline u16 musb_read_txfifoadd(void __iomem *mbase)
409 {
410 return musb_readw(mbase, MUSB_TXFIFOADD);
411 }
412
musb_read_rxfifosz(void __iomem * mbase)413 static inline u8 musb_read_rxfifosz(void __iomem *mbase)
414 {
415 return musb_readb(mbase, MUSB_RXFIFOSZ);
416 }
417
musb_read_rxfifoadd(void __iomem * mbase)418 static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
419 {
420 return musb_readw(mbase, MUSB_RXFIFOADD);
421 }
422
musb_read_ulpi_buscontrol(void __iomem * mbase)423 static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
424 {
425 #ifdef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */
426 return 0;
427 #else
428 return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
429 #endif
430 }
431
musb_read_configdata(void __iomem * mbase)432 static inline u8 musb_read_configdata(void __iomem *mbase)
433 {
434 #ifdef CONFIG_USB_MUSB_FIXED_CONFIGDATA
435 /* <Sigh> allwinner saves a reg, and we need to hardcode this */
436 return 0xde;
437 #else
438 musb_writeb(mbase, MUSB_INDEX, 0);
439 return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
440 #endif
441 }
442
musb_read_hwvers(void __iomem * mbase)443 static inline u16 musb_read_hwvers(void __iomem *mbase)
444 {
445 #ifdef CONFIG_ARCH_SUNXI
446 return 0; /* Unknown version */
447 #else
448 return musb_readw(mbase, MUSB_HWVERS);
449 #endif
450 }
451
musb_read_target_reg_base(u8 i,void __iomem * mbase)452 static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
453 {
454 return (MUSB_BUSCTL_OFFSET(i, 0) + mbase);
455 }
456
musb_write_rxfunaddr(void __iomem * ep_target_regs,u8 qh_addr_reg)457 static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
458 u8 qh_addr_reg)
459 {
460 musb_writeb(ep_target_regs, MUSB_RXFUNCADDR, qh_addr_reg);
461 }
462
musb_write_rxhubaddr(void __iomem * ep_target_regs,u8 qh_h_addr_reg)463 static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
464 u8 qh_h_addr_reg)
465 {
466 musb_writeb(ep_target_regs, MUSB_RXHUBADDR, qh_h_addr_reg);
467 }
468
musb_write_rxhubport(void __iomem * ep_target_regs,u8 qh_h_port_reg)469 static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
470 u8 qh_h_port_reg)
471 {
472 musb_writeb(ep_target_regs, MUSB_RXHUBPORT, qh_h_port_reg);
473 }
474
musb_write_txfunaddr(void __iomem * mbase,u8 epnum,u8 qh_addr_reg)475 static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
476 u8 qh_addr_reg)
477 {
478 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
479 qh_addr_reg);
480 }
481
musb_write_txhubaddr(void __iomem * mbase,u8 epnum,u8 qh_addr_reg)482 static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
483 u8 qh_addr_reg)
484 {
485 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
486 qh_addr_reg);
487 }
488
musb_write_txhubport(void __iomem * mbase,u8 epnum,u8 qh_h_port_reg)489 static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
490 u8 qh_h_port_reg)
491 {
492 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
493 qh_h_port_reg);
494 }
495
musb_read_rxfunaddr(void __iomem * mbase,u8 epnum)496 static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
497 {
498 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXFUNCADDR));
499 }
500
musb_read_rxhubaddr(void __iomem * mbase,u8 epnum)501 static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
502 {
503 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBADDR));
504 }
505
musb_read_rxhubport(void __iomem * mbase,u8 epnum)506 static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
507 {
508 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBPORT));
509 }
510
musb_read_txfunaddr(void __iomem * mbase,u8 epnum)511 static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
512 {
513 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR));
514 }
515
musb_read_txhubaddr(void __iomem * mbase,u8 epnum)516 static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
517 {
518 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR));
519 }
520
musb_read_txhubport(void __iomem * mbase,u8 epnum)521 static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
522 {
523 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT));
524 }
525
526 #endif /* __MUSB_REGS_H__ */
527