1 /******************************************************************************* 2 3 Intel(R) 82576 Virtual Function Linux driver 4 Copyright(c) 1999 - 2008 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 FILE_LICENCE ( GPL2_ONLY ); 30 31 #ifndef _IGBVF_VF_H_ 32 #define _IGBVF_VF_H_ 33 34 #include <stddef.h> 35 #include <stdint.h> 36 #include <stdlib.h> 37 #include <stdio.h> 38 #include <string.h> 39 #include <unistd.h> 40 #include <byteswap.h> 41 #include <errno.h> 42 #include <ipxe/pci.h> 43 #include <ipxe/malloc.h> 44 #include <ipxe/if_ether.h> 45 #include <ipxe/io.h> 46 #include <ipxe/ethernet.h> 47 #include <ipxe/iobuf.h> 48 #include <ipxe/netdevice.h> 49 50 #include "igbvf_osdep.h" 51 #include "igbvf_regs.h" 52 #include "igbvf_defines.h" 53 54 struct e1000_hw; 55 56 #define E1000_DEV_ID_82576_VF 0x10CA 57 #define E1000_DEV_ID_I350_VF 0x1520 58 59 #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 60 61 /* Additional Descriptor Control definitions */ 62 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 63 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ 64 65 /* SRRCTL bit definitions */ 66 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 67 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 68 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 69 #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 70 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 71 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 72 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 73 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 74 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 75 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 76 #define E1000_SRRCTL_DROP_EN 0x80000000 77 78 #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F 79 #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 80 81 /* Interrupt Defines */ 82 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 83 #define E1000_EITR(_n) (0x01680 + ((_n) << 2)) 84 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ 85 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 86 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 87 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 88 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 89 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ 90 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ 91 #define E1000_IVAR_VALID 0x80 92 93 /* Receive Descriptor - Advanced */ 94 union e1000_adv_rx_desc { 95 struct { 96 u64 pkt_addr; /* Packet buffer address */ 97 u64 hdr_addr; /* Header buffer address */ 98 } read; 99 struct { 100 struct { 101 union { 102 u32 data; 103 struct { 104 u16 pkt_info; /* RSS type, Packet type */ 105 u16 hdr_info; /* Split Header, 106 * header buffer length */ 107 } hs_rss; 108 } lo_dword; 109 union { 110 u32 rss; /* RSS Hash */ 111 struct { 112 u16 ip_id; /* IP id */ 113 u16 csum; /* Packet Checksum */ 114 } csum_ip; 115 } hi_dword; 116 } lower; 117 struct { 118 u32 status_error; /* ext status/error */ 119 u16 length; /* Packet length */ 120 u16 vlan; /* VLAN tag */ 121 } upper; 122 } wb; /* writeback */ 123 }; 124 125 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 126 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 127 128 /* Transmit Descriptor - Advanced */ 129 union e1000_adv_tx_desc { 130 struct { 131 u64 buffer_addr; /* Address of descriptor's data buf */ 132 u32 cmd_type_len; 133 u32 olinfo_status; 134 } read; 135 struct { 136 u64 rsvd; /* Reserved */ 137 u32 nxtseq_seed; 138 u32 status; 139 } wb; 140 }; 141 142 /* Adv Transmit Descriptor Config Masks */ 143 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 144 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 145 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 146 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 147 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 148 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 149 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 150 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 151 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 152 153 /* Context descriptors */ 154 struct e1000_adv_tx_context_desc { 155 u32 vlan_macip_lens; 156 u32 seqnum_seed; 157 u32 type_tucmd_mlhl; 158 u32 mss_l4len_idx; 159 }; 160 161 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 162 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 163 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 164 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 165 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 166 167 enum e1000_mac_type { 168 e1000_undefined = 0, 169 e1000_vfadapt, 170 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 171 }; 172 173 struct e1000_vf_stats { 174 u64 base_gprc; 175 u64 base_gptc; 176 u64 base_gorc; 177 u64 base_gotc; 178 u64 base_mprc; 179 u64 base_gotlbc; 180 u64 base_gptlbc; 181 u64 base_gorlbc; 182 u64 base_gprlbc; 183 184 u32 last_gprc; 185 u32 last_gptc; 186 u32 last_gorc; 187 u32 last_gotc; 188 u32 last_mprc; 189 u32 last_gotlbc; 190 u32 last_gptlbc; 191 u32 last_gorlbc; 192 u32 last_gprlbc; 193 194 u64 gprc; 195 u64 gptc; 196 u64 gorc; 197 u64 gotc; 198 u64 mprc; 199 u64 gotlbc; 200 u64 gptlbc; 201 u64 gorlbc; 202 u64 gprlbc; 203 }; 204 205 #include "igbvf_mbx.h" 206 207 struct e1000_mac_operations { 208 /* Function pointers for the MAC. */ 209 s32 (*init_params)(struct e1000_hw *); 210 s32 (*check_for_link)(struct e1000_hw *); 211 void (*clear_vfta)(struct e1000_hw *); 212 s32 (*get_bus_info)(struct e1000_hw *); 213 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 214 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 215 s32 (*reset_hw)(struct e1000_hw *); 216 s32 (*init_hw)(struct e1000_hw *); 217 s32 (*setup_link)(struct e1000_hw *); 218 void (*write_vfta)(struct e1000_hw *, u32, u32); 219 void (*mta_set)(struct e1000_hw *, u32); 220 void (*rar_set)(struct e1000_hw *, u8*, u32); 221 s32 (*read_mac_addr)(struct e1000_hw *); 222 }; 223 224 struct e1000_mac_info { 225 struct e1000_mac_operations ops; 226 u8 addr[6]; 227 u8 perm_addr[6]; 228 229 enum e1000_mac_type type; 230 231 u16 mta_reg_count; 232 u16 rar_entry_count; 233 234 bool get_link_status; 235 }; 236 237 enum e1000_bus_type { 238 e1000_bus_type_unknown = 0, 239 e1000_bus_type_pci, 240 e1000_bus_type_pcix, 241 e1000_bus_type_pci_express, 242 e1000_bus_type_reserved 243 }; 244 245 enum e1000_bus_speed { 246 e1000_bus_speed_unknown = 0, 247 e1000_bus_speed_33, 248 e1000_bus_speed_66, 249 e1000_bus_speed_100, 250 e1000_bus_speed_120, 251 e1000_bus_speed_133, 252 e1000_bus_speed_2500, 253 e1000_bus_speed_5000, 254 e1000_bus_speed_reserved 255 }; 256 257 enum e1000_bus_width { 258 e1000_bus_width_unknown = 0, 259 e1000_bus_width_pcie_x1, 260 e1000_bus_width_pcie_x2, 261 e1000_bus_width_pcie_x4 = 4, 262 e1000_bus_width_pcie_x8 = 8, 263 e1000_bus_width_32, 264 e1000_bus_width_64, 265 e1000_bus_width_reserved 266 }; 267 268 struct e1000_bus_info { 269 enum e1000_bus_type type; 270 enum e1000_bus_speed speed; 271 enum e1000_bus_width width; 272 273 u16 func; 274 u16 pci_cmd_word; 275 }; 276 277 struct e1000_mbx_operations { 278 s32 (*init_params)(struct e1000_hw *hw); 279 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 280 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 281 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 282 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 283 s32 (*check_for_msg)(struct e1000_hw *, u16); 284 s32 (*check_for_ack)(struct e1000_hw *, u16); 285 s32 (*check_for_rst)(struct e1000_hw *, u16); 286 }; 287 288 struct e1000_mbx_stats { 289 u32 msgs_tx; 290 u32 msgs_rx; 291 292 u32 acks; 293 u32 reqs; 294 u32 rsts; 295 }; 296 297 struct e1000_mbx_info { 298 struct e1000_mbx_operations ops; 299 struct e1000_mbx_stats stats; 300 u32 timeout; 301 u32 usec_delay; 302 u16 size; 303 }; 304 305 struct e1000_dev_spec_vf { 306 u32 vf_number; 307 u32 v2p_mailbox; 308 }; 309 310 struct e1000_hw { 311 void *back; 312 313 u8 __iomem *hw_addr; 314 u8 __iomem *flash_address; 315 unsigned long io_base; 316 317 struct e1000_mac_info mac; 318 struct e1000_bus_info bus; 319 struct e1000_mbx_info mbx; 320 321 union { 322 struct e1000_dev_spec_vf vf; 323 } dev_spec; 324 325 u16 device_id; 326 u16 subsystem_vendor_id; 327 u16 subsystem_device_id; 328 u16 vendor_id; 329 330 u8 revision_id; 331 }; 332 333 enum e1000_promisc_type { 334 e1000_promisc_disabled = 0, /* all promisc modes disabled */ 335 e1000_promisc_unicast = 1, /* unicast promiscuous enabled */ 336 e1000_promisc_multicast = 2, /* multicast promiscuous enabled */ 337 e1000_promisc_enabled = 3, /* both uni and multicast promisc */ 338 e1000_num_promisc_types 339 }; 340 341 /* These functions must be implemented by drivers */ 342 s32 igbvf_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 343 void igbvf_vfta_set_vf(struct e1000_hw *, u16, bool); 344 void igbvf_rlpml_set_vf(struct e1000_hw *, u16); 345 s32 igbvf_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type); 346 #endif /* _IGBVF_VF_H_ */ 347