1 /************************************************* -*- linux-c -*- 2 * Myricom 10Gb Network Interface Card Software 3 * Copyright 2005-2010, Myricom, Inc. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 17 * 02110-1301, USA. 18 ****************************************************************/ 19 20 FILE_LICENCE ( GPL2_ONLY ); 21 22 #ifndef _myri10ge_mcp_h 23 #define _myri10ge_mcp_h 24 25 #define MXGEFW_VERSION_MAJOR 1 26 #define MXGEFW_VERSION_MINOR 4 27 28 #ifdef MXGEFW 29 #ifndef _stdint_h_ 30 typedef signed char int8_t; 31 typedef signed short int16_t; 32 typedef signed int int32_t; 33 typedef signed long long int64_t; 34 typedef unsigned char uint8_t; 35 typedef unsigned short uint16_t; 36 typedef unsigned int uint32_t; 37 typedef unsigned long long uint64_t; 38 #endif 39 #endif 40 41 /* 8 Bytes */ 42 struct mcp_dma_addr { 43 uint32_t high; 44 uint32_t low; 45 }; 46 typedef struct mcp_dma_addr mcp_dma_addr_t; 47 48 /* 4 Bytes */ 49 struct mcp_slot { 50 uint16_t checksum; 51 uint16_t length; 52 }; 53 typedef struct mcp_slot mcp_slot_t; 54 55 #ifdef MXGEFW_NDIS 56 /* 8-byte descriptor, exclusively used by NDIS drivers. */ 57 struct mcp_slot_8 { 58 /* Place hash value at the top so it gets written before length. 59 * The driver polls length. 60 */ 61 uint32_t hash; 62 uint16_t checksum; 63 uint16_t length; 64 }; 65 typedef struct mcp_slot_8 mcp_slot_8_t; 66 67 /* Two bits of length in mcp_slot are used to indicate hash type. */ 68 #define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 69 #define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 70 #define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 71 #define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 72 #endif 73 74 /* 64 Bytes */ 75 struct mcp_cmd { 76 uint32_t cmd; 77 uint32_t data0; /* will be low portion if data > 32 bits */ 78 /* 8 */ 79 uint32_t data1; /* will be high portion if data > 32 bits */ 80 uint32_t data2; /* currently unused.. */ 81 /* 16 */ 82 struct mcp_dma_addr response_addr; 83 /* 24 */ 84 uint32_t pad[10]; 85 }; 86 typedef struct mcp_cmd mcp_cmd_t; 87 88 /* 8 Bytes */ 89 struct mcp_cmd_response { 90 uint32_t data; 91 uint32_t result; 92 }; 93 typedef struct mcp_cmd_response mcp_cmd_response_t; 94 95 96 97 /* 98 flags used in mcp_kreq_ether_send_t: 99 100 The SMALL flag is only needed in the first segment. It is raised 101 for packets that are total less or equal 512 bytes. 102 103 The CKSUM flag must be set in all segments. 104 105 The PADDED flags is set if the packet needs to be padded, and it 106 must be set for all segments. 107 108 The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 109 length of all previous segments was odd. 110 */ 111 112 113 #define MXGEFW_FLAGS_SMALL 0x1 114 #define MXGEFW_FLAGS_TSO_HDR 0x1 115 #define MXGEFW_FLAGS_FIRST 0x2 116 #define MXGEFW_FLAGS_ALIGN_ODD 0x4 117 #define MXGEFW_FLAGS_CKSUM 0x8 118 #define MXGEFW_FLAGS_TSO_LAST 0x8 119 #define MXGEFW_FLAGS_NO_TSO 0x10 120 #define MXGEFW_FLAGS_TSO_CHOP 0x10 121 #define MXGEFW_FLAGS_TSO_PLD 0x20 122 123 #define MXGEFW_SEND_SMALL_SIZE 1520 124 #define MXGEFW_MAX_MTU 9400 125 126 union mcp_pso_or_cumlen { 127 uint16_t pseudo_hdr_offset; 128 uint16_t cum_len; 129 }; 130 typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 131 132 #define MXGEFW_MAX_SEND_DESC 12 133 #define MXGEFW_PAD 2 134 135 /* 16 Bytes */ 136 struct mcp_kreq_ether_send { 137 uint32_t addr_high; 138 uint32_t addr_low; 139 uint16_t pseudo_hdr_offset; 140 uint16_t length; 141 uint8_t pad; 142 uint8_t rdma_count; 143 uint8_t cksum_offset; /* where to start computing cksum */ 144 uint8_t flags; /* as defined above */ 145 }; 146 typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 147 148 /* 8 Bytes */ 149 struct mcp_kreq_ether_recv { 150 uint32_t addr_high; 151 uint32_t addr_low; 152 }; 153 typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 154 155 156 /* Commands */ 157 158 #define MXGEFW_BOOT_HANDOFF 0xfc0000 159 #define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 160 161 #define MXGEFW_ETH_CMD 0xf80000 162 #define MXGEFW_ETH_SEND_4 0x200000 163 #define MXGEFW_ETH_SEND_1 0x240000 164 #define MXGEFW_ETH_SEND_2 0x280000 165 #define MXGEFW_ETH_SEND_3 0x2c0000 166 #define MXGEFW_ETH_RECV_SMALL 0x300000 167 #define MXGEFW_ETH_RECV_BIG 0x340000 168 #define MXGEFW_ETH_SEND_GO 0x380000 169 #define MXGEFW_ETH_SEND_STOP 0x3C0000 170 171 #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 172 #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 173 174 enum myri10ge_mcp_cmd_type { 175 MXGEFW_CMD_NONE = 0, 176 /* Reset the mcp, it is left in a safe state, waiting 177 for the driver to set all its parameters */ 178 MXGEFW_CMD_RESET = 1, 179 180 /* get the version number of the current firmware.. 181 (may be available in the eeprom strings..? */ 182 MXGEFW_GET_MCP_VERSION = 2, 183 184 185 /* Parameters which must be set by the driver before it can 186 issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 187 MXGEFW_CMD_RESET is issued */ 188 189 MXGEFW_CMD_SET_INTRQ_DMA = 3, 190 /* data0 = LSW of the host address 191 * data1 = MSW of the host address 192 * data2 = slice number if multiple slices are used 193 */ 194 195 MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */ 196 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */ 197 198 199 /* Parameters which refer to lanai SRAM addresses where the 200 driver must issue PIO writes for various things */ 201 202 MXGEFW_CMD_GET_SEND_OFFSET = 6, 203 MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7, 204 MXGEFW_CMD_GET_BIG_RX_OFFSET = 8, 205 /* data0 = slice number if multiple slices are used */ 206 207 MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9, 208 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10, 209 210 /* Parameters which refer to rings stored on the MCP, 211 and whose size is controlled by the mcp */ 212 213 MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */ 214 MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */ 215 216 /* Parameters which refer to rings stored in the host, 217 and whose size is controlled by the host. Note that 218 all must be physically contiguous and must contain 219 a power of 2 number of entries. */ 220 221 MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ 222 #define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31) 223 224 /* command to bring ethernet interface up. Above parameters 225 (plus mtu & mac address) must have been exchanged prior 226 to issuing this command */ 227 MXGEFW_CMD_ETHERNET_UP = 14, 228 229 /* command to bring ethernet interface down. No further sends 230 or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 231 is issued, and all interrupt queues must be flushed prior 232 to ack'ing this command */ 233 234 MXGEFW_CMD_ETHERNET_DOWN = 15, 235 236 /* commands the driver may issue live, without resetting 237 the nic. Note that increasing the mtu "live" should 238 only be done if the driver has already supplied buffers 239 sufficiently large to handle the new mtu. Decreasing 240 the mtu live is safe */ 241 242 MXGEFW_CMD_SET_MTU = 16, 243 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */ 244 MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */ 245 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */ 246 247 MXGEFW_ENABLE_PROMISC = 20, 248 MXGEFW_DISABLE_PROMISC = 21, 249 MXGEFW_SET_MAC_ADDRESS = 22, 250 251 MXGEFW_ENABLE_FLOW_CONTROL = 23, 252 MXGEFW_DISABLE_FLOW_CONTROL = 24, 253 254 /* do a DMA test 255 data0,data1 = DMA address 256 data2 = RDMA length (MSH), WDMA length (LSH) 257 command return data = repetitions (MSH), 0.5-ms ticks (LSH) 258 */ 259 MXGEFW_DMA_TEST = 25, 260 261 MXGEFW_ENABLE_ALLMULTI = 26, 262 MXGEFW_DISABLE_ALLMULTI = 27, 263 264 /* returns MXGEFW_CMD_ERROR_MULTICAST 265 if there is no room in the cache 266 data0,MSH(data1) = multicast group address */ 267 MXGEFW_JOIN_MULTICAST_GROUP = 28, 268 /* returns MXGEFW_CMD_ERROR_MULTICAST 269 if the address is not in the cache, 270 or is equal to FF-FF-FF-FF-FF-FF 271 data0,MSH(data1) = multicast group address */ 272 MXGEFW_LEAVE_MULTICAST_GROUP = 29, 273 MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30, 274 275 MXGEFW_CMD_SET_STATS_DMA_V2 = 31, 276 /* data0, data1 = bus addr, 277 * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 278 * adding new stuff to mcp_irq_data without changing the ABI 279 * 280 * If multiple slices are used, data2 contains both the size of the 281 * structure (in the lower 16 bits) and the slice number 282 * (in the upper 16 bits). 283 */ 284 285 MXGEFW_CMD_UNALIGNED_TEST = 32, 286 /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 287 chipset */ 288 289 MXGEFW_CMD_UNALIGNED_STATUS = 33, 290 /* return data = boolean, true if the chipset is known to be unaligned */ 291 292 MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34, 293 /* data0 = number of big buffers to use. It must be 0 or a power of 2. 294 * 0 indicates that the NIC consumes as many buffers as they are required 295 * for packet. This is the default behavior. 296 * A power of 2 number indicates that the NIC always uses the specified 297 * number of buffers for each big receive packet. 298 * It is up to the driver to ensure that this value is big enough for 299 * the NIC to be able to receive maximum-sized packets. 300 */ 301 302 MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35, 303 MXGEFW_CMD_ENABLE_RSS_QUEUES = 36, 304 /* data0 = number of slices n (0, 1, ..., n-1) to enable 305 * data1 = interrupt mode | use of multiple transmit queues. 306 * 0=share one INTx/MSI. 307 * 1=use one MSI-X per queue. 308 * If all queues share one interrupt, the driver must have set 309 * RSS_SHARED_INTERRUPT_DMA before enabling queues. 310 * 2=enable both receive and send queues. 311 * Without this bit set, only one send queue (slice 0's send queue) 312 * is enabled. The receive queues are always enabled. 313 */ 314 #define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 315 #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 316 #define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 317 318 MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37, 319 MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38, 320 /* data0, data1 = bus address lsw, msw */ 321 MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39, 322 /* get the offset of the indirection table */ 323 MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40, 324 /* set the size of the indirection table */ 325 MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41, 326 /* get the offset of the secret key */ 327 MXGEFW_CMD_RSS_KEY_UPDATED = 42, 328 /* tell nic that the secret key's been updated */ 329 MXGEFW_CMD_SET_RSS_ENABLE = 43, 330 /* data0 = enable/disable rss 331 * 0: disable rss. nic does not distribute receive packets. 332 * 1: enable rss. nic distributes receive packets among queues. 333 * data1 = hash type 334 * 1: IPV4 (required by RSS) 335 * 2: TCP_IPV4 (required by RSS) 336 * 3: IPV4 | TCP_IPV4 (required by RSS) 337 * 4: source port 338 * 5: source port + destination port 339 */ 340 #define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 341 #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 342 #define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 343 #define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 344 #define MXGEFW_RSS_HASH_TYPE_MAX 0x5 345 346 MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44, 347 /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 348 * If the header size of a IPv6 TSO packet is larger than the specified 349 * value, then the driver must not use TSO. 350 * This size restriction only applies to IPv6 TSO. 351 * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 352 * always has enough header buffer to store maximum-sized headers. 353 */ 354 355 MXGEFW_CMD_SET_TSO_MODE = 45, 356 /* data0 = TSO mode. 357 * 0: Linux/FreeBSD style (NIC default) 358 * 1: NDIS/NetBSD style 359 */ 360 #define MXGEFW_TSO_MODE_LINUX 0 361 #define MXGEFW_TSO_MODE_NDIS 1 362 363 MXGEFW_CMD_MDIO_READ = 46, 364 /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 365 MXGEFW_CMD_MDIO_WRITE = 47, 366 /* data0 = dev_addr, data1 = register/addr, data2 = value */ 367 368 MXGEFW_CMD_I2C_READ = 48, 369 /* Starts to get a fresh copy of one byte or of the module i2c table, the 370 * obtained data is cached inside the xaui-xfi chip : 371 * data0 : 0 => get one byte, 1=> get 256 bytes 372 * data1 : If data0 == 0: location to refresh 373 * bit 7:0 register location 374 * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1) 375 * bit 23:16 is the i2c bus number (for multi-port NICs) 376 * If data0 == 1: unused 377 * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 378 * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts 379 * will return MXGEFW_CMD_ERROR_BUSY 380 */ 381 MXGEFW_CMD_I2C_BYTE = 49, 382 /* Return the last obtained copy of a given byte in the xfp i2c table 383 * (copy cached during the last relevant MXGEFW_CMD_I2C_READ) 384 * data0 : index of the desired table entry 385 * Return data = the byte stored at the requested index in the table 386 */ 387 388 MXGEFW_CMD_GET_VPUMP_OFFSET = 50, 389 /* Return data = NIC memory offset of mcp_vpump_public_global */ 390 MXGEFW_CMD_RESET_VPUMP = 51, 391 /* Resets the VPUMP state */ 392 393 MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52, 394 /* data0 = mcp_slot type to use. 395 * 0 = the default 4B mcp_slot 396 * 1 = 8B mcp_slot_8 397 */ 398 #define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 399 #define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 400 401 MXGEFW_CMD_SET_THROTTLE_FACTOR = 53, 402 /* set the throttle factor for ethp_z8e 403 data0 = throttle_factor 404 throttle_factor = 256 * pcie-raw-speed / tx_speed 405 tx_speed = 256 * pcie-raw-speed / throttle_factor 406 407 For PCI-E x8: pcie-raw-speed == 16Gb/s 408 For PCI-E x4: pcie-raw-speed == 8Gb/s 409 410 ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 411 ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 412 413 with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 414 with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 415 */ 416 417 MXGEFW_CMD_VPUMP_UP = 54, 418 /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 419 MXGEFW_CMD_GET_VPUMP_CLK = 55, 420 /* Get the lanai clock */ 421 422 MXGEFW_CMD_GET_DCA_OFFSET = 56, 423 /* offset of dca control for WDMAs */ 424 425 /* VMWare NetQueue commands */ 426 MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57, 427 MXGEFW_CMD_NETQ_ADD_FILTER = 58, 428 /* data0 = filter_id << 16 | queue << 8 | type */ 429 /* data1 = MS4 of MAC Addr */ 430 /* data2 = LS2_MAC << 16 | VLAN_tag */ 431 MXGEFW_CMD_NETQ_DEL_FILTER = 59, 432 /* data0 = filter_id */ 433 MXGEFW_CMD_NETQ_QUERY1 = 60, 434 MXGEFW_CMD_NETQ_QUERY2 = 61, 435 MXGEFW_CMD_NETQ_QUERY3 = 62, 436 MXGEFW_CMD_NETQ_QUERY4 = 63, 437 438 MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64, 439 /* When set, small receive buffers can cross page boundaries. 440 * Both small and big receive buffers may start at any address. 441 * This option has performance implications, so use with caution. 442 */ 443 }; 444 typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 445 446 447 enum myri10ge_mcp_cmd_status { 448 MXGEFW_CMD_OK = 0, 449 MXGEFW_CMD_UNKNOWN = 1, 450 MXGEFW_CMD_ERROR_RANGE = 2, 451 MXGEFW_CMD_ERROR_BUSY = 3, 452 MXGEFW_CMD_ERROR_EMPTY = 4, 453 MXGEFW_CMD_ERROR_CLOSED = 5, 454 MXGEFW_CMD_ERROR_HASH_ERROR = 6, 455 MXGEFW_CMD_ERROR_BAD_PORT = 7, 456 MXGEFW_CMD_ERROR_RESOURCES = 8, 457 MXGEFW_CMD_ERROR_MULTICAST = 9, 458 MXGEFW_CMD_ERROR_UNALIGNED = 10, 459 MXGEFW_CMD_ERROR_NO_MDIO = 11, 460 MXGEFW_CMD_ERROR_I2C_FAILURE = 12, 461 MXGEFW_CMD_ERROR_I2C_ABSENT = 13, 462 MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14 463 }; 464 typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 465 466 467 #define MXGEFW_OLD_IRQ_DATA_LEN 40 468 469 struct mcp_irq_data { 470 /* add new counters at the beginning */ 471 uint32_t future_use[1]; 472 uint32_t dropped_pause; 473 uint32_t dropped_unicast_filtered; 474 uint32_t dropped_bad_crc32; 475 uint32_t dropped_bad_phy; 476 uint32_t dropped_multicast_filtered; 477 /* 40 Bytes */ 478 uint32_t send_done_count; 479 480 #define MXGEFW_LINK_DOWN 0 481 #define MXGEFW_LINK_UP 1 482 #define MXGEFW_LINK_MYRINET 2 483 #define MXGEFW_LINK_UNKNOWN 3 484 uint32_t link_up; 485 uint32_t dropped_link_overflow; 486 uint32_t dropped_link_error_or_filtered; 487 uint32_t dropped_runt; 488 uint32_t dropped_overrun; 489 uint32_t dropped_no_small_buffer; 490 uint32_t dropped_no_big_buffer; 491 uint32_t rdma_tags_available; 492 493 uint8_t tx_stopped; 494 uint8_t link_down; 495 uint8_t stats_updated; 496 uint8_t valid; 497 }; 498 typedef struct mcp_irq_data mcp_irq_data_t; 499 500 #ifdef MXGEFW_NDIS 501 /* Exclusively used by NDIS drivers */ 502 struct mcp_rss_shared_interrupt { 503 uint8_t pad[2]; 504 uint8_t queue; 505 uint8_t valid; 506 }; 507 #endif 508 509 /* definitions for NETQ filter type */ 510 #define MXGEFW_NETQ_FILTERTYPE_NONE 0 511 #define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 512 #define MXGEFW_NETQ_FILTERTYPE_VLAN 2 513 #define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 514 515 #endif /* _myri10ge_mcp_h */ 516