1 /* Copyright 2015 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include <skiboot.h>
18 #include <chip.h>
19 #include <xscom.h>
20 #include <io.h>
21 #include <cpu.h>
22 #include <nx.h>
23 #include <vas.h>
24
25 /* Configuration settings */
26 #define CFG_842_FC_ENABLE (0x1f) /* enable all 842 functions */
27 #define CFG_842_ENABLE (1) /* enable 842 engines */
28 #define DMA_CSB_WR NX_DMA_CSB_WR_CI
29 #define DMA_COMPLETION_MODE NX_DMA_COMPLETION_MODE_CI
30 #define DMA_CPB_WR NX_DMA_CPB_WR_CI_PAD
31 #define DMA_OUTPUT_DATA_WR NX_DMA_OUTPUT_DATA_WR_CI
32 #define EE_1 (1) /* enable engine 842 1 */
33 #define EE_0 (1) /* enable engine 842 0 */
34
nx_cfg_842(u32 gcid,u64 xcfg)35 static int nx_cfg_842(u32 gcid, u64 xcfg)
36 {
37 u64 cfg, ci, ct;
38 int rc, instance = gcid + 1;
39
40 BUILD_ASSERT(MAX_CHIPS < NX_842_CFG_CI_MAX);
41
42 rc = xscom_read(gcid, xcfg, &cfg);
43 if (rc) {
44 prerror("NX%d: ERROR: XSCOM 842 config read failure %d\n",
45 gcid, rc);
46 return rc;
47 }
48
49 ct = GETFIELD(NX_842_CFG_CT, cfg);
50 if (!ct)
51 prlog(PR_INFO, "NX%d: 842 CT set to %u\n", gcid, NX_CT_842);
52 else if (ct == NX_CT_842)
53 prlog(PR_INFO, "NX%d: 842 CT already set to %u\n",
54 gcid, NX_CT_842);
55 else
56 prlog(PR_INFO, "NX%d: 842 CT already set to %u, "
57 "changing to %u\n", gcid, (unsigned int)ct, NX_CT_842);
58 ct = NX_CT_842;
59 cfg = SETFIELD(NX_842_CFG_CT, cfg, ct);
60
61 /* Coprocessor Instance must be shifted left.
62 * See hw doc Section 5.5.1.
63 */
64 ci = GETFIELD(NX_842_CFG_CI, cfg) >> NX_842_CFG_CI_LSHIFT;
65 if (!ci)
66 prlog(PR_INFO, "NX%d: 842 CI set to %d\n", gcid, instance);
67 else if (ci == instance)
68 prlog(PR_INFO, "NX%d: 842 CI already set to %u\n", gcid,
69 (unsigned int)ci);
70 else
71 prlog(PR_INFO, "NX%d: 842 CI already set to %u, "
72 "changing to %d\n", gcid, (unsigned int)ci, instance);
73 ci = instance;
74 cfg = SETFIELD(NX_842_CFG_CI, cfg, ci << NX_842_CFG_CI_LSHIFT);
75
76 /* Enable all functions */
77 cfg = SETFIELD(NX_842_CFG_FC_ENABLE, cfg, CFG_842_FC_ENABLE);
78
79 cfg = SETFIELD(NX_842_CFG_ENABLE, cfg, CFG_842_ENABLE);
80
81 rc = xscom_write(gcid, xcfg, cfg);
82 if (rc)
83 prerror("NX%d: ERROR: 842 CT %u CI %u config failure %d\n",
84 gcid, (unsigned int)ct, (unsigned int)ci, rc);
85 else
86 prlog(PR_DEBUG, "NX%d: 842 Config 0x%016lx\n",
87 gcid, (unsigned long)cfg);
88
89 return rc;
90 }
91
nx_cfg_842_umac(struct dt_node * node,u32 gcid,u32 pb_base)92 static int nx_cfg_842_umac(struct dt_node *node, u32 gcid, u32 pb_base)
93 {
94 int rc;
95 u64 umac_bar, umac_notify;
96 struct dt_node *nx_node;
97 static u32 nx842_tid = 1; /* tid counter within coprocessor type */
98
99 nx_node = dt_new(node, "ibm,842-high-fifo");
100 umac_bar = pb_base + NX_P9_842_HIGH_PRI_RX_FIFO_BAR;
101 umac_notify = pb_base + NX_P9_842_HIGH_PRI_RX_FIFO_NOTIFY_MATCH;
102 rc = nx_cfg_rx_fifo(nx_node, "ibm,p9-nx-842", "High", gcid,
103 NX_CT_842, nx842_tid++, umac_bar,
104 umac_notify);
105 if (rc)
106 return rc;
107
108 nx_node = dt_new(node, "ibm,842-normal-fifo");
109 umac_bar = pb_base + NX_P9_842_NORMAL_PRI_RX_FIFO_BAR;
110 umac_notify = pb_base + NX_P9_842_NORMAL_PRI_RX_FIFO_NOTIFY_MATCH;
111 rc = nx_cfg_rx_fifo(nx_node, "ibm,p9-nx-842", "Normal", gcid,
112 NX_CT_842, nx842_tid++, umac_bar,
113 umac_notify);
114
115 return rc;
116 }
117
nx_cfg_842_dma(u32 gcid,u64 xcfg)118 static int nx_cfg_842_dma(u32 gcid, u64 xcfg)
119 {
120 u64 cfg;
121 int rc;
122
123 rc = xscom_read(gcid, xcfg, &cfg);
124 if (rc) {
125 prerror("NX%d: ERROR: XSCOM DMA config read failure %d\n",
126 gcid, rc);
127 return rc;
128 }
129
130 if (proc_gen >= proc_gen_p8) {
131 cfg = SETFIELD(NX_DMA_CFG_842_COMPRESS_PREFETCH, cfg,
132 DMA_COMPRESS_PREFETCH);
133 cfg = SETFIELD(NX_DMA_CFG_842_DECOMPRESS_PREFETCH, cfg,
134 DMA_DECOMPRESS_PREFETCH);
135 }
136
137 cfg = SETFIELD(NX_DMA_CFG_842_COMPRESS_MAX_RR, cfg,
138 DMA_COMPRESS_MAX_RR);
139 cfg = SETFIELD(NX_DMA_CFG_842_DECOMPRESS_MAX_RR, cfg,
140 DMA_DECOMPRESS_MAX_RR);
141 cfg = SETFIELD(NX_DMA_CFG_842_SPBC, cfg,
142 DMA_SPBC);
143 if (proc_gen < proc_gen_p9) {
144 cfg = SETFIELD(NX_DMA_CFG_842_CSB_WR, cfg,
145 DMA_CSB_WR);
146 cfg = SETFIELD(NX_DMA_CFG_842_COMPLETION_MODE, cfg,
147 DMA_COMPLETION_MODE);
148 cfg = SETFIELD(NX_DMA_CFG_842_CPB_WR, cfg,
149 DMA_CPB_WR);
150 cfg = SETFIELD(NX_DMA_CFG_842_OUTPUT_DATA_WR, cfg,
151 DMA_OUTPUT_DATA_WR);
152 }
153
154 rc = xscom_write(gcid, xcfg, cfg);
155 if (rc)
156 prerror("NX%d: ERROR: DMA config failure %d\n", gcid, rc);
157 else
158 prlog(PR_DEBUG, "NX%d: DMA 0x%016lx\n", gcid,
159 (unsigned long)cfg);
160
161 return rc;
162 }
163
nx_cfg_842_ee(u32 gcid,u64 xcfg)164 static int nx_cfg_842_ee(u32 gcid, u64 xcfg)
165 {
166 u64 cfg;
167 int rc;
168
169 rc = xscom_read(gcid, xcfg, &cfg);
170 if (rc) {
171 prerror("NX%d: ERROR: XSCOM EE config read failure %d\n",
172 gcid, rc);
173 return rc;
174 }
175
176 cfg = SETFIELD(NX_EE_CFG_CH1, cfg, EE_1);
177 cfg = SETFIELD(NX_EE_CFG_CH0, cfg, EE_0);
178
179 rc = xscom_write(gcid, xcfg, cfg);
180 if (rc)
181 prerror("NX%d: ERROR: Engine Enable failure %d\n", gcid, rc);
182 else
183 prlog(PR_DEBUG, "NX%d: Engine Enable 0x%016lx\n",
184 gcid, (unsigned long)cfg);
185
186 return rc;
187 }
188
nx_enable_842(struct dt_node * node,u32 gcid,u32 pb_base)189 void nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base)
190 {
191 u64 cfg_dma, cfg_842, cfg_ee;
192 int rc;
193
194 if (dt_node_is_compatible(node, "ibm,power8-nx")) {
195 cfg_dma = pb_base + NX_P8_DMA_CFG;
196 cfg_842 = pb_base + NX_P8_842_CFG;
197 cfg_ee = pb_base + NX_P8_EE_CFG;
198 } else {
199 prerror("NX%d: ERROR: Unknown NX type!\n", gcid);
200 return;
201 }
202
203 rc = nx_cfg_842_dma(gcid, cfg_dma);
204 if (rc)
205 return;
206
207 rc = nx_cfg_842(gcid, cfg_842);
208 if (rc)
209 return;
210
211 rc = nx_cfg_842_ee(gcid, cfg_ee);
212 if (rc)
213 return;
214
215 prlog(PR_INFO, "NX%d: 842 Coprocessor Enabled\n", gcid);
216
217 dt_add_property_cells(node, "ibm,842-coprocessor-type", NX_CT_842);
218 dt_add_property_cells(node, "ibm,842-coprocessor-instance", gcid + 1);
219 }
220
p9_nx_enable_842(struct dt_node * node,u32 gcid,u32 pb_base)221 void p9_nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base)
222 {
223 u64 cfg_dma, cfg_ee;
224 int rc;
225
226 cfg_dma = pb_base + NX_P9_DMA_CFG;
227 cfg_ee = pb_base + NX_P9_EE_CFG;
228
229 rc = nx_cfg_842_dma(gcid, cfg_dma);
230 if (rc)
231 return;
232
233 rc = nx_cfg_842_umac(node, gcid, pb_base);
234 if (rc)
235 return;
236
237 rc = nx_cfg_842_ee(gcid, cfg_ee);
238 if (rc)
239 return;
240
241 prlog(PR_INFO, "NX%d: 842 Coprocessor Enabled\n", gcid);
242
243 }
244