1 /* Copyright 2013-2014 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16 #include <stdint.h>
17 #include <stdbool.h>
18 #include <stdlib.h>
19 #include <errno.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <time.h>
23 #include <lpc.h>
24 #include <sfc-ctrl.h>
25
26 #include <libflash/libflash.h>
27 #include <libflash/libflash-priv.h>
28
29 /* Offset of SFC registers in FW space */
30 #define SFC_CMDREG_OFFSET 0x00000c00
31 /* Offset of SFC command buffer in FW space */
32 #define SFC_CMDBUF_OFFSET 0x00000d00
33 /* Offset of flash MMIO mapping in FW space */
34 #define SFC_MMIO_OFFSET 0x0c000000
35
36
37 /*
38 * Register definitions
39 */
40 #define SFC_REG_CONF 0x10 /* CONF: Direct Access Configuration */
41 #define SFC_REG_CONF_FRZE (1 << 3)
42 #define SFC_REG_CONF_ECCEN (1 << 2)
43 #define SFC_REG_CONF_DRCD (1 << 1)
44 #define SFC_REG_CONF_FLRLD (1 << 0)
45
46 #define SFC_REG_STATUS 0x0C /* STATUS : Status Reg */
47 #define SFC_REG_STATUS_NX_ON_SHFT 28
48 #define SFC_REG_STATUS_RWP (1 << 27)
49 #define SFC_REG_STATUS_FOURBYTEAD (1 << 26)
50 #define SFC_REG_STATUS_ILLEGAL (1 << 4)
51 #define SFC_REG_STATUS_ECCERRCNTN (1 << 3)
52 #define SFC_REG_STATUS_ECCUEN (1 << 2)
53 #define SFC_REG_STATUS_DONE (1 << 0)
54
55 #define SFC_REG_CMD 0x40 /* CMD : Command */
56 #define SFC_REG_CMD_OPCODE_SHFT 9
57 #define SFC_REG_CMD_LENGTH_SHFT 0
58
59 #define SFC_REG_SPICLK 0x3C /* SPICLK: SPI clock rate config */
60 #define SFC_REG_SPICLK_OUTDLY_SHFT 24
61 #define SFC_REG_SPICLK_INSAMPDLY_SHFT 16
62 #define SFC_REG_SPICLK_CLKHI_SHFT 8
63 #define SFC_REG_SPICLK_CLKLO_SHFT 0
64
65 #define SFC_REG_ADR 0x44 /* ADR : Address */
66 #define SFC_REG_ERASMS 0x48 /* ERASMS : Small Erase Block Size */
67 #define SFC_REG_ERASLGS 0x4C /* ERALGS : Large Erase Block Size */
68 #define SFC_REG_CONF4 0x54 /* CONF4 : SPI Op Code for Small Erase */
69 #define SFC_REG_CONF5 0x58 /* CONF5 : Small Erase Size config reg */
70
71 #define SFC_REG_CONF8 0x64 /* CONF8 : Read Command */
72 #define SFC_REG_CONF8_CSINACTIVERD_SHFT 18
73 #define SFC_REG_CONF8_DUMMY_SHFT 8
74 #define SFC_REG_CONF8_READOP_SHFT 0
75
76 #define SFC_REG_ADRCBF 0x80 /* ADRCBF : First Intf NOR Addr Offset */
77 #define SFC_REG_ADRCMF 0x84 /* ADRCMF : First Intf NOR Allocation */
78 #define SFC_REG_ADRCBS 0x88 /* ADRCBS : Second Intf NOR Addr Offset */
79 #define SFC_REG_ADRCMS 0x8C /* ADRCMS : Second Intf NOR Allocation */
80 #define SFC_REG_OADRNB 0x90 /* OADRNB : Direct Access OBP Window Base Address */
81 #define SFC_REG_OADRNS 0x94 /* OADRNS : DIrect Access OPB Window Size */
82
83 #define SFC_REG_CHIPIDCONF 0x9C /* CHIPIDCONF : config ChipId CMD */
84 #define SFC_REG_CHIPIDCONF_OPCODE_SHFT 24
85 #define SFC_REG_CHIPIDCONF_READ (1 << 23)
86 #define SFC_REG_CHIPIDCONF_WRITE (1 << 22)
87 #define SFC_REG_CHIPIDCONF_USE_ADDR (1 << 21)
88 #define SFC_REG_CHIPIDCONF_DUMMY_SHFT 16
89 #define SFC_REG_CHIPIDCONF_LEN_SHFT 0
90
91 /*
92 * SFC Opcodes
93 */
94 #define SFC_OP_READRAW 0x03 /* Read Raw */
95 #define SFC_OP_WRITERAW 0x02 /* Write Raw */
96 #define SFC_OP_ERASM 0x32 /* Erase Small */
97 #define SFC_OP_ERALG 0x34 /* Erase Large */
98 #define SFC_OP_ENWRITPROT 0x53 /* Enable WRite Protect */
99 #define SFC_OP_CHIPID 0x1F /* Get Chip ID */
100 #define SFC_OP_STATUS 0x05 /* Get Status */
101 #define SFC_OP_TURNOFF 0x5E /* Turn Off */
102 #define SFC_OP_TURNON 0x50 /* Turn On */
103 #define SFC_OP_ABORT 0x6F /* Super-Abort */
104 #define SFC_OP_START4BA 0x37 /* Start 4BA */
105 #define SFC_OP_END4BA 0x69 /* End 4BA */
106
107 /* Command buffer size */
108 #define SFC_CMDBUF_SIZE 256
109
110 struct sfc_ctrl {
111 /* Erase sizes */
112 uint32_t small_er_size;
113 uint32_t large_er_size;
114
115 /* Current 4b mode */
116 bool mode_4b;
117
118 /* Callbacks */
119 struct spi_flash_ctrl ops;
120 };
121
122 /* Command register support */
sfc_reg_read(uint8_t reg,uint32_t * val)123 static inline int sfc_reg_read(uint8_t reg, uint32_t *val)
124 {
125 uint32_t tmp;
126 int rc;
127
128 *val = 0xffffffff;
129 rc = lpc_fw_read32(&tmp, SFC_CMDREG_OFFSET + reg);
130 if (rc)
131 return rc;
132 *val = be32_to_cpu(tmp);
133 return 0;
134 }
135
sfc_reg_write(uint8_t reg,uint32_t val)136 static inline int sfc_reg_write(uint8_t reg, uint32_t val)
137 {
138 return lpc_fw_write32(cpu_to_be32(val), SFC_CMDREG_OFFSET + reg);
139 }
140
sfc_buf_write(uint32_t len,const void * data)141 static int sfc_buf_write(uint32_t len, const void *data)
142 {
143 uint32_t tmp, off = 0;
144 int rc;
145
146 if (len > SFC_CMDBUF_SIZE)
147 return FLASH_ERR_PARM_ERROR;
148
149 while (len >= 4) {
150 tmp = *(const uint32_t *)data;
151 rc = lpc_fw_write32(tmp, SFC_CMDBUF_OFFSET + off);
152 if (rc)
153 return rc;
154 off += 4;
155 len -= 4;
156 data += 4;
157 }
158 if (!len)
159 return 0;
160
161 /* lpc_fw_write operates on BE values so that's what we layout
162 * in memory with memcpy. The swap in the register on LE doesn't
163 * matter, the result in memory will be in the right order.
164 */
165 tmp = -1;
166 memcpy(&tmp, data, len);
167 return lpc_fw_write32(tmp, SFC_CMDBUF_OFFSET + off);
168 }
169
sfc_buf_read(uint32_t len,void * data)170 static int sfc_buf_read(uint32_t len, void *data)
171 {
172 uint32_t tmp, off = 0;
173 int rc;
174
175 if (len > SFC_CMDBUF_SIZE)
176 return FLASH_ERR_PARM_ERROR;
177
178 while (len >= 4) {
179 rc = lpc_fw_read32(data, SFC_CMDBUF_OFFSET + off);
180 if (rc)
181 return rc;
182 off += 4;
183 len -= 4;
184 data += 4;
185 }
186 if (!len)
187 return 0;
188
189 rc = lpc_fw_read32(&tmp, SFC_CMDBUF_OFFSET + off);
190 if (rc)
191 return rc;
192 /* We know tmp contains a big endian value, so memcpy is
193 * our friend here
194 */
195 memcpy(data, &tmp, len);
196 return 0;
197 }
198
199 /* Polls until SFC indicates command is complete */
sfc_poll_complete(void)200 static int sfc_poll_complete(void)
201 {
202 uint32_t status, timeout;
203 struct timespec ts;
204
205 /*
206 * A full 256 bytes read/write command will take at least
207 * 126us. Smaller commands are faster but we use less of
208 * them. So let's sleep in increments of 100us
209 */
210 ts.tv_sec = 0;
211 ts.tv_nsec = 100000;
212
213 /*
214 * Use a 1s timeout which should be sufficient for the
215 * commands we use
216 */
217 timeout = 10000;
218
219 do {
220 int rc;
221
222 rc = sfc_reg_read(SFC_REG_STATUS, &status);
223 if (rc)
224 return rc;
225 if (status & SFC_REG_STATUS_DONE)
226 break;
227 if (--timeout == 0)
228 return FLASH_ERR_CTRL_TIMEOUT;
229 nanosleep(&ts, NULL);
230 } while (true);
231
232 return 0;
233 }
234
sfc_exec_command(uint8_t opcode,uint32_t length)235 static int sfc_exec_command(uint8_t opcode, uint32_t length)
236 {
237 int rc = 0;
238 uint32_t cmd_reg = 0;
239
240 if (opcode > 0x7f || length > 0x1ff)
241 return FLASH_ERR_PARM_ERROR;
242
243 /* Write command register to start execution */
244 cmd_reg |= (opcode << SFC_REG_CMD_OPCODE_SHFT);
245 cmd_reg |= (length << SFC_REG_CMD_LENGTH_SHFT);
246 rc = sfc_reg_write(SFC_REG_CMD, cmd_reg);
247 if (rc)
248 return rc;
249
250 /* Wait for command to complete */
251 return sfc_poll_complete();
252 }
253
sfc_chip_id(struct spi_flash_ctrl * ctrl,uint8_t * id_buf,uint32_t * id_size)254 static int sfc_chip_id(struct spi_flash_ctrl *ctrl, uint8_t *id_buf,
255 uint32_t *id_size)
256 {
257 uint32_t idconf;
258 int rc;
259
260 (void)ctrl;
261
262 if ((*id_size) < 3)
263 return FLASH_ERR_PARM_ERROR;
264
265 /*
266 * XXX This will not work in locked down mode but we assume that
267 * in this case, the chip ID command is already properly programmed
268 * and the SFC will ignore this. However I haven't verified...
269 */
270 idconf = ((uint64_t)CMD_RDID) << SFC_REG_CHIPIDCONF_OPCODE_SHFT;
271 idconf |= SFC_REG_CHIPIDCONF_READ;
272 idconf |= (3ul << SFC_REG_CHIPIDCONF_LEN_SHFT);
273 (void)sfc_reg_write(SFC_REG_CHIPIDCONF, idconf);
274
275 /* Perform command */
276 rc = sfc_exec_command(SFC_OP_CHIPID, 0);
277 if (rc)
278 return rc;
279
280 /* Read chip ID */
281 rc = sfc_buf_read(3, id_buf);
282 if (rc)
283 return rc;
284 *id_size = 3;
285
286 return 0;
287 }
288
289
sfc_read(struct spi_flash_ctrl * ctrl,uint32_t pos,void * buf,uint32_t len)290 static int sfc_read(struct spi_flash_ctrl *ctrl, uint32_t pos,
291 void *buf, uint32_t len)
292 {
293 (void)ctrl;
294
295 while(len) {
296 uint32_t chunk = len;
297 int rc;
298
299 if (chunk > SFC_CMDBUF_SIZE)
300 chunk = SFC_CMDBUF_SIZE;
301 rc = sfc_reg_write(SFC_REG_ADR, pos);
302 if (rc)
303 return rc;
304 rc = sfc_exec_command(SFC_OP_READRAW, chunk);
305 if (rc)
306 return rc;
307 rc = sfc_buf_read(chunk, buf);
308 if (rc)
309 return rc;
310 len -= chunk;
311 pos += chunk;
312 buf += chunk;
313 }
314 return 0;
315 }
316
sfc_write(struct spi_flash_ctrl * ctrl,uint32_t addr,const void * buf,uint32_t size)317 static int sfc_write(struct spi_flash_ctrl *ctrl, uint32_t addr,
318 const void *buf, uint32_t size)
319 {
320 uint32_t chunk;
321 int rc;
322
323 (void)ctrl;
324
325 while(size) {
326 /* We shall not cross a page boundary */
327 chunk = 0x100 - (addr & 0xff);
328 if (chunk > size)
329 chunk = size;
330
331 /* Write to SFC write buffer */
332 rc = sfc_buf_write(chunk, buf);
333 if (rc)
334 return rc;
335
336 /* Program address */
337 rc = sfc_reg_write(SFC_REG_ADR, addr);
338 if (rc)
339 return rc;
340
341 /* Send command */
342 rc = sfc_exec_command(SFC_OP_WRITERAW, chunk);
343 if (rc)
344 return rc;
345
346 addr += chunk;
347 buf += chunk;
348 size -= chunk;
349 }
350 return 0;
351 }
352
sfc_erase(struct spi_flash_ctrl * ctrl,uint32_t addr,uint32_t size)353 static int sfc_erase(struct spi_flash_ctrl *ctrl, uint32_t addr,
354 uint32_t size)
355 {
356 struct sfc_ctrl *ct = container_of(ctrl, struct sfc_ctrl, ops);
357 uint32_t sm_mask = ct->small_er_size - 1;
358 uint32_t lg_mask = ct->large_er_size - 1;
359 uint32_t chunk;
360 uint8_t cmd;
361 int rc;
362
363 while(size) {
364 /* Choose erase size for this chunk */
365 if (((addr | size) & lg_mask) == 0) {
366 chunk = ct->large_er_size;
367 cmd = SFC_OP_ERALG;
368 } else if (((addr | size) & sm_mask) == 0) {
369 chunk = ct->small_er_size;
370 cmd = SFC_OP_ERASM;
371 } else
372 return FLASH_ERR_ERASE_BOUNDARY;
373
374 rc = sfc_reg_write(SFC_REG_ADR, addr);
375 if (rc)
376 return rc;
377 rc = sfc_exec_command(cmd, 0);
378 if (rc)
379 return rc;
380 addr += chunk;
381 size -= chunk;
382 }
383 return 0;
384 }
385
sfc_setup(struct spi_flash_ctrl * ctrl,uint32_t * tsize)386 static int sfc_setup(struct spi_flash_ctrl *ctrl, uint32_t *tsize)
387 {
388 struct sfc_ctrl *ct = container_of(ctrl, struct sfc_ctrl, ops);
389 struct flash_info *info = ctrl->finfo;
390 uint32_t er_flags;
391
392 (void)tsize;
393
394 /* Keep non-erase related flags */
395 er_flags = ~FL_ERASE_ALL;
396
397 /* Add supported erase sizes */
398 if (ct->small_er_size == 0x1000 || ct->large_er_size == 0x1000)
399 er_flags |= FL_ERASE_4K;
400 if (ct->small_er_size == 0x8000 || ct->large_er_size == 0x8000)
401 er_flags |= FL_ERASE_32K;
402 if (ct->small_er_size == 0x10000 || ct->large_er_size == 0x10000)
403 er_flags |= FL_ERASE_64K;
404
405 /* Mask the flags out */
406 info->flags &= er_flags;
407
408 return 0;
409 }
410
sfc_set_4b(struct spi_flash_ctrl * ctrl,bool enable)411 static int sfc_set_4b(struct spi_flash_ctrl *ctrl, bool enable)
412 {
413 struct sfc_ctrl *ct = container_of(ctrl, struct sfc_ctrl, ops);
414 int rc;
415
416 rc = sfc_exec_command(enable ? SFC_OP_START4BA : SFC_OP_END4BA, 0);
417 if (rc)
418 return rc;
419 ct->mode_4b = enable;
420 return 0;
421 }
422
sfc_validate_er_size(uint32_t * size)423 static void sfc_validate_er_size(uint32_t *size)
424 {
425 if (*size == 0)
426 return;
427
428 /* We only support 4k, 32k and 64k */
429 if (*size != 0x1000 && *size != 0x8000 && *size != 0x10000) {
430 FL_ERR("SFC: Erase size %d bytes unsupported\n", *size);
431 *size = 0;
432 }
433 }
434
sfc_init(struct sfc_ctrl * ct)435 static int sfc_init(struct sfc_ctrl *ct)
436 {
437 int rc;
438 uint32_t status;
439
440 /*
441 * Assumptions: The controller has been fully initialized
442 * by an earlier FW layer setting the chip ID command, the
443 * erase sizes, and configuring the timings for reads and
444 * writes.
445 *
446 * This driver is meant to be usable if the configuration
447 * is in lock down.
448 *
449 * If that wasn't the case, we could configure some sane
450 * defaults here and tuned values in setup() after the
451 * chip has been identified.
452 */
453
454 /* Read erase sizes from flash */
455 rc = sfc_reg_read(SFC_REG_ERASMS, &ct->small_er_size);
456 if (rc)
457 return rc;
458 sfc_validate_er_size(&ct->small_er_size);
459 rc = sfc_reg_read(SFC_REG_ERASLGS, &ct->large_er_size);
460 if (rc)
461 return rc;
462 sfc_validate_er_size(&ct->large_er_size);
463
464 /* No erase sizes we can cope with ? Ouch... */
465 if ((ct->small_er_size == 0 && ct->large_er_size == 0) ||
466 (ct->large_er_size && (ct->small_er_size > ct->large_er_size))) {
467 FL_ERR("SFC: No supported erase sizes !\n");
468 return FLASH_ERR_CTRL_CONFIG_MISMATCH;
469 }
470
471 FL_INF("SFC: Suppored erase sizes:");
472 if (ct->small_er_size)
473 FL_INF(" %dKB", ct->small_er_size >> 10);
474 if (ct->large_er_size)
475 FL_INF(" %dKB", ct->large_er_size >> 10);
476 FL_INF("\n");
477
478 /* Read current state of 4 byte addressing */
479 rc = sfc_reg_read(SFC_REG_STATUS, &status);
480 if (rc)
481 return rc;
482 ct->mode_4b = !!(status & SFC_REG_STATUS_FOURBYTEAD);
483
484 return 0;
485 }
486
sfc_open(struct spi_flash_ctrl ** ctrl)487 int sfc_open(struct spi_flash_ctrl **ctrl)
488 {
489 struct sfc_ctrl *ct;
490 int rc;
491
492 *ctrl = NULL;
493 ct = malloc(sizeof(*ct));
494 if (!ct) {
495 FL_ERR("SFC: Failed to allocate\n");
496 return FLASH_ERR_MALLOC_FAILED;
497 }
498 memset(ct, 0, sizeof(*ct));
499 ct->ops.chip_id = sfc_chip_id;
500 ct->ops.setup = sfc_setup;
501 ct->ops.set_4b = sfc_set_4b;
502 ct->ops.read = sfc_read;
503 ct->ops.write = sfc_write;
504 ct->ops.erase = sfc_erase;
505
506 rc = sfc_init(ct);
507 if (rc)
508 goto fail;
509 *ctrl = &ct->ops;
510 return 0;
511 fail:
512 free(ct);
513 return rc;
514 }
515
sfc_close(struct spi_flash_ctrl * ctrl)516 void sfc_close(struct spi_flash_ctrl *ctrl)
517 {
518 struct sfc_ctrl *ct = container_of(ctrl, struct sfc_ctrl, ops);
519
520 /* Free the whole lot */
521 free(ct);
522 }
523
524