1 /* Copyright 2013-2016 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 /*
18 * Handle ChipTOD chip & configure core timebases
19 */
20 #include <skiboot.h>
21 #include <xscom.h>
22 #include <xscom-p8-regs.h>
23 #include <xscom-p9-regs.h>
24 #include <io.h>
25 #include <cpu.h>
26 #include <chip.h>
27 #include <mem_region.h>
28 #include <chiptod.h>
29 #include <interrupts.h>
30 #include <timebase.h>
31 #include <errorlog.h>
32 #include <libfdt/libfdt.h>
33 #include <opal-api.h>
34 #include <nvram.h>
35 #include <sbe-p8.h>
36
37 #include <p9_stop_api.H>
38 #include <p8_pore_table_gen_api.H>
39 #include <sbe_xip_image.h>
40
41 #define MAX_RESET_PATCH_SIZE 64
42
43 static uint32_t slw_saved_reset[MAX_RESET_PATCH_SIZE];
44
45 static bool slw_current_le = false;
46
47 enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT;
48 bool has_deep_states = false;
49
50 DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW,
51 OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL,
52 OPAL_NA);
53
54 DEFINE_LOG_ENTRY(OPAL_RC_SLW_SET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW,
55 OPAL_PLATFORM_FIRMWARE, OPAL_INFO,
56 OPAL_NA);
57
58 DEFINE_LOG_ENTRY(OPAL_RC_SLW_GET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW,
59 OPAL_PLATFORM_FIRMWARE, OPAL_INFO,
60 OPAL_NA);
61
62 DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW,
63 OPAL_PLATFORM_FIRMWARE, OPAL_INFO,
64 OPAL_NA);
65
slw_do_rvwinkle(void * data)66 static void slw_do_rvwinkle(void *data)
67 {
68 struct cpu_thread *cpu = this_cpu();
69 struct cpu_thread *master = data;
70 uint64_t lpcr = mfspr(SPR_LPCR);
71 struct proc_chip *chip;
72
73 /* Setup our ICP to receive IPIs */
74 icp_prep_for_pm();
75
76 /* Setup LPCR to wakeup on external interrupts only */
77 mtspr(SPR_LPCR, ((lpcr & ~SPR_LPCR_P8_PECE) | SPR_LPCR_P8_PECE2));
78 isync();
79
80 prlog(PR_DEBUG, "SLW: CPU PIR 0x%04x going to rvwinkle...\n",
81 cpu->pir);
82
83 /* Tell that we got it */
84 cpu->state = cpu_state_rvwinkle;
85
86 enter_p8_pm_state(1);
87
88 /* Restore SPRs */
89 init_shared_sprs();
90 init_replicated_sprs();
91
92 /* Ok, it's ours again */
93 cpu->state = cpu_state_active;
94
95 prlog(PR_DEBUG, "SLW: CPU PIR 0x%04x woken up !\n", cpu->pir);
96
97 /* Cleanup our ICP */
98 reset_cpu_icp();
99
100 /* Resync timebase */
101 chiptod_wakeup_resync();
102
103 /* Restore LPCR */
104 mtspr(SPR_LPCR, lpcr);
105 isync();
106
107 /* If we are passed a master pointer we are the designated
108 * waker, let's proceed. If not, return, we are finished.
109 */
110 if (!master)
111 return;
112
113 prlog(PR_DEBUG, "SLW: CPU PIR 0x%04x waiting for master...\n",
114 cpu->pir);
115
116 /* Allriiiight... now wait for master to go down */
117 while(master->state != cpu_state_rvwinkle)
118 sync();
119
120 /* XXX Wait one second ! (should check xscom state ? ) */
121 time_wait_ms(1000);
122
123 for_each_chip(chip) {
124 struct cpu_thread *c;
125 uint64_t tmp;
126 for_each_available_core_in_chip(c, chip->id) {
127 xscom_read(chip->id,
128 XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir),
129 EX_PM_IDLE_STATE_HISTORY_PHYP),
130 &tmp);
131 prlog(PR_TRACE, "SLW: core %x:%x"
132 " history: 0x%016llx (mid2)\n",
133 chip->id, pir_to_core_id(c->pir),
134 tmp);
135 }
136 }
137
138 prlog(PR_DEBUG, "SLW: Waking master (PIR 0x%04x)...\n", master->pir);
139
140 /* Now poke all the secondary threads on the master's core */
141 for_each_cpu(cpu) {
142 if (!cpu_is_sibling(cpu, master) || (cpu == master))
143 continue;
144 icp_kick_cpu(cpu);
145
146 /* Wait for it to claim to be back (XXX ADD TIMEOUT) */
147 while(cpu->state != cpu_state_active)
148 sync();
149 }
150
151 /* Now poke the master and be gone */
152 icp_kick_cpu(master);
153 }
154
slw_patch_reset(void)155 static void slw_patch_reset(void)
156 {
157 uint32_t *src, *dst, *sav;
158
159 BUILD_ASSERT((&reset_patch_end - &reset_patch_start) <=
160 MAX_RESET_PATCH_SIZE);
161
162 src = &reset_patch_start;
163 dst = (uint32_t *)0x100;
164 sav = slw_saved_reset;
165 while(src < &reset_patch_end) {
166 *(sav++) = *(dst);
167 *(dst++) = *(src++);
168 }
169 sync_icache();
170 }
171
slw_unpatch_reset(void)172 static void slw_unpatch_reset(void)
173 {
174 extern uint32_t reset_patch_start;
175 extern uint32_t reset_patch_end;
176 uint32_t *src, *dst, *sav;
177
178 src = &reset_patch_start;
179 dst = (uint32_t *)0x100;
180 sav = slw_saved_reset;
181 while(src < &reset_patch_end) {
182 *(dst++) = *(sav++);
183 src++;
184 }
185 sync_icache();
186 }
187
slw_general_init(struct proc_chip * chip,struct cpu_thread * c)188 static bool slw_general_init(struct proc_chip *chip, struct cpu_thread *c)
189 {
190 uint32_t core = pir_to_core_id(c->pir);
191 uint64_t tmp;
192 int rc;
193
194 /* PowerManagement GP0 clear PM_DISABLE */
195 rc = xscom_read(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_GP0), &tmp);
196 if (rc) {
197 log_simple_error(&e_info(OPAL_RC_SLW_INIT),
198 "SLW: Failed to read PM_GP0\n");
199 return false;
200 }
201 tmp = tmp & ~0x8000000000000000ULL;
202 rc = xscom_write(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_GP0), tmp);
203 if (rc) {
204 log_simple_error(&e_info(OPAL_RC_SLW_INIT),
205 "SLW: Failed to write PM_GP0\n");
206 return false;
207 }
208 prlog(PR_TRACE, "SLW: PMGP0 set to 0x%016llx\n", tmp);
209
210 /* Read back for debug */
211 rc = xscom_read(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_GP0), &tmp);
212 if (rc)
213 log_simple_error(&e_info(OPAL_RC_SLW_INIT),
214 "SLW: Failed to re-read PM_GP0. Continuing...\n");
215
216 prlog(PR_TRACE, "SLW: PMGP0 read 0x%016llx\n", tmp);
217
218 return true;
219 }
220
slw_set_overrides(struct proc_chip * chip,struct cpu_thread * c)221 static bool slw_set_overrides(struct proc_chip *chip, struct cpu_thread *c)
222 {
223 uint32_t core = pir_to_core_id(c->pir);
224 int rc;
225
226 rc = xscom_write(chip->id,
227 XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_SPECIAL_WAKEUP_PHYP),
228 0);
229 if (rc) {
230 log_simple_error(&e_info(OPAL_RC_SLW_SET),
231 "SLW: Failed to write PM_SPECIAL_WAKEUP_PHYP\n");
232 return false;
233 }
234
235 return true;
236 }
237
slw_set_overrides_p9(struct proc_chip * chip,struct cpu_thread * c)238 static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c)
239 {
240 uint64_t tmp;
241 int rc;
242 uint32_t core = pir_to_core_id(c->pir);
243
244 /* Clear special wakeup bits that could hold power mgt */
245 rc = xscom_write(chip->id,
246 XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP),
247 0);
248 if (rc) {
249 log_simple_error(&e_info(OPAL_RC_SLW_SET),
250 "SLW: Failed to write EC_PPM_SPECIAL_WKUP_HYP\n");
251 return false;
252 }
253 /* Read back for debug */
254 rc = xscom_read(chip->id,
255 XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP),
256 &tmp);
257 if (tmp)
258 prlog(PR_WARNING,
259 "SLW: core %d EC_PPM_SPECIAL_WKUP_HYP read 0x%016llx\n",
260 core, tmp);
261 rc = xscom_read(chip->id,
262 XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_OTR),
263 &tmp);
264 if (tmp)
265 prlog(PR_WARNING,
266 "SLW: core %d EC_PPM_SPECIAL_WKUP_OTR read 0x%016llx\n",
267 core, tmp);
268 return true;
269 }
270
slw_unset_overrides(struct proc_chip * chip,struct cpu_thread * c)271 static bool slw_unset_overrides(struct proc_chip *chip, struct cpu_thread *c)
272 {
273 uint32_t core = pir_to_core_id(c->pir);
274
275 /* XXX FIXME: Save and restore the overrides */
276 prlog(PR_DEBUG, "SLW: slw_unset_overrides %x:%x\n", chip->id, core);
277 return true;
278 }
279
slw_set_idle_mode(struct proc_chip * chip,struct cpu_thread * c)280 static bool slw_set_idle_mode(struct proc_chip *chip, struct cpu_thread *c)
281 {
282 uint32_t core = pir_to_core_id(c->pir);
283 uint64_t tmp;
284 int rc;
285
286 /*
287 * PM GP1 allows fast/deep mode to be selected independently for sleep
288 * and winkle. Init PM GP1 so that sleep happens in fast mode and
289 * winkle happens in deep mode.
290 * Make use of the OR XSCOM for this since the OCC might be manipulating
291 * the PM_GP1 register as well. Before doing this ensure that the bits
292 * managing idle states are cleared so as to override any bits set at
293 * init time.
294 */
295
296 tmp = ~EX_PM_GP1_SLEEP_WINKLE_MASK;
297 rc = xscom_write(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_CLEAR_GP1),
298 tmp);
299 if (rc) {
300 log_simple_error(&e_info(OPAL_RC_SLW_SET),
301 "SLW: Failed to write PM_GP1\n");
302 return false;
303 }
304
305 rc = xscom_write(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_SET_GP1),
306 EX_PM_SETUP_GP1_FAST_SLEEP_DEEP_WINKLE);
307 if (rc) {
308 log_simple_error(&e_info(OPAL_RC_SLW_SET),
309 "SLW: Failed to write PM_GP1\n");
310 return false;
311 }
312
313 /* Read back for debug */
314 xscom_read(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_GP1), &tmp);
315 prlog(PR_TRACE, "SLW: PMGP1 read 0x%016llx\n", tmp);
316 return true;
317 }
318
slw_get_idle_state_history(struct proc_chip * chip,struct cpu_thread * c)319 static bool slw_get_idle_state_history(struct proc_chip *chip, struct cpu_thread *c)
320 {
321 uint32_t core = pir_to_core_id(c->pir);
322 uint64_t tmp;
323 int rc;
324
325 /* Cleanup history */
326 rc = xscom_read(chip->id,
327 XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_IDLE_STATE_HISTORY_PHYP),
328 &tmp);
329 if (rc) {
330 log_simple_error(&e_info(OPAL_RC_SLW_GET),
331 "SLW: Failed to read PM_IDLE_STATE_HISTORY\n");
332 return false;
333 }
334
335 prlog(PR_TRACE, "SLW: core %x:%x history: 0x%016llx (old1)\n",
336 chip->id, core, tmp);
337
338 rc = xscom_read(chip->id,
339 XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_IDLE_STATE_HISTORY_PHYP),
340 &tmp);
341
342 if (rc) {
343 log_simple_error(&e_info(OPAL_RC_SLW_GET),
344 "SLW: Failed to read PM_IDLE_STATE_HISTORY\n");
345 return false;
346 }
347
348 prlog(PR_TRACE, "SLW: core %x:%x history: 0x%016llx (old2)\n",
349 chip->id, core, tmp);
350
351 return true;
352 }
353
idle_prepare_core(struct proc_chip * chip,struct cpu_thread * c)354 static bool idle_prepare_core(struct proc_chip *chip, struct cpu_thread *c)
355 {
356 prlog(PR_TRACE, "FASTSLEEP: Prepare core %x:%x\n",
357 chip->id, pir_to_core_id(c->pir));
358
359 if(!slw_general_init(chip, c))
360 return false;
361 if(!slw_set_overrides(chip, c))
362 return false;
363 if(!slw_set_idle_mode(chip, c))
364 return false;
365 if(!slw_get_idle_state_history(chip, c))
366 return false;
367
368 return true;
369
370 }
371
372 /* Define device-tree fields */
373 #define MAX_NAME_LEN 16
374 struct cpu_idle_states {
375 char name[MAX_NAME_LEN];
376 u32 latency_ns;
377 u32 residency_ns;
378 /*
379 * Register value/mask used to select different idle states.
380 * PMICR in POWER8 and PSSCR in POWER9
381 */
382 u64 pm_ctrl_reg_val;
383 u64 pm_ctrl_reg_mask;
384 u32 flags;
385 };
386
387 static struct cpu_idle_states nap_only_cpu_idle_states[] = {
388 { /* nap */
389 .name = "nap",
390 .latency_ns = 4000,
391 .residency_ns = 100000,
392 .flags = 0*OPAL_PM_DEC_STOP \
393 | 0*OPAL_PM_TIMEBASE_STOP \
394 | 1*OPAL_PM_LOSE_USER_CONTEXT \
395 | 0*OPAL_PM_LOSE_HYP_CONTEXT \
396 | 0*OPAL_PM_LOSE_FULL_CONTEXT \
397 | 1*OPAL_PM_NAP_ENABLED \
398 | 0*OPAL_PM_SLEEP_ENABLED \
399 | 0*OPAL_PM_WINKLE_ENABLED \
400 | 0*OPAL_USE_PMICR,
401 .pm_ctrl_reg_val = 0,
402 .pm_ctrl_reg_mask = 0 },
403 };
404
405 static struct cpu_idle_states power8_cpu_idle_states[] = {
406 { /* nap */
407 .name = "nap",
408 .latency_ns = 4000,
409 .residency_ns = 100000,
410 .flags = 0*OPAL_PM_DEC_STOP \
411 | 0*OPAL_PM_TIMEBASE_STOP \
412 | 1*OPAL_PM_LOSE_USER_CONTEXT \
413 | 0*OPAL_PM_LOSE_HYP_CONTEXT \
414 | 0*OPAL_PM_LOSE_FULL_CONTEXT \
415 | 1*OPAL_PM_NAP_ENABLED \
416 | 0*OPAL_USE_PMICR,
417 .pm_ctrl_reg_val = 0,
418 .pm_ctrl_reg_mask = 0 },
419 { /* fast sleep (with workaround) */
420 .name = "fastsleep_",
421 .latency_ns = 40000,
422 .residency_ns = 300000000,
423 .flags = 1*OPAL_PM_DEC_STOP \
424 | 1*OPAL_PM_TIMEBASE_STOP \
425 | 1*OPAL_PM_LOSE_USER_CONTEXT \
426 | 0*OPAL_PM_LOSE_HYP_CONTEXT \
427 | 0*OPAL_PM_LOSE_FULL_CONTEXT \
428 | 1*OPAL_PM_SLEEP_ENABLED_ER1 \
429 | 0*OPAL_USE_PMICR, /* Not enabled until deep
430 states are available */
431 .pm_ctrl_reg_val = OPAL_PM_FASTSLEEP_PMICR,
432 .pm_ctrl_reg_mask = OPAL_PM_SLEEP_PMICR_MASK },
433 { /* Winkle */
434 .name = "winkle",
435 .latency_ns = 10000000,
436 .residency_ns = 1000000000, /* Educated guess (not measured).
437 * Winkle is not currently used by
438 * linux cpuidle subsystem so we
439 * don't have real world user.
440 * However, this should be roughly
441 * accurate for when linux does
442 * use it. */
443 .flags = 1*OPAL_PM_DEC_STOP \
444 | 1*OPAL_PM_TIMEBASE_STOP \
445 | 1*OPAL_PM_LOSE_USER_CONTEXT \
446 | 1*OPAL_PM_LOSE_HYP_CONTEXT \
447 | 1*OPAL_PM_LOSE_FULL_CONTEXT \
448 | 1*OPAL_PM_WINKLE_ENABLED \
449 | 0*OPAL_USE_PMICR, /* Currently choosing deep vs
450 fast via EX_PM_GP1 reg */
451 .pm_ctrl_reg_val = 0,
452 .pm_ctrl_reg_mask = 0 },
453 };
454
455 /*
456 * cpu_idle_states for key idle states of POWER9 that we want to
457 * exploit.
458 * Note latency_ns and residency_ns are estimated values for now.
459 */
460 static struct cpu_idle_states power9_cpu_idle_states[] = {
461 {
462 .name = "stop0_lite", /* Enter stop0 with no state loss */
463 .latency_ns = 1000,
464 .residency_ns = 10000,
465 .flags = 0*OPAL_PM_DEC_STOP \
466 | 0*OPAL_PM_TIMEBASE_STOP \
467 | 0*OPAL_PM_LOSE_USER_CONTEXT \
468 | 0*OPAL_PM_LOSE_HYP_CONTEXT \
469 | 0*OPAL_PM_LOSE_FULL_CONTEXT \
470 | 1*OPAL_PM_STOP_INST_FAST,
471 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(0) \
472 | OPAL_PM_PSSCR_MTL(3) \
473 | OPAL_PM_PSSCR_TR(3),
474 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
475 {
476 .name = "stop0",
477 .latency_ns = 2000,
478 .residency_ns = 20000,
479 .flags = 0*OPAL_PM_DEC_STOP \
480 | 0*OPAL_PM_TIMEBASE_STOP \
481 | 1*OPAL_PM_LOSE_USER_CONTEXT \
482 | 0*OPAL_PM_LOSE_HYP_CONTEXT \
483 | 0*OPAL_PM_LOSE_FULL_CONTEXT \
484 | 1*OPAL_PM_STOP_INST_FAST,
485 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(0) \
486 | OPAL_PM_PSSCR_MTL(3) \
487 | OPAL_PM_PSSCR_TR(3) \
488 | OPAL_PM_PSSCR_ESL \
489 | OPAL_PM_PSSCR_EC,
490 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
491
492 /* stop1_lite has been removed since it adds no additional benefit over stop0_lite */
493
494 {
495 .name = "stop1",
496 .latency_ns = 5000,
497 .residency_ns = 50000,
498 .flags = 0*OPAL_PM_DEC_STOP \
499 | 0*OPAL_PM_TIMEBASE_STOP \
500 | 1*OPAL_PM_LOSE_USER_CONTEXT \
501 | 0*OPAL_PM_LOSE_HYP_CONTEXT \
502 | 0*OPAL_PM_LOSE_FULL_CONTEXT \
503 | 1*OPAL_PM_STOP_INST_FAST,
504 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(1) \
505 | OPAL_PM_PSSCR_MTL(3) \
506 | OPAL_PM_PSSCR_TR(3) \
507 | OPAL_PM_PSSCR_ESL \
508 | OPAL_PM_PSSCR_EC,
509 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
510 /*
511 * stop2_lite has been removed since currently it adds minimal benefit over stop2.
512 * However, the benefit is eclipsed by the time required to ungate the clocks
513 */
514
515 {
516 .name = "stop2",
517 .latency_ns = 10000,
518 .residency_ns = 100000,
519 .flags = 0*OPAL_PM_DEC_STOP \
520 | 0*OPAL_PM_TIMEBASE_STOP \
521 | 1*OPAL_PM_LOSE_USER_CONTEXT \
522 | 0*OPAL_PM_LOSE_HYP_CONTEXT \
523 | 0*OPAL_PM_LOSE_FULL_CONTEXT \
524 | 1*OPAL_PM_STOP_INST_FAST,
525 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(2) \
526 | OPAL_PM_PSSCR_MTL(3) \
527 | OPAL_PM_PSSCR_TR(3) \
528 | OPAL_PM_PSSCR_ESL \
529 | OPAL_PM_PSSCR_EC,
530 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
531 {
532 .name = "stop4",
533 .latency_ns = 100000,
534 .residency_ns = 10000000,
535 .flags = 0*OPAL_PM_DEC_STOP \
536 | 0*OPAL_PM_TIMEBASE_STOP \
537 | 1*OPAL_PM_LOSE_USER_CONTEXT \
538 | 1*OPAL_PM_LOSE_HYP_CONTEXT \
539 | 1*OPAL_PM_LOSE_FULL_CONTEXT \
540 | 1*OPAL_PM_STOP_INST_DEEP,
541 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(4) \
542 | OPAL_PM_PSSCR_MTL(7) \
543 | OPAL_PM_PSSCR_TR(3) \
544 | OPAL_PM_PSSCR_ESL \
545 | OPAL_PM_PSSCR_EC,
546 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
547 {
548 .name = "stop5",
549 .latency_ns = 200000,
550 .residency_ns = 20000000,
551 .flags = 0*OPAL_PM_DEC_STOP \
552 | 0*OPAL_PM_TIMEBASE_STOP \
553 | 1*OPAL_PM_LOSE_USER_CONTEXT \
554 | 1*OPAL_PM_LOSE_HYP_CONTEXT \
555 | 1*OPAL_PM_LOSE_FULL_CONTEXT \
556 | 1*OPAL_PM_STOP_INST_DEEP,
557 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(5) \
558 | OPAL_PM_PSSCR_MTL(7) \
559 | OPAL_PM_PSSCR_TR(3) \
560 | OPAL_PM_PSSCR_ESL \
561 | OPAL_PM_PSSCR_EC,
562 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
563
564 {
565 .name = "stop8",
566 .latency_ns = 2000000,
567 .residency_ns = 20000000,
568 .flags = 1*OPAL_PM_DEC_STOP \
569 | 1*OPAL_PM_TIMEBASE_STOP \
570 | 1*OPAL_PM_LOSE_USER_CONTEXT \
571 | 1*OPAL_PM_LOSE_HYP_CONTEXT \
572 | 1*OPAL_PM_LOSE_FULL_CONTEXT \
573 | 1*OPAL_PM_STOP_INST_DEEP,
574 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(8) \
575 | OPAL_PM_PSSCR_MTL(11) \
576 | OPAL_PM_PSSCR_TR(3) \
577 | OPAL_PM_PSSCR_ESL \
578 | OPAL_PM_PSSCR_EC,
579 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
580
581 {
582 .name = "stop11",
583 .latency_ns = 10000000,
584 .residency_ns = 100000000,
585 .flags = 1*OPAL_PM_DEC_STOP \
586 | 1*OPAL_PM_TIMEBASE_STOP \
587 | 1*OPAL_PM_LOSE_USER_CONTEXT \
588 | 1*OPAL_PM_LOSE_HYP_CONTEXT \
589 | 1*OPAL_PM_LOSE_FULL_CONTEXT \
590 | 1*OPAL_PM_STOP_INST_DEEP,
591 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(11) \
592 | OPAL_PM_PSSCR_MTL(11) \
593 | OPAL_PM_PSSCR_TR(3) \
594 | OPAL_PM_PSSCR_ESL \
595 | OPAL_PM_PSSCR_EC,
596 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
597
598 };
599
600 /*
601 * Prior to Mambo.7.8.21, mambo did set the MSR correctly for lite stop
602 * states, so disable them for now.
603 */
604 static struct cpu_idle_states power9_mambo_cpu_idle_states[] = {
605 {
606 .name = "stop0",
607 .latency_ns = 2000,
608 .residency_ns = 20000,
609 .flags = 0*OPAL_PM_DEC_STOP \
610 | 0*OPAL_PM_TIMEBASE_STOP \
611 | 1*OPAL_PM_LOSE_USER_CONTEXT \
612 | 0*OPAL_PM_LOSE_HYP_CONTEXT \
613 | 0*OPAL_PM_LOSE_FULL_CONTEXT \
614 | 1*OPAL_PM_STOP_INST_FAST,
615 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(0) \
616 | OPAL_PM_PSSCR_MTL(3) \
617 | OPAL_PM_PSSCR_TR(3) \
618 | OPAL_PM_PSSCR_ESL \
619 | OPAL_PM_PSSCR_EC,
620 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
621 {
622 .name = "stop1",
623 .latency_ns = 5000,
624 .residency_ns = 50000,
625 .flags = 0*OPAL_PM_DEC_STOP \
626 | 0*OPAL_PM_TIMEBASE_STOP \
627 | 1*OPAL_PM_LOSE_USER_CONTEXT \
628 | 0*OPAL_PM_LOSE_HYP_CONTEXT \
629 | 0*OPAL_PM_LOSE_FULL_CONTEXT \
630 | 1*OPAL_PM_STOP_INST_FAST,
631 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(1) \
632 | OPAL_PM_PSSCR_MTL(3) \
633 | OPAL_PM_PSSCR_TR(3) \
634 | OPAL_PM_PSSCR_ESL \
635 | OPAL_PM_PSSCR_EC,
636 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
637 {
638 .name = "stop2",
639 .latency_ns = 10000,
640 .residency_ns = 100000,
641 .flags = 0*OPAL_PM_DEC_STOP \
642 | 0*OPAL_PM_TIMEBASE_STOP \
643 | 1*OPAL_PM_LOSE_USER_CONTEXT \
644 | 0*OPAL_PM_LOSE_HYP_CONTEXT \
645 | 0*OPAL_PM_LOSE_FULL_CONTEXT \
646 | 1*OPAL_PM_STOP_INST_FAST,
647 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(2) \
648 | OPAL_PM_PSSCR_MTL(3) \
649 | OPAL_PM_PSSCR_TR(3) \
650 | OPAL_PM_PSSCR_ESL \
651 | OPAL_PM_PSSCR_EC,
652 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
653 {
654 .name = "stop4",
655 .latency_ns = 100000,
656 .residency_ns = 1000000,
657 .flags = 1*OPAL_PM_DEC_STOP \
658 | 1*OPAL_PM_TIMEBASE_STOP \
659 | 1*OPAL_PM_LOSE_USER_CONTEXT \
660 | 1*OPAL_PM_LOSE_HYP_CONTEXT \
661 | 1*OPAL_PM_LOSE_FULL_CONTEXT \
662 | 1*OPAL_PM_STOP_INST_DEEP,
663 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(4) \
664 | OPAL_PM_PSSCR_MTL(7) \
665 | OPAL_PM_PSSCR_TR(3) \
666 | OPAL_PM_PSSCR_ESL \
667 | OPAL_PM_PSSCR_EC,
668 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
669
670 {
671 .name = "stop8",
672 .latency_ns = 2000000,
673 .residency_ns = 20000000,
674 .flags = 1*OPAL_PM_DEC_STOP \
675 | 1*OPAL_PM_TIMEBASE_STOP \
676 | 1*OPAL_PM_LOSE_USER_CONTEXT \
677 | 1*OPAL_PM_LOSE_HYP_CONTEXT \
678 | 1*OPAL_PM_LOSE_FULL_CONTEXT \
679 | 1*OPAL_PM_STOP_INST_DEEP,
680 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(8) \
681 | OPAL_PM_PSSCR_MTL(11) \
682 | OPAL_PM_PSSCR_TR(3) \
683 | OPAL_PM_PSSCR_ESL \
684 | OPAL_PM_PSSCR_EC,
685 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
686
687 {
688 .name = "stop11",
689 .latency_ns = 10000000,
690 .residency_ns = 100000000,
691 .flags = 1*OPAL_PM_DEC_STOP \
692 | 1*OPAL_PM_TIMEBASE_STOP \
693 | 1*OPAL_PM_LOSE_USER_CONTEXT \
694 | 1*OPAL_PM_LOSE_HYP_CONTEXT \
695 | 1*OPAL_PM_LOSE_FULL_CONTEXT \
696 | 1*OPAL_PM_STOP_INST_DEEP,
697 .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(11) \
698 | OPAL_PM_PSSCR_MTL(11) \
699 | OPAL_PM_PSSCR_TR(3) \
700 | OPAL_PM_PSSCR_ESL \
701 | OPAL_PM_PSSCR_EC,
702 .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK },
703
704 };
705
slw_late_init_p9(struct proc_chip * chip)706 static void slw_late_init_p9(struct proc_chip *chip)
707 {
708 struct cpu_thread *c;
709 int rc;
710
711 prlog(PR_INFO, "SLW: Configuring self-restore for HRMOR\n");
712 for_each_available_cpu(c) {
713 if (c->chip_id != chip->id)
714 continue;
715 /*
716 * Clear HRMOR. Need to update only for thread
717 * 0 of each core. Doing it anyway for all threads
718 */
719 rc = p9_stop_save_cpureg((void *)chip->homer_base,
720 P9_STOP_SPR_HRMOR, 0,
721 c->pir);
722 if (rc) {
723 log_simple_error(&e_info(OPAL_RC_SLW_REG),
724 "SLW: Failed to set HRMOR for CPU %x,RC=0x%x\n",
725 c->pir, rc);
726 prlog(PR_ERR, "Disabling deep stop states\n");
727 }
728 }
729 }
730
731 /* Add device tree properties to describe idle states */
add_cpu_idle_state_properties(void)732 void add_cpu_idle_state_properties(void)
733 {
734 struct dt_node *power_mgt;
735 struct cpu_idle_states *states;
736 struct proc_chip *chip;
737 int nr_states;
738
739 bool can_sleep = true;
740 bool has_stop_inst = false;
741 u8 i;
742
743 u64 *pm_ctrl_reg_val_buf;
744 u64 *pm_ctrl_reg_mask_buf;
745 u32 supported_states_mask;
746 u32 opal_disabled_states_mask = ~0xEC000000; /* all but stop11 */
747 const char* nvram_disable_str;
748 u32 nvram_disabled_states_mask = 0x00;
749 u32 stop_levels;
750
751 /* Variables to track buffer length */
752 u8 name_buf_len;
753 u8 num_supported_idle_states;
754
755 /* Buffers to hold idle state properties */
756 char *name_buf, *alloced_name_buf;
757 u32 *latency_ns_buf;
758 u32 *residency_ns_buf;
759 u32 *flags_buf;
760
761 prlog(PR_DEBUG, "CPU idle state device tree init\n");
762
763 /* Create /ibm,opal/power-mgt if it doesn't exist already */
764 power_mgt = dt_new_check(opal_node, "power-mgt");
765 if (!power_mgt) {
766 /**
767 * @fwts-label CreateDTPowerMgtNodeFail
768 * @fwts-advice OPAL failed to add the power-mgt device tree
769 * node. This could mean that firmware ran out of memory,
770 * or there's a bug somewhere.
771 */
772 prlog(PR_ERR, "creating dt node /ibm,opal/power-mgt failed\n");
773 return;
774 }
775
776 /*
777 * Chose the right state table for the chip
778 *
779 * XXX We use the first chip version, we should probably look
780 * for the smaller of all chips instead..
781 */
782 chip = next_chip(NULL);
783 assert(chip);
784 if (chip->type == PROC_CHIP_P9_NIMBUS ||
785 chip->type == PROC_CHIP_P9_CUMULUS) {
786 if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) {
787 states = power9_mambo_cpu_idle_states;
788 nr_states = ARRAY_SIZE(power9_mambo_cpu_idle_states);
789 } else {
790 states = power9_cpu_idle_states;
791 nr_states = ARRAY_SIZE(power9_cpu_idle_states);
792 }
793
794 has_stop_inst = true;
795 stop_levels = dt_prop_get_u32_def(power_mgt,
796 "ibm,enabled-stop-levels", 0);
797 if (!stop_levels) {
798 prerror("SLW: No stop levels available. Power saving is disabled!\n");
799 has_deep_states = false;
800 } else {
801 /* Iterate to see if we have deep states enabled */
802 for (i = 0; i < nr_states; i++) {
803 u32 level = 31 - (states[i].pm_ctrl_reg_val &
804 OPAL_PM_PSSCR_RL_MASK);
805
806 if ((stop_levels & (1ul << level)) &&
807 (states[i].flags & OPAL_PM_STOP_INST_DEEP))
808 has_deep_states = true;
809 }
810 }
811 if ((wakeup_engine_state == WAKEUP_ENGINE_PRESENT) && has_deep_states) {
812 slw_late_init_p9(chip);
813 xive_late_init();
814 nx_p9_rng_late_init();
815 }
816 if (wakeup_engine_state != WAKEUP_ENGINE_PRESENT)
817 has_deep_states = false;
818 } else if (chip->type == PROC_CHIP_P8_MURANO ||
819 chip->type == PROC_CHIP_P8_VENICE ||
820 chip->type == PROC_CHIP_P8_NAPLES) {
821 const struct dt_property *p;
822
823 p = dt_find_property(dt_root, "ibm,enabled-idle-states");
824 if (p)
825 prlog(PR_NOTICE,
826 "SLW: HB-provided idle states property found\n");
827 states = power8_cpu_idle_states;
828 nr_states = ARRAY_SIZE(power8_cpu_idle_states);
829
830 /* Check if hostboot say we can sleep */
831 if (!p || !dt_prop_find_string(p, "fast-sleep")) {
832 prlog(PR_WARNING, "SLW: Sleep not enabled by HB"
833 " on this platform\n");
834 can_sleep = false;
835 }
836
837 /* Clip to NAP only on Murano and Venice DD1.x */
838 if ((chip->type == PROC_CHIP_P8_MURANO ||
839 chip->type == PROC_CHIP_P8_VENICE) &&
840 chip->ec_level < 0x20) {
841 prlog(PR_NOTICE, "SLW: Sleep not enabled on P8 DD1.x\n");
842 can_sleep = false;
843 }
844
845 } else {
846 states = nap_only_cpu_idle_states;
847 nr_states = ARRAY_SIZE(nap_only_cpu_idle_states);
848 }
849
850
851 /*
852 * Currently we can't append strings and cells to dt properties.
853 * So create buffers to which you can append values, then create
854 * dt properties with this buffer content.
855 */
856
857 /* Allocate memory to idle state property buffers. */
858 alloced_name_buf= malloc(nr_states * sizeof(char) * MAX_NAME_LEN);
859 name_buf = alloced_name_buf;
860 latency_ns_buf = malloc(nr_states * sizeof(u32));
861 residency_ns_buf= malloc(nr_states * sizeof(u32));
862 flags_buf = malloc(nr_states * sizeof(u32));
863 pm_ctrl_reg_val_buf = malloc(nr_states * sizeof(u64));
864 pm_ctrl_reg_mask_buf = malloc(nr_states * sizeof(u64));
865
866 name_buf_len = 0;
867 num_supported_idle_states = 0;
868
869 /*
870 * Create a mask with the flags of all supported idle states
871 * set. Use this to only add supported idle states to the
872 * device-tree
873 */
874 if (has_stop_inst) {
875 /* Power 9 / POWER ISA 3.0 */
876 supported_states_mask = OPAL_PM_STOP_INST_FAST;
877 if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT)
878 supported_states_mask |= OPAL_PM_STOP_INST_DEEP;
879 } else {
880 /* Power 7 and Power 8 */
881 supported_states_mask = OPAL_PM_NAP_ENABLED;
882 if (can_sleep)
883 supported_states_mask |= OPAL_PM_SLEEP_ENABLED |
884 OPAL_PM_SLEEP_ENABLED_ER1;
885 if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT)
886 supported_states_mask |= OPAL_PM_WINKLE_ENABLED;
887 }
888 nvram_disable_str = nvram_query_dangerous("opal-stop-state-disable-mask");
889 if (nvram_disable_str)
890 nvram_disabled_states_mask = strtol(nvram_disable_str, NULL, 0);
891 prlog(PR_DEBUG, "NVRAM stop disable mask: %x\n", nvram_disabled_states_mask);
892 for (i = 0; i < nr_states; i++) {
893 /* For each state, check if it is one of the supported states. */
894 if (!(states[i].flags & supported_states_mask))
895 continue;
896
897 /* We can only use the stop levels that HB has made available */
898 if (has_stop_inst) {
899 u32 level = 31 - (states[i].pm_ctrl_reg_val &
900 OPAL_PM_PSSCR_RL_MASK);
901
902 if (!(stop_levels & (1ul << level)))
903 continue;
904
905 if ((opal_disabled_states_mask |
906 nvram_disabled_states_mask) &
907 (1ul << level)) {
908 if (nvram_disable_str &&
909 !(nvram_disabled_states_mask & (1ul << level))) {
910 prlog(PR_NOTICE, "SLW: Enabling: %s "
911 "(disabled in OPAL, forced by "
912 "NVRAM)\n",states[i].name);
913 } else {
914 prlog(PR_NOTICE, "SLW: Disabling: %s in OPAL\n",
915 states[i].name);
916 continue;
917 }
918 }
919 }
920
921 prlog(PR_INFO, "SLW: Enabling: %s\n", states[i].name);
922
923 /*
924 * If a state is supported add each of its property
925 * to its corresponding property buffer.
926 */
927 strncpy(name_buf, states[i].name, MAX_NAME_LEN);
928 name_buf = name_buf + strlen(states[i].name) + 1;
929
930 *latency_ns_buf = cpu_to_fdt32(states[i].latency_ns);
931 latency_ns_buf++;
932
933 *residency_ns_buf = cpu_to_fdt32(states[i].residency_ns);
934 residency_ns_buf++;
935
936 *flags_buf = cpu_to_fdt32(states[i].flags);
937 flags_buf++;
938
939 *pm_ctrl_reg_val_buf = cpu_to_fdt64(states[i].pm_ctrl_reg_val);
940 pm_ctrl_reg_val_buf++;
941
942 *pm_ctrl_reg_mask_buf = cpu_to_fdt64(states[i].pm_ctrl_reg_mask);
943 pm_ctrl_reg_mask_buf++;
944
945 /* Increment buffer length trackers */
946 name_buf_len += strlen(states[i].name) + 1;
947 num_supported_idle_states++;
948
949 }
950
951 /* Point buffer pointers back to beginning of the buffer */
952 name_buf -= name_buf_len;
953 latency_ns_buf -= num_supported_idle_states;
954 residency_ns_buf -= num_supported_idle_states;
955 flags_buf -= num_supported_idle_states;
956 pm_ctrl_reg_val_buf -= num_supported_idle_states;
957 pm_ctrl_reg_mask_buf -= num_supported_idle_states;
958 /* Create dt properties with the buffer content */
959 dt_add_property(power_mgt, "ibm,cpu-idle-state-names", name_buf,
960 name_buf_len* sizeof(char));
961 dt_add_property(power_mgt, "ibm,cpu-idle-state-latencies-ns",
962 latency_ns_buf, num_supported_idle_states * sizeof(u32));
963 dt_add_property(power_mgt, "ibm,cpu-idle-state-residency-ns",
964 residency_ns_buf, num_supported_idle_states * sizeof(u32));
965 dt_add_property(power_mgt, "ibm,cpu-idle-state-flags", flags_buf,
966 num_supported_idle_states * sizeof(u32));
967
968 if (has_stop_inst) {
969 dt_add_property(power_mgt, "ibm,cpu-idle-state-psscr",
970 pm_ctrl_reg_val_buf,
971 num_supported_idle_states * sizeof(u64));
972 dt_add_property(power_mgt, "ibm,cpu-idle-state-psscr-mask",
973 pm_ctrl_reg_mask_buf,
974 num_supported_idle_states * sizeof(u64));
975 } else {
976 dt_add_property(power_mgt, "ibm,cpu-idle-state-pmicr",
977 pm_ctrl_reg_val_buf,
978 num_supported_idle_states * sizeof(u64));
979 dt_add_property(power_mgt, "ibm,cpu-idle-state-pmicr-mask",
980 pm_ctrl_reg_mask_buf,
981 num_supported_idle_states * sizeof(u64));
982 }
983 assert(alloced_name_buf == name_buf);
984 free(alloced_name_buf);
985 free(latency_ns_buf);
986 free(residency_ns_buf);
987 free(flags_buf);
988 free(pm_ctrl_reg_val_buf);
989 free(pm_ctrl_reg_mask_buf);
990 }
991
slw_cleanup_core(struct proc_chip * chip,struct cpu_thread * c)992 static void slw_cleanup_core(struct proc_chip *chip, struct cpu_thread *c)
993 {
994 uint64_t tmp;
995 int rc;
996
997 /* Display history to check transition */
998 rc = xscom_read(chip->id,
999 XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir),
1000 EX_PM_IDLE_STATE_HISTORY_PHYP),
1001 &tmp);
1002 if (rc) {
1003 log_simple_error(&e_info(OPAL_RC_SLW_GET),
1004 "SLW: Failed to read PM_IDLE_STATE_HISTORY\n");
1005 /* XXX error handling ? return false; */
1006 }
1007
1008 prlog(PR_DEBUG, "SLW: core %x:%x history: 0x%016llx (new1)\n",
1009 chip->id, pir_to_core_id(c->pir), tmp);
1010
1011 rc = xscom_read(chip->id,
1012 XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir),
1013 EX_PM_IDLE_STATE_HISTORY_PHYP),
1014 &tmp);
1015 if (rc) {
1016 log_simple_error(&e_info(OPAL_RC_SLW_GET),
1017 "SLW: Failed to read PM_IDLE_STATE_HISTORY\n");
1018 /* XXX error handling ? return false; */
1019 }
1020
1021 prlog(PR_DEBUG, "SLW: core %x:%x history: 0x%016llx (new2)\n",
1022 chip->id, pir_to_core_id(c->pir), tmp);
1023
1024 /*
1025 * XXX FIXME: Error out if the transition didn't reach rvwinkle ?
1026 */
1027
1028 /*
1029 * XXX FIXME: We should restore a bunch of the EX bits we
1030 * overwrite to sane values here
1031 */
1032 slw_unset_overrides(chip, c);
1033 }
1034
slw_cleanup_chip(struct proc_chip * chip)1035 static void slw_cleanup_chip(struct proc_chip *chip)
1036 {
1037 struct cpu_thread *c;
1038
1039 for_each_available_core_in_chip(c, chip->id)
1040 slw_cleanup_core(chip, c);
1041 }
1042
slw_patch_scans(struct proc_chip * chip,bool le_mode)1043 static void slw_patch_scans(struct proc_chip *chip, bool le_mode)
1044 {
1045 int64_t rc;
1046 uint64_t old_val, new_val;
1047
1048 rc = sbe_xip_get_scalar((void *)chip->slw_base,
1049 "skip_ex_override_ring_scans", &old_val);
1050 if (rc) {
1051 log_simple_error(&e_info(OPAL_RC_SLW_REG),
1052 "SLW: Failed to read scan override on chip %d\n",
1053 chip->id);
1054 return;
1055 }
1056
1057 new_val = le_mode ? 0 : 1;
1058
1059 prlog(PR_TRACE, "SLW: Chip %d, LE value was: %lld, setting to %lld\n",
1060 chip->id, old_val, new_val);
1061
1062 rc = sbe_xip_set_scalar((void *)chip->slw_base,
1063 "skip_ex_override_ring_scans", new_val);
1064 if (rc) {
1065 log_simple_error(&e_info(OPAL_RC_SLW_REG),
1066 "SLW: Failed to set LE mode on chip %d\n", chip->id);
1067 return;
1068 }
1069 }
1070
slw_reinit(uint64_t flags)1071 int64_t slw_reinit(uint64_t flags)
1072 {
1073 struct proc_chip *chip;
1074 struct cpu_thread *cpu;
1075 bool has_waker = false;
1076 bool target_le = slw_current_le;
1077
1078 if (proc_gen < proc_gen_p8)
1079 return OPAL_UNSUPPORTED;
1080
1081 if (flags & OPAL_REINIT_CPUS_HILE_BE)
1082 target_le = false;
1083 if (flags & OPAL_REINIT_CPUS_HILE_LE)
1084 target_le = true;
1085
1086 prlog(PR_TRACE, "SLW Reinit from CPU PIR 0x%04x,"
1087 " HILE set to %s endian...\n",
1088 this_cpu()->pir,
1089 target_le ? "little" : "big");
1090
1091 /* Prepare chips/cores for rvwinkle */
1092 for_each_chip(chip) {
1093 if (!chip->slw_base) {
1094 log_simple_error(&e_info(OPAL_RC_SLW_INIT),
1095 "SLW: Not found on chip %d\n", chip->id);
1096 return OPAL_HARDWARE;
1097 }
1098
1099 slw_patch_scans(chip, target_le);
1100 }
1101 slw_current_le = target_le;
1102
1103 /* XXX Save HIDs ? Or do that in head.S ... */
1104
1105 slw_patch_reset();
1106
1107 /* rvwinkle everybody and pick one to wake me once I rvwinkle myself */
1108 for_each_available_cpu(cpu) {
1109 struct cpu_thread *master = NULL;
1110
1111 if (cpu == this_cpu())
1112 continue;
1113
1114 /* Pick up a waker for myself: it must not be a sibling of
1115 * the current CPU and must be a thread 0 (so it gets to
1116 * sync its timebase before doing time_wait_ms()
1117 */
1118 if (!has_waker && !cpu_is_sibling(cpu, this_cpu()) &&
1119 cpu_is_thread0(cpu)) {
1120 has_waker = true;
1121 master = this_cpu();
1122 }
1123 __cpu_queue_job(cpu, "slw_do_rvwinkle",
1124 slw_do_rvwinkle, master, true);
1125
1126 /* Wait for it to claim to be down */
1127 while(cpu->state != cpu_state_rvwinkle)
1128 sync();
1129 }
1130
1131 /* XXX Wait one second ! (should check xscom state ? ) */
1132 prlog(PR_TRACE, "SLW: Waiting one second...\n");
1133 time_wait_ms(1000);
1134 prlog(PR_TRACE, "SLW: Done.\n");
1135
1136 for_each_chip(chip) {
1137 struct cpu_thread *c;
1138 uint64_t tmp;
1139 for_each_available_core_in_chip(c, chip->id) {
1140 xscom_read(chip->id,
1141 XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir),
1142 EX_PM_IDLE_STATE_HISTORY_PHYP),
1143 &tmp);
1144 prlog(PR_DEBUG, "SLW: core %x:%x"
1145 " history: 0x%016llx (mid)\n",
1146 chip->id, pir_to_core_id(c->pir), tmp);
1147 }
1148 }
1149
1150
1151 /* Wake everybody except on my core */
1152 for_each_cpu(cpu) {
1153 if (cpu->state != cpu_state_rvwinkle ||
1154 cpu_is_sibling(cpu, this_cpu()))
1155 continue;
1156 icp_kick_cpu(cpu);
1157
1158 /* Wait for it to claim to be back (XXX ADD TIMEOUT) */
1159 while(cpu->state != cpu_state_active)
1160 sync();
1161 }
1162
1163 /* Did we find a waker ? If we didn't, that means we had no
1164 * other core in the system, we can't do it
1165 */
1166 if (!has_waker) {
1167 prlog(PR_TRACE, "SLW: No candidate waker, giving up !\n");
1168 return OPAL_HARDWARE;
1169 }
1170
1171 /* Our siblings are rvwinkling, and our waker is waiting for us
1172 * so let's just go down now
1173 */
1174 slw_do_rvwinkle(NULL);
1175
1176 slw_unpatch_reset();
1177
1178 for_each_chip(chip)
1179 slw_cleanup_chip(chip);
1180
1181 prlog(PR_TRACE, "SLW Reinit complete !\n");
1182
1183 return OPAL_SUCCESS;
1184 }
1185
slw_patch_regs(struct proc_chip * chip)1186 static void slw_patch_regs(struct proc_chip *chip)
1187 {
1188 struct cpu_thread *c;
1189 void *image = (void *)chip->slw_base;
1190 int rc;
1191
1192 for_each_available_cpu(c) {
1193 if (c->chip_id != chip->id)
1194 continue;
1195
1196 /* Clear HRMOR */
1197 rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM,
1198 P8_SPR_HRMOR, 0,
1199 cpu_get_core_index(c),
1200 cpu_get_thread_index(c));
1201 if (rc) {
1202 log_simple_error(&e_info(OPAL_RC_SLW_REG),
1203 "SLW: Failed to set HRMOR for CPU %x\n",
1204 c->pir);
1205 }
1206
1207 /* XXX Add HIDs etc... */
1208 }
1209 }
1210
slw_init_chip_p9(struct proc_chip * chip)1211 static void slw_init_chip_p9(struct proc_chip *chip)
1212 {
1213 struct cpu_thread *c;
1214
1215 prlog(PR_DEBUG, "SLW: Init chip 0x%x\n", chip->id);
1216
1217 /* At power ON setup inits for power-mgt */
1218 for_each_available_core_in_chip(c, chip->id)
1219 slw_set_overrides_p9(chip, c);
1220
1221
1222 }
1223
slw_image_check_p9(struct proc_chip * chip)1224 static bool slw_image_check_p9(struct proc_chip *chip)
1225 {
1226
1227 if (!chip->homer_base) {
1228 log_simple_error(&e_info(OPAL_RC_SLW_REG),
1229 "SLW: HOMER base not set %x\n",
1230 chip->id);
1231 return false;
1232 } else
1233 return true;
1234
1235
1236 }
1237
slw_image_check_p8(struct proc_chip * chip)1238 static bool slw_image_check_p8(struct proc_chip *chip)
1239 {
1240 int64_t rc;
1241
1242 prlog(PR_DEBUG, "SLW: slw_check chip 0x%x\n", chip->id);
1243 if (!chip->slw_base) {
1244 prerror("SLW: No image found !\n");
1245 return false;
1246 }
1247
1248 /* Check actual image size */
1249 rc = sbe_xip_get_scalar((void *)chip->slw_base, "image_size",
1250 &chip->slw_image_size);
1251 if (rc != 0) {
1252 log_simple_error(&e_info(OPAL_RC_SLW_INIT),
1253 "SLW: Error %lld reading SLW image size\n", rc);
1254 /* XXX Panic ? */
1255 chip->slw_base = 0;
1256 chip->slw_bar_size = 0;
1257 chip->slw_image_size = 0;
1258 return false;
1259 }
1260 prlog(PR_DEBUG, "SLW: Image size from image: 0x%llx\n",
1261 chip->slw_image_size);
1262
1263 if (chip->slw_image_size > chip->slw_bar_size) {
1264 log_simple_error(&e_info(OPAL_RC_SLW_INIT),
1265 "SLW: Built-in image size larger than BAR size !\n");
1266 /* XXX Panic ? */
1267 return false;
1268 }
1269 return true;
1270
1271 }
1272
slw_late_init_p8(struct proc_chip * chip)1273 static void slw_late_init_p8(struct proc_chip *chip)
1274 {
1275
1276 prlog(PR_DEBUG, "SLW: late Init chip 0x%x\n", chip->id);
1277
1278 /* Patch SLW image */
1279 slw_patch_regs(chip);
1280
1281 }
slw_init_chip_p8(struct proc_chip * chip)1282 static void slw_init_chip_p8(struct proc_chip *chip)
1283 {
1284 struct cpu_thread *c;
1285
1286 prlog(PR_DEBUG, "SLW: Init chip 0x%x\n", chip->id);
1287 /* At power ON setup inits for fast-sleep */
1288 for_each_available_core_in_chip(c, chip->id) {
1289 idle_prepare_core(chip, c);
1290 }
1291 }
1292
1293 /* Workarounds while entering fast-sleep */
1294
fast_sleep_enter(void)1295 static void fast_sleep_enter(void)
1296 {
1297 uint32_t core = pir_to_core_id(this_cpu()->pir);
1298 uint32_t chip_id = this_cpu()->chip_id;
1299 struct cpu_thread *primary_thread;
1300 uint64_t tmp;
1301 int rc;
1302
1303 primary_thread = this_cpu()->primary;
1304
1305 rc = xscom_read(chip_id, XSCOM_ADDR_P8_EX(core, L2_FIR_ACTION1),
1306 &tmp);
1307 if (rc) {
1308 prlog(PR_WARNING, "fast_sleep_enter XSCOM failed(1):"
1309 " rc=%d chip_id=%d core=%d\n",
1310 rc, chip_id, core);
1311 return;
1312 }
1313
1314 primary_thread->save_l2_fir_action1 = tmp;
1315 primary_thread->in_fast_sleep = true;
1316
1317 tmp = tmp & ~0x0200000000000000ULL;
1318 rc = xscom_write(chip_id, XSCOM_ADDR_P8_EX(core, L2_FIR_ACTION1),
1319 tmp);
1320 if (rc) {
1321 prlog(PR_WARNING, "fast_sleep_enter XSCOM failed(2):"
1322 " rc=%d chip_id=%d core=%d\n",
1323 rc, chip_id, core);
1324 return;
1325 }
1326 rc = xscom_read(chip_id, XSCOM_ADDR_P8_EX(core, L2_FIR_ACTION1),
1327 &tmp);
1328 if (rc) {
1329 prlog(PR_WARNING, "fast_sleep_enter XSCOM failed(3):"
1330 " rc=%d chip_id=%d core=%d\n",
1331 rc, chip_id, core);
1332 return;
1333 }
1334
1335 }
1336
1337 /* Workarounds while exiting fast-sleep */
1338
fast_sleep_exit(void)1339 void fast_sleep_exit(void)
1340 {
1341 uint32_t core = pir_to_core_id(this_cpu()->pir);
1342 uint32_t chip_id = this_cpu()->chip_id;
1343 struct cpu_thread *primary_thread;
1344 int rc;
1345
1346 primary_thread = this_cpu()->primary;
1347 primary_thread->in_fast_sleep = false;
1348
1349 rc = xscom_write(chip_id, XSCOM_ADDR_P8_EX(core, L2_FIR_ACTION1),
1350 primary_thread->save_l2_fir_action1);
1351 if (rc) {
1352 prlog(PR_WARNING, "fast_sleep_exit XSCOM failed:"
1353 " rc=%d chip_id=%d core=%d\n",
1354 rc, chip_id, core);
1355 return;
1356 }
1357 }
1358
1359 /*
1360 * Setup and cleanup method for fast-sleep workarounds
1361 * state = 1 fast-sleep
1362 * enter = 1 Enter state
1363 * exit = 0 Exit state
1364 */
1365
opal_config_cpu_idle_state(uint64_t state,uint64_t enter)1366 static int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t enter)
1367 {
1368 /* Only fast-sleep for now */
1369 if (state != 1)
1370 return OPAL_PARAMETER;
1371
1372 switch(enter) {
1373 case 1:
1374 fast_sleep_enter();
1375 break;
1376 case 0:
1377 fast_sleep_exit();
1378 break;
1379 default:
1380 return OPAL_PARAMETER;
1381 }
1382
1383 return OPAL_SUCCESS;
1384 }
1385
1386 opal_call(OPAL_CONFIG_CPU_IDLE_STATE, opal_config_cpu_idle_state, 2);
1387
opal_slw_set_reg(uint64_t cpu_pir,uint64_t sprn,uint64_t val)1388 int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val)
1389 {
1390
1391 struct cpu_thread *c = find_cpu_by_pir(cpu_pir);
1392 struct proc_chip *chip;
1393 int rc;
1394
1395 if (!c) {
1396 prerror("SLW: Unknown thread with pir %x\n", (u32) cpu_pir);
1397 return OPAL_PARAMETER;
1398 }
1399
1400 chip = get_chip(c->chip_id);
1401 if (!chip) {
1402 prerror("SLW: Unknown chip for thread with pir %x\n",
1403 (u32) cpu_pir);
1404 return OPAL_PARAMETER;
1405 }
1406
1407 if (proc_gen == proc_gen_p9) {
1408 if (!has_deep_states) {
1409 prlog(PR_INFO, "SLW: Deep states not enabled\n");
1410 return OPAL_SUCCESS;
1411 }
1412
1413 if (wakeup_engine_state != WAKEUP_ENGINE_PRESENT) {
1414 log_simple_error(&e_info(OPAL_RC_SLW_REG),
1415 "SLW: wakeup_engine in bad state=%d chip=%x\n",
1416 wakeup_engine_state,chip->id);
1417 return OPAL_INTERNAL_ERROR;
1418 }
1419 rc = p9_stop_save_cpureg((void *)chip->homer_base,
1420 sprn, val, cpu_pir);
1421
1422 } else if (proc_gen == proc_gen_p8) {
1423 int spr_is_supported = 0;
1424 void *image;
1425 int i;
1426
1427 /* Check of the SPR is supported by libpore */
1428 for (i = 0; i < SLW_SPR_REGS_SIZE ; i++) {
1429 if (sprn == SLW_SPR_REGS[i].value) {
1430 spr_is_supported = 1;
1431 break;
1432 }
1433 }
1434 if (!spr_is_supported) {
1435 log_simple_error(&e_info(OPAL_RC_SLW_REG),
1436 "SLW: Trying to set unsupported spr for CPU %x\n",
1437 c->pir);
1438 return OPAL_UNSUPPORTED;
1439 }
1440 image = (void *)chip->slw_base;
1441 rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM,
1442 sprn, val,
1443 cpu_get_core_index(c),
1444 cpu_get_thread_index(c));
1445 } else {
1446 log_simple_error(&e_info(OPAL_RC_SLW_REG),
1447 "SLW: proc_gen not supported\n");
1448 return OPAL_UNSUPPORTED;
1449
1450 }
1451
1452 if (rc) {
1453 log_simple_error(&e_info(OPAL_RC_SLW_REG),
1454 "SLW: Failed to set spr %llx for CPU %x, RC=0x%x\n",
1455 sprn, c->pir, rc);
1456 return OPAL_INTERNAL_ERROR;
1457 }
1458 prlog(PR_DEBUG, "SLW: restore spr:0x%llx on c:0x%x with 0x%llx\n",
1459 sprn, c->pir, val);
1460 return OPAL_SUCCESS;
1461
1462 }
1463
1464 opal_call(OPAL_SLW_SET_REG, opal_slw_set_reg, 3);
1465
slw_init(void)1466 void slw_init(void)
1467 {
1468 struct proc_chip *chip;
1469
1470 if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) {
1471 wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT;
1472 add_cpu_idle_state_properties();
1473 return;
1474 }
1475 if (proc_gen == proc_gen_p8) {
1476 for_each_chip(chip) {
1477 slw_init_chip_p8(chip);
1478 if(slw_image_check_p8(chip))
1479 wakeup_engine_state = WAKEUP_ENGINE_PRESENT;
1480 if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT)
1481 slw_late_init_p8(chip);
1482 }
1483 p8_sbe_init_timer();
1484 } else if (proc_gen == proc_gen_p9) {
1485 for_each_chip(chip) {
1486 slw_init_chip_p9(chip);
1487 if(slw_image_check_p9(chip))
1488 wakeup_engine_state = WAKEUP_ENGINE_PRESENT;
1489 if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT)
1490 slw_late_init_p9(chip);
1491 }
1492 }
1493 add_cpu_idle_state_properties();
1494 }
1495