1 /* 2 * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h] 3 * 4 * Copyright (C) 2005 Ivan Kokshaysky 5 * Copyright (C) SAN People 6 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 7 * 8 * Parallel I/O Controller (PIO) - System peripherals registers. 9 * Based on AT91RM9200 datasheet revision E. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #ifndef AT91_PIO_H 18 #define AT91_PIO_H 19 20 21 #define AT91_ASM_PIO_RANGE 0x200 22 #define AT91_ASM_PIOC_ASR \ 23 (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) 24 #define AT91_ASM_PIOC_BSR \ 25 (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74) 26 #define AT91_ASM_PIOC_PDR \ 27 (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04) 28 #define AT91_ASM_PIOC_PUDR \ 29 (AT91_PIO_BASE + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60) 30 31 #define AT91_ASM_PIOD_PDR \ 32 (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04) 33 #define AT91_ASM_PIOD_PUDR \ 34 (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60) 35 #define AT91_ASM_PIOD_ASR \ 36 (AT91_PIO_BASE + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70) 37 38 #ifndef __ASSEMBLY__ 39 40 typedef struct at91_port { 41 u32 per; /* 0x00 PIO Enable Register */ 42 u32 pdr; /* 0x04 PIO Disable Register */ 43 u32 psr; /* 0x08 PIO Status Register */ 44 u32 reserved0; 45 u32 oer; /* 0x10 Output Enable Register */ 46 u32 odr; /* 0x14 Output Disable Registerr */ 47 u32 osr; /* 0x18 Output Status Register */ 48 u32 reserved1; 49 u32 ifer; /* 0x20 Input Filter Enable Register */ 50 u32 ifdr; /* 0x24 Input Filter Disable Register */ 51 u32 ifsr; /* 0x28 Input Filter Status Register */ 52 u32 reserved2; 53 u32 sodr; /* 0x30 Set Output Data Register */ 54 u32 codr; /* 0x34 Clear Output Data Register */ 55 u32 odsr; /* 0x38 Output Data Status Register */ 56 u32 pdsr; /* 0x3C Pin Data Status Register */ 57 u32 ier; /* 0x40 Interrupt Enable Register */ 58 u32 idr; /* 0x44 Interrupt Disable Register */ 59 u32 imr; /* 0x48 Interrupt Mask Register */ 60 u32 isr; /* 0x4C Interrupt Status Register */ 61 u32 mder; /* 0x50 Multi-driver Enable Register */ 62 u32 mddr; /* 0x54 Multi-driver Disable Register */ 63 u32 mdsr; /* 0x58 Multi-driver Status Register */ 64 u32 reserved3; 65 u32 pudr; /* 0x60 Pull-up Disable Register */ 66 u32 puer; /* 0x64 Pull-up Enable Register */ 67 u32 pusr; /* 0x68 Pad Pull-up Status Register */ 68 u32 reserved4; 69 u32 asr; /* 0x70 Select A Register */ 70 u32 bsr; /* 0x74 Select B Register */ 71 u32 absr; /* 0x78 AB Select Status Register */ 72 u32 reserved5[9]; /* */ 73 u32 ower; /* 0xA0 Output Write Enable Register */ 74 u32 owdr; /* 0xA4 Output Write Disable Register */ 75 u32 owsr; /* OxA8 utput Write Status Register */ 76 u32 reserved6[85]; 77 } at91_port_t; 78 79 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ 80 defined(CONFIG_AT91SAM9G10) || defined(CONFIG_AT91SAM9G20) 81 #define AT91_PIO_PORTS 3 82 #elif defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \ 83 defined(CONFIG_AT91SAM9M10G45) 84 #define AT91_PIO_PORTS 5 85 #elif defined(CONFIG_AT91RM9200) || defined(CONFIG_AT91CAP9) || \ 86 defined(CONFIG_AT91SAM9RL) 87 #define AT91_PIO_PORTS 4 88 #else 89 #error "Unsupported cpu. Please update at91_pio.h" 90 #endif 91 92 typedef union at91_pio { 93 struct { 94 at91_port_t pioa; 95 at91_port_t piob; 96 at91_port_t pioc; 97 #if (AT91_PIO_PORTS > 3) 98 at91_port_t piod; 99 #endif 100 #if (AT91_PIO_PORTS > 4) 101 at91_port_t pioe; 102 #endif 103 } ; 104 at91_port_t port[AT91_PIO_PORTS]; 105 } at91_pio_t; 106 107 #ifdef CONFIG_AT91_GPIO 108 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); 109 int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); 110 int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); 111 int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); 112 int at91_set_pio_output(unsigned port, unsigned pin, int value); 113 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup); 114 int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup); 115 int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on); 116 int at91_set_pio_value(unsigned port, unsigned pin, int value); 117 int at91_get_pio_value(unsigned port, unsigned pin); 118 #endif 119 #endif 120 121 #define AT91_PIO_PORTA 0x0 122 #define AT91_PIO_PORTB 0x1 123 #define AT91_PIO_PORTC 0x2 124 #define AT91_PIO_PORTD 0x3 125 #define AT91_PIO_PORTE 0x4 126 127 #ifdef CONFIG_AT91_LEGACY 128 129 #define PIO_PER 0x00 /* Enable Register */ 130 #define PIO_PDR 0x04 /* Disable Register */ 131 #define PIO_PSR 0x08 /* Status Register */ 132 #define PIO_OER 0x10 /* Output Enable Register */ 133 #define PIO_ODR 0x14 /* Output Disable Register */ 134 #define PIO_OSR 0x18 /* Output Status Register */ 135 #define PIO_IFER 0x20 /* Glitch Input Filter Enable */ 136 #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ 137 #define PIO_IFSR 0x28 /* Glitch Input Filter Status */ 138 #define PIO_SODR 0x30 /* Set Output Data Register */ 139 #define PIO_CODR 0x34 /* Clear Output Data Register */ 140 #define PIO_ODSR 0x38 /* Output Data Status Register */ 141 #define PIO_PDSR 0x3c /* Pin Data Status Register */ 142 #define PIO_IER 0x40 /* Interrupt Enable Register */ 143 #define PIO_IDR 0x44 /* Interrupt Disable Register */ 144 #define PIO_IMR 0x48 /* Interrupt Mask Register */ 145 #define PIO_ISR 0x4c /* Interrupt Status Register */ 146 #define PIO_MDER 0x50 /* Multi-driver Enable Register */ 147 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */ 148 #define PIO_MDSR 0x58 /* Multi-driver Status Register */ 149 #define PIO_PUDR 0x60 /* Pull-up Disable Register */ 150 #define PIO_PUER 0x64 /* Pull-up Enable Register */ 151 #define PIO_PUSR 0x68 /* Pull-up Status Register */ 152 #define PIO_ASR 0x70 /* Peripheral A Select Register */ 153 #define PIO_BSR 0x74 /* Peripheral B Select Register */ 154 #define PIO_ABSR 0x78 /* AB Status Register */ 155 #define PIO_OWER 0xa0 /* Output Write Enable Register */ 156 #define PIO_OWDR 0xa4 /* Output Write Disable Register */ 157 #define PIO_OWSR 0xa8 /* Output Write Status Register */ 158 #endif 159 160 #endif 161