1 /* 2 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h] 3 * 4 * Copyright (C) 2007 Atmel Corporation 5 * 6 * Common definitions. 7 * Based on AT91SAM9RL datasheet revision A. (Preliminary) 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file COPYING in the main directory of this archive for 11 * more details. 12 */ 13 14 #ifndef AT91SAM9RL_H 15 #define AT91SAM9RL_H 16 17 /* 18 * Peripheral identifiers/interrupts. 19 */ 20 #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 21 #define AT91_ID_SYS 1 /* System Controller */ 22 #define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ 23 #define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ 24 #define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ 25 #define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ 26 #define AT91SAM9RL_ID_US0 6 /* USART 0 */ 27 #define AT91SAM9RL_ID_US1 7 /* USART 1 */ 28 #define AT91SAM9RL_ID_US2 8 /* USART 2 */ 29 #define AT91SAM9RL_ID_US3 9 /* USART 3 */ 30 #define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ 31 #define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ 32 #define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ 33 #define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ 34 #define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ 35 #define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ 36 #define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ 37 #define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ 38 #define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ 39 #define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ 40 #define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ 41 #define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ 42 #define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ 43 #define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ 44 #define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ 45 #define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ 46 47 #define AT91_SDRAMC_BASE 0xffffea00 48 #define AT91_SMC_BASE 0xffffec00 49 #define AT91_MATRIX_BASE 0xffffee00 50 #define AT91_PIO_BASE 0xfffff400 51 #define AT91_PMC_BASE 0xfffffc00 52 #define AT91_RSTC_BASE 0xfffffd00 53 #define AT91_PIT_BASE 0xfffffd30 54 #define AT91_WDT_BASE 0xfffffd40 55 56 #ifdef CONFIG_AT91_LEGACY 57 58 /* 59 * User Peripheral physical base addresses. 60 */ 61 #define AT91SAM9RL_BASE_TCB0 0xfffa0000 62 #define AT91SAM9RL_BASE_TC0 0xfffa0000 63 #define AT91SAM9RL_BASE_TC1 0xfffa0040 64 #define AT91SAM9RL_BASE_TC2 0xfffa0080 65 #define AT91SAM9RL_BASE_MCI 0xfffa4000 66 #define AT91SAM9RL_BASE_TWI0 0xfffa8000 67 #define AT91SAM9RL_BASE_TWI1 0xfffac000 68 #define AT91SAM9RL_BASE_US0 0xfffb0000 69 #define AT91SAM9RL_BASE_US1 0xfffb4000 70 #define AT91SAM9RL_BASE_US2 0xfffb8000 71 #define AT91SAM9RL_BASE_US3 0xfffbc000 72 #define AT91SAM9RL_BASE_SSC0 0xfffc0000 73 #define AT91SAM9RL_BASE_SSC1 0xfffc4000 74 #define AT91SAM9RL_BASE_PWMC 0xfffc8000 75 #define AT91SAM9RL_BASE_SPI 0xfffcc000 76 #define AT91SAM9RL_BASE_TSC 0xfffd0000 77 #define AT91SAM9RL_BASE_UDPHS 0xfffd4000 78 #define AT91SAM9RL_BASE_AC97C 0xfffd8000 79 #define AT91_BASE_SYS 0xffffc000 80 81 /* 82 * System Peripherals (offset from AT91_BASE_SYS) 83 */ 84 #define AT91_DMA (0xffffe600 - AT91_BASE_SYS) 85 #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) 86 #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) 87 #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 88 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 89 #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) 90 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 91 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) 92 #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) 93 #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) 94 #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) 95 #define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) 96 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 97 #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 98 #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 99 #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) 100 #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) 101 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 102 #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) 103 #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 104 #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) 105 106 #define AT91_USART0 AT91SAM9RL_BASE_US0 107 #define AT91_USART1 AT91SAM9RL_BASE_US1 108 #define AT91_USART2 AT91SAM9RL_BASE_US2 109 #define AT91_USART3 AT91SAM9RL_BASE_US3 110 111 #endif /* CONFIG_AT91_LEGACY */ 112 113 /* 114 * Internal Memory. 115 */ 116 #define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 117 #define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ 118 119 #define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ 120 #define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ 121 122 #define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ 123 #define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ 124 125 /* 126 * Cpu Name 127 */ 128 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9RL" 129 130 #endif 131