1 /* 2 * MCF520x Internal Memory Map 3 * 4 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __IMMAP_520X__ 27 #define __IMMAP_520X__ 28 29 #define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) 30 #define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) 31 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) 32 #define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000) 33 #define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000) 34 #define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) 35 #define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) 36 #define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000) 37 #define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) 38 #define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000) 39 #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) 40 #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) 41 #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) 42 #define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) 43 #define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) 44 #define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) 45 #define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) 46 #define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) 47 #define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) 48 #define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00088000) 49 #define MMAP_WDOG (CONFIG_SYS_MBAR + 0x0008C000) 50 #define MMAP_PLL (CONFIG_SYS_MBAR + 0x00090000) 51 #define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) 52 #define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) 53 #define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) 54 #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000A8000) 55 56 #include <asm/coldfire/crossbar.h> 57 #include <asm/coldfire/edma.h> 58 #include <asm/coldfire/eport.h> 59 #include <asm/coldfire/flexbus.h> 60 #include <asm/coldfire/intctrl.h> 61 #include <asm/coldfire/qspi.h> 62 63 /* System Controller Module */ 64 typedef struct scm1 { 65 u32 mpr; /* 0x00 Master Privilege */ 66 u32 rsvd1[7]; 67 u32 pacra; /* 0x20 Peripheral Access Ctrl A */ 68 u32 pacrb; /* 0x24 Peripheral Access Ctrl B */ 69 u32 pacrc; /* 0x28 Peripheral Access Ctrl C */ 70 u32 pacrd; /* 0x2C Peripheral Access Ctrl D */ 71 u32 rsvd2[4]; 72 u32 pacre; /* 0x40 Peripheral Access Ctrl E */ 73 u32 pacrf; /* 0x44 Peripheral Access Ctrl F */ 74 u32 rsvd3[3]; 75 u32 bmt; /* 0x50 bus monitor */ 76 } scm1_t; 77 78 typedef struct scm2 { 79 u8 rsvd1[19]; /* 0x00 - 0x12 */ 80 u8 wcr; /* 0x13 */ 81 u16 rsvd2; /* 0x14 - 0x15 */ 82 u16 cwcr; /* 0x16 */ 83 u8 rsvd3[3]; /* 0x18 - 0x1A */ 84 u8 cwsr; /* 0x1B */ 85 u8 rsvd4[3]; /* 0x1C - 0x1E */ 86 u8 scmisr; /* 0x1F */ 87 u8 rsvd5[79]; /* 0x20 - 0x6F */ 88 u32 cfadr; /* 0x70 */ 89 u8 rsvd7; /* 0x74 */ 90 u8 cfier; /* 0x75 */ 91 u8 cfloc; /* 0x76 */ 92 u8 cfatr; /* 0x77 */ 93 u32 rsvd8; /* 0x78 - 0x7B */ 94 u32 cfdtr; /* 0x7C */ 95 } scm2_t; 96 97 /* Chip configuration module */ 98 typedef struct rcm { 99 u8 rcr; 100 u8 rsr; 101 } rcm_t; 102 103 typedef struct ccm_ctrl { 104 u16 ccr; /* 0x00 Chip Cfg */ 105 u16 res1; /* 0x02 */ 106 u16 rcon; /* 0x04 Reset Cfg */ 107 u16 cir; /* 0x06 Chip ID */ 108 } ccm_t; 109 110 /* GPIO port */ 111 typedef struct gpio_ctrl { 112 /* Port Output Data */ 113 u8 podr_busctl; /* 0x00 */ 114 u8 podr_be; /* 0x01 */ 115 u8 podr_cs; /* 0x02 */ 116 u8 podr_feci2c; /* 0x03 */ 117 u8 podr_qspi; /* 0x04 */ 118 u8 podr_timer; /* 0x05 */ 119 u8 podr_uart; /* 0x06 */ 120 u8 podr_fech; /* 0x07 */ 121 u8 podr_fecl; /* 0x08 */ 122 u8 res01[3]; /* 0x9 - 0x0B */ 123 124 /* Port Data Direction */ 125 u8 pddr_busctl; /* 0x0C */ 126 u8 pddr_be; /* 0x0D */ 127 u8 pddr_cs; /* 0x0E */ 128 u8 pddr_feci2c; /* 0x0F */ 129 u8 pddr_qspi; /* 0x10*/ 130 u8 pddr_timer; /* 0x11 */ 131 u8 pddr_uart; /* 0x12 */ 132 u8 pddr_fech; /* 0x13 */ 133 u8 pddr_fecl; /* 0x14 */ 134 u8 res02[5]; /* 0x15 - 0x19 */ 135 136 /* Port Data Direction */ 137 u8 ppdr_cs; /* 0x1A */ 138 u8 ppdr_feci2c; /* 0x1B */ 139 u8 ppdr_qspi; /* 0x1C */ 140 u8 ppdr_timer; /* 0x1D */ 141 u8 ppdr_uart; /* 0x1E */ 142 u8 ppdr_fech; /* 0x1F */ 143 u8 ppdr_fecl; /* 0x20 */ 144 u8 res03[3]; /* 0x21 - 0x23 */ 145 146 /* Port Clear Output Data */ 147 u8 pclrr_busctl; /* 0x24 */ 148 u8 pclrr_be; /* 0x25 */ 149 u8 pclrr_cs; /* 0x26 */ 150 u8 pclrr_feci2c; /* 0x27 */ 151 u8 pclrr_qspi; /* 0x28 */ 152 u8 pclrr_timer; /* 0x29 */ 153 u8 pclrr_uart; /* 0x2A */ 154 u8 pclrr_fech; /* 0x2B */ 155 u8 pclrr_fecl; /* 0x2C */ 156 u8 res04[3]; /* 0x2D - 0x2F */ 157 158 /* Pin Assignment */ 159 u8 par_busctl; /* 0x30 */ 160 u8 par_be; /* 0x31 */ 161 u8 par_cs; /* 0x32 */ 162 u8 par_feci2c; /* 0x33 */ 163 u8 par_qspi; /* 0x34 */ 164 u8 par_timer; /* 0x35 */ 165 u16 par_uart; /* 0x36 */ 166 u8 par_fec; /* 0x38 */ 167 u8 par_irq; /* 0x39 */ 168 169 /* Mode Select Control */ 170 /* Drive Strength Control */ 171 u8 mscr_fb; /* 0x3A */ 172 u8 mscr_sdram; /* 0x3B */ 173 174 u8 dscr_i2c; /* 0x3C */ 175 u8 dscr_misc; /* 0x3D */ 176 u8 dscr_fec; /* 0x3E */ 177 u8 dscr_uart; /* 0x3F */ 178 u8 dscr_qspi; /* 0x40 */ 179 } gpio_t; 180 181 /* SDRAM controller */ 182 typedef struct sdram_ctrl { 183 u32 mode; /* 0x00 Mode/Extended Mode */ 184 u32 ctrl; /* 0x04 Ctrl */ 185 u32 cfg1; /* 0x08 Cfg 1 */ 186 u32 cfg2; /* 0x0C Cfg 2 */ 187 u32 res1[64]; /* 0x10 - 0x10F */ 188 u32 cs0; /* 0x110 Chip Select 0 Cfg */ 189 u32 cs1; /* 0x114 Chip Select 1 Cfg */ 190 } sdram_t; 191 192 /* Clock Module */ 193 typedef struct pll_ctrl { 194 u8 odr; /* 0x00 Output divider */ 195 u8 rsvd1; 196 u8 cr; /* 0x02 Control */ 197 u8 rsvd2; 198 u8 mdr; /* 0x04 Modulation Divider */ 199 u8 rsvd3; 200 u8 fdr; /* 0x06 Feedback Divider */ 201 u8 rsvd4; 202 } pll_t; 203 204 /* Watchdog registers */ 205 typedef struct wdog_ctrl { 206 u16 cr; /* 0x00 Control */ 207 u16 mr; /* 0x02 Modulus */ 208 u16 cntr; /* 0x04 Count */ 209 u16 sr; /* 0x06 Service */ 210 } wdog_t; 211 212 #endif /* __IMMAP_520X__ */ 213