1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2004-2008 Freescale Semiconductor, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * xpedite5200 board configuration file 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* 31 * High Level Configuration Options 32 */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 37 #define CONFIG_XPEDITE5200 1 38 #define CONFIG_SYS_BOARD_NAME "XPedite5200" 39 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 40 41 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 42 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ 43 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 44 #define CONFIG_PCI1 1 /* PCI controller 1 */ 45 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 46 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 47 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 48 49 /* 50 * DDR config 51 */ 52 #define CONFIG_FSL_DDR2 53 #undef CONFIG_FSL_DDR_INTERACTIVE 54 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 55 #define CONFIG_DDR_SPD 56 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 57 #define SPD_EEPROM_ADDRESS 0x54 58 #define CONFIG_NUM_DDR_CONTROLLERS 1 59 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 60 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 61 #define CONFIG_DDR_ECC 62 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 63 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 64 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 65 #define CONFIG_VERY_BIG_RAM 66 67 #define CONFIG_SYS_CLK_FREQ 66666666 68 69 /* 70 * These can be toggled for performance analysis, otherwise use default. 71 */ 72 #define CONFIG_L2_CACHE /* toggle L2 cache */ 73 #define CONFIG_BTB /* toggle branch predition */ 74 #define CONFIG_ENABLE_36BIT_PHYS 1 75 76 /* 77 * Base addresses -- Note these are effective addresses where the 78 * actual resources get mapped (not physical addresses) 79 */ 80 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 81 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ 82 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 83 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 84 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) 85 86 /* 87 * Diagnostics 88 */ 89 #define CONFIG_SYS_ALT_MEMTEST 90 #define CONFIG_SYS_MEMTEST_START 0x10000000 91 #define CONFIG_SYS_MEMTEST_END 0x20000000 92 93 /* 94 * Memory map 95 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 96 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable 97 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 98 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable 99 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 100 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 101 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable 102 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable 103 */ 104 105 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 106 107 /* 108 * NAND flash configuration 109 */ 110 #define CONFIG_SYS_NAND_BASE 0xef800000 111 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 112 #define CONFIG_SYS_MAX_NAND_DEVICE 1 113 #define CONFIG_NAND_ACTL 114 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ 115 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ 116 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ 117 #define CONFIG_SYS_NAND_ACTL_DELAY 25 118 119 /* 120 * NOR flash configuration 121 */ 122 #define CONFIG_SYS_FLASH_BASE 0xfc000000 123 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 124 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 125 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 126 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 127 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 128 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 129 #define CONFIG_FLASH_CFI_DRIVER 130 #define CONFIG_SYS_FLASH_CFI 131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 132 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 133 {0xfbf40000, 0xc0000} } 134 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 135 136 /* 137 * Chip select configuration 138 */ 139 /* NOR Flash 0 on CS0 */ 140 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 141 BR_PS_16 | \ 142 BR_V) 143 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ 144 OR_GPCM_ACS_DIV4 | \ 145 OR_GPCM_SCY_8) 146 147 /* NOR Flash 1 on CS1 */ 148 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 149 BR_PS_16 | \ 150 BR_V) 151 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 152 153 /* NAND flash on CS2 */ 154 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 155 BR_PS_8 | \ 156 BR_V) 157 158 /* NAND flash on CS2 */ 159 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 160 OR_GPCM_BCTLD | \ 161 OR_GPCM_CSNT | \ 162 OR_GPCM_ACS_DIV4 | \ 163 OR_GPCM_SCY_4 | \ 164 OR_GPCM_TRLX | \ 165 OR_GPCM_EHTR) 166 167 /* NAND flash on CS3 */ 168 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 169 BR_PS_8 | \ 170 BR_V) 171 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 172 173 /* 174 * Use L1 as initial stack 175 */ 176 #define CONFIG_SYS_INIT_RAM_LOCK 1 177 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 178 #define CONFIG_SYS_INIT_RAM_END 0x4000 179 180 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 181 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 182 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 183 184 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 185 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 186 187 /* 188 * Serial Port 189 */ 190 #define CONFIG_CONS_INDEX 1 191 #define CONFIG_SYS_NS16550 192 #define CONFIG_SYS_NS16550_SERIAL 193 #define CONFIG_SYS_NS16550_REG_SIZE 1 194 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 195 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 196 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 197 #define CONFIG_SYS_BAUDRATE_TABLE \ 198 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 199 #define CONFIG_BAUDRATE 115200 200 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 201 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 202 203 /* 204 * Use the HUSH parser 205 */ 206 #define CONFIG_SYS_HUSH_PARSER 207 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 208 209 /* 210 * Pass open firmware flat tree 211 */ 212 #define CONFIG_OF_LIBFDT 1 213 #define CONFIG_OF_BOARD_SETUP 1 214 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 215 216 /* 217 * I2C 218 */ 219 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 220 #define CONFIG_HARD_I2C /* I2C with hardware support */ 221 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 222 #define CONFIG_SYS_I2C_SLAVE 0x7F 223 #define CONFIG_SYS_I2C_OFFSET 0x3000 224 #define CONFIG_SYS_I2C2_OFFSET 0x3100 225 #define CONFIG_I2C_MULTI_BUS 226 227 /* I2C EEPROM */ 228 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 229 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 231 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 232 233 /* I2C RTC */ 234 #define CONFIG_RTC_M41T11 1 235 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 236 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 237 238 /* GPIO */ 239 #define CONFIG_PCA953X 240 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 241 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 242 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 243 244 /* PCA957 @ 0x18 */ 245 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 246 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 247 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 248 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 249 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 250 #define CONFIG_SYS_PCA953X_FLASH_WP 0x20 251 #define CONFIG_SYS_PCA953X_MONARCH 0x40 252 #define CONFIG_SYS_PCA953X_EREADY 0x80 253 254 /* PCA957 @ 0x19 */ 255 #define CONFIG_SYS_PCA953X_P14_IO0 0x01 256 #define CONFIG_SYS_PCA953X_P14_IO1 0x02 257 #define CONFIG_SYS_PCA953X_P14_IO2 0x04 258 #define CONFIG_SYS_PCA953X_P14_IO3 0x08 259 #define CONFIG_SYS_PCA953X_P14_IO4 0x10 260 #define CONFIG_SYS_PCA953X_P14_IO5 0x20 261 #define CONFIG_SYS_PCA953X_P14_IO6 0x40 262 #define CONFIG_SYS_PCA953X_P14_IO7 0x80 263 264 /* 265 * General PCI 266 * Memory space is mapped 1-1, but I/O space must start from 0. 267 */ 268 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 269 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 270 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ 271 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 272 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 273 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ 274 275 /* 276 * Networking options 277 */ 278 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 279 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 280 #define CONFIG_NET_MULTI 1 281 #define CONFIG_MII 1 /* MII PHY management */ 282 #define CONFIG_ETHPRIME "eTSEC1" 283 284 #define CONFIG_TSEC1 1 285 #define CONFIG_TSEC1_NAME "eTSEC1" 286 #define TSEC1_FLAGS TSEC_GIGABIT 287 #define TSEC1_PHY_ADDR 1 288 #define TSEC1_PHYIDX 0 289 #define CONFIG_HAS_ETH0 290 291 #define CONFIG_TSEC2 1 292 #define CONFIG_TSEC2_NAME "eTSEC2" 293 #define TSEC2_FLAGS TSEC_GIGABIT 294 #define TSEC2_PHY_ADDR 2 295 #define TSEC2_PHYIDX 0 296 #define CONFIG_HAS_ETH1 297 298 #define CONFIG_TSEC3 1 299 #define CONFIG_TSEC3_NAME "eTSEC3" 300 #define TSEC3_FLAGS TSEC_GIGABIT 301 #define TSEC3_PHY_ADDR 3 302 #define TSEC3_PHYIDX 0 303 #define CONFIG_HAS_ETH2 304 305 #define CONFIG_TSEC4 1 306 #define CONFIG_TSEC4_NAME "eTSEC4" 307 #define TSEC4_FLAGS TSEC_GIGABIT 308 #define TSEC4_PHY_ADDR 4 309 #define TSEC4_PHYIDX 0 310 #define CONFIG_HAS_ETH3 311 312 /* 313 * BOOTP options 314 */ 315 #define CONFIG_BOOTP_BOOTFILESIZE 316 #define CONFIG_BOOTP_BOOTPATH 317 #define CONFIG_BOOTP_GATEWAY 318 319 /* 320 * Command configuration. 321 */ 322 #include <config_cmd_default.h> 323 324 #define CONFIG_CMD_ASKENV 325 #define CONFIG_CMD_DATE 326 #define CONFIG_CMD_DHCP 327 #define CONFIG_CMD_EEPROM 328 #define CONFIG_CMD_ELF 329 #define CONFIG_CMD_SAVEENV 330 #define CONFIG_CMD_FLASH 331 #define CONFIG_CMD_I2C 332 #define CONFIG_CMD_JFFS2 333 #define CONFIG_CMD_MII 334 #define CONFIG_CMD_NAND 335 #define CONFIG_CMD_NET 336 #define CONFIG_CMD_PCA953X 337 #define CONFIG_CMD_PCA953X_INFO 338 #define CONFIG_CMD_PCI 339 #define CONFIG_CMD_PING 340 #define CONFIG_CMD_SNTP 341 342 /* 343 * Miscellaneous configurable options 344 */ 345 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 346 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 347 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 348 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 349 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 350 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 351 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 352 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 353 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 354 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 355 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ 356 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 357 #define CONFIG_PREBOOT /* enable preboot variable */ 358 #define CONFIG_FIT 1 359 #define CONFIG_FIT_VERBOSE 1 360 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 361 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 362 363 /* 364 * For booting Linux, the board info and command line data 365 * have to be in the first 16 MB of memory, since this is 366 * the maximum mapped by the Linux kernel during initialization. 367 */ 368 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 369 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 370 371 /* 372 * Boot Flags 373 */ 374 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 375 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 376 377 /* 378 * Environment Configuration 379 */ 380 #define CONFIG_ENV_IS_IN_FLASH 1 381 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 382 #define CONFIG_ENV_SIZE 0x8000 383 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 384 385 /* 386 * Flash memory map: 387 * fff80000 - ffffffff Pri U-Boot (512 KB) 388 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 389 * fff00000 - fff3ffff Pri FDT (256KB) 390 * fef00000 - ffefffff Pri OS image (16MB) 391 * fc000000 - feefffff Pri OS Use/Filesystem (47MB) 392 * 393 * fbf80000 - fbffffff Sec U-Boot (512 KB) 394 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) 395 * fbf00000 - fbf3ffff Sec FDT (256KB) 396 * faf00000 - fbefffff Sec OS image (16MB) 397 * f8000000 - faefffff Sec OS Use/Filesystem (47MB) 398 */ 399 #define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000) 400 #define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000) 401 #define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000) 402 #define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000) 403 #define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) 404 #define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000) 405 406 #define CONFIG_PROG_UBOOT1 \ 407 "$download_cmd $loadaddr $ubootfile; " \ 408 "if test $? -eq 0; then " \ 409 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 410 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 411 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 412 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 413 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 414 "if test $? -ne 0; then " \ 415 "echo PROGRAM FAILED; " \ 416 "else; " \ 417 "echo PROGRAM SUCCEEDED; " \ 418 "fi; " \ 419 "else; " \ 420 "echo DOWNLOAD FAILED; " \ 421 "fi;" 422 423 #define CONFIG_PROG_UBOOT2 \ 424 "$download_cmd $loadaddr $ubootfile; " \ 425 "if test $? -eq 0; then " \ 426 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 427 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 428 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 429 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 430 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 431 "if test $? -ne 0; then " \ 432 "echo PROGRAM FAILED; " \ 433 "else; " \ 434 "echo PROGRAM SUCCEEDED; " \ 435 "fi; " \ 436 "else; " \ 437 "echo DOWNLOAD FAILED; " \ 438 "fi;" 439 440 #define CONFIG_BOOT_OS_NET \ 441 "$download_cmd $osaddr $osfile; " \ 442 "if test $? -eq 0; then " \ 443 "if test -n $fdtaddr; then " \ 444 "$download_cmd $fdtaddr $fdtfile; " \ 445 "if test $? -eq 0; then " \ 446 "bootm $osaddr - $fdtaddr; " \ 447 "else; " \ 448 "echo FDT DOWNLOAD FAILED; " \ 449 "fi; " \ 450 "else; " \ 451 "bootm $osaddr; " \ 452 "fi; " \ 453 "else; " \ 454 "echo OS DOWNLOAD FAILED; " \ 455 "fi;" 456 457 #define CONFIG_PROG_OS1 \ 458 "$download_cmd $osaddr $osfile; " \ 459 "if test $? -eq 0; then " \ 460 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 461 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 462 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 463 "if test $? -ne 0; then " \ 464 "echo OS PROGRAM FAILED; " \ 465 "else; " \ 466 "echo OS PROGRAM SUCCEEDED; " \ 467 "fi; " \ 468 "else; " \ 469 "echo OS DOWNLOAD FAILED; " \ 470 "fi;" 471 472 #define CONFIG_PROG_OS2 \ 473 "$download_cmd $osaddr $osfile; " \ 474 "if test $? -eq 0; then " \ 475 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 476 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 477 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 478 "if test $? -ne 0; then " \ 479 "echo OS PROGRAM FAILED; " \ 480 "else; " \ 481 "echo OS PROGRAM SUCCEEDED; " \ 482 "fi; " \ 483 "else; " \ 484 "echo OS DOWNLOAD FAILED; " \ 485 "fi;" 486 487 #define CONFIG_PROG_FDT1 \ 488 "$download_cmd $fdtaddr $fdtfile; " \ 489 "if test $? -eq 0; then " \ 490 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 491 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 492 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 493 "if test $? -ne 0; then " \ 494 "echo FDT PROGRAM FAILED; " \ 495 "else; " \ 496 "echo FDT PROGRAM SUCCEEDED; " \ 497 "fi; " \ 498 "else; " \ 499 "echo FDT DOWNLOAD FAILED; " \ 500 "fi;" 501 502 #define CONFIG_PROG_FDT2 \ 503 "$download_cmd $fdtaddr $fdtfile; " \ 504 "if test $? -eq 0; then " \ 505 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 506 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 507 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 508 "if test $? -ne 0; then " \ 509 "echo FDT PROGRAM FAILED; " \ 510 "else; " \ 511 "echo FDT PROGRAM SUCCEEDED; " \ 512 "fi; " \ 513 "else; " \ 514 "echo FDT DOWNLOAD FAILED; " \ 515 "fi;" 516 517 #define CONFIG_EXTRA_ENV_SETTINGS \ 518 "autoload=yes\0" \ 519 "download_cmd=tftp\0" \ 520 "console_args=console=ttyS0,115200\0" \ 521 "root_args=root=/dev/nfs rw\0" \ 522 "misc_args=ip=on\0" \ 523 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 524 "bootfile=/home/user/file\0" \ 525 "osfile=/home/user/uImage-XPedite5200\0" \ 526 "fdtfile=/home/user/xpedite5200.dtb\0" \ 527 "ubootfile=/home/user/u-boot.bin\0" \ 528 "fdtaddr=c00000\0" \ 529 "osaddr=0x1000000\0" \ 530 "loadaddr=0x1000000\0" \ 531 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 532 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 533 "prog_os1="CONFIG_PROG_OS1"\0" \ 534 "prog_os2="CONFIG_PROG_OS2"\0" \ 535 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 536 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 537 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 538 "bootcmd_flash1=run set_bootargs; " \ 539 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 540 "bootcmd_flash2=run set_bootargs; " \ 541 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 542 "bootcmd=run bootcmd_flash1\0" 543 #endif /* __CONFIG_H */ 544