1 /*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25
26 /*
27 * Ethernet test
28 *
29 * The Serial Communication Controllers (SCC) listed in ctlr_list array below
30 * are tested in the loopback ethernet mode.
31 * The controllers are configured accordingly and several packets
32 * are transmitted. The configurable test parameters are:
33 * MIN_PACKET_LENGTH - minimum size of packet to transmit
34 * MAX_PACKET_LENGTH - maximum size of packet to transmit
35 * TEST_NUM - number of tests
36 */
37
38 #include <post.h>
39 #if CONFIG_POST & CONFIG_SYS_POST_ETHER
40 #if defined(CONFIG_8xx)
41 #include <commproc.h>
42 #elif defined(CONFIG_MPC8260)
43 #include <asm/cpm_8260.h>
44 #else
45 #error "Apparently a bad configuration, please fix."
46 #endif
47
48 #include <command.h>
49 #include <net.h>
50 #include <serial.h>
51
52 DECLARE_GLOBAL_DATA_PTR;
53
54 #define MIN_PACKET_LENGTH 64
55 #define MAX_PACKET_LENGTH 256
56 #define TEST_NUM 1
57
58 #define CTLR_SCC 0
59
60 extern void spi_init_f (void);
61 extern void spi_init_r (void);
62
63 /* The list of controllers to test */
64 #if defined(CONFIG_MPC823)
65 static int ctlr_list[][2] = { {CTLR_SCC, 1} };
66 #else
67 static int ctlr_list[][2] = { };
68 #endif
69
70 #define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
71
72 static struct {
73 void (*init) (int index);
74 void (*halt) (int index);
75 int (*send) (int index, volatile void *packet, int length);
76 int (*recv) (int index, void *packet, int length);
77 } ctlr_proc[1];
78
79 static char *ctlr_name[1] = { "SCC" };
80
81 /* Ethernet Transmit and Receive Buffers */
82 #define DBUF_LENGTH 1520
83
84 #define TX_BUF_CNT 2
85
86 #define TOUT_LOOP 100
87
88 static char txbuf[DBUF_LENGTH];
89
90 static uint rxIdx; /* index of the current RX buffer */
91 static uint txIdx; /* index of the current TX buffer */
92
93 /*
94 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
95 * immr->udata_bd address on Dual-Port RAM
96 * Provide for Double Buffering
97 */
98
99 typedef volatile struct CommonBufferDescriptor {
100 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
101 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
102 } RTXBD;
103
104 static RTXBD *rtx;
105
106 /*
107 * SCC callbacks
108 */
109
scc_init(int scc_index)110 static void scc_init (int scc_index)
111 {
112 uchar ea[6];
113
114 static int proff[] = {
115 PROFF_SCC1,
116 PROFF_SCC2,
117 PROFF_SCC3,
118 PROFF_SCC4,
119 };
120 static unsigned int cpm_cr[] = {
121 CPM_CR_CH_SCC1,
122 CPM_CR_CH_SCC2,
123 CPM_CR_CH_SCC3,
124 CPM_CR_CH_SCC4,
125 };
126
127 int i;
128 scc_enet_t *pram_ptr;
129
130 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
131
132 immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
133 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
134
135 #if defined(CONFIG_FADS)
136 #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC86xADS)
137 /* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */
138 *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
139 *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
140 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
141 #else
142 *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
143 *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
144 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
145 #endif
146 #endif
147
148 pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]);
149
150 rxIdx = 0;
151 txIdx = 0;
152
153 #ifdef CONFIG_SYS_ALLOC_DPRAM
154 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
155 dpram_alloc_align (sizeof (RTXBD), 8));
156 #else
157 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
158 #endif
159
160 #if 0
161
162 #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
163 /* Configure port A pins for Txd and Rxd.
164 */
165 immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
166 immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
167 immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
168 #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
169 /* Configure port B pins for Txd and Rxd.
170 */
171 immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
172 immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
173 immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
174 #else
175 #error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
176 #endif
177
178 #if defined(PC_ENET_LBK)
179 /* Configure port C pins to disable External Loopback
180 */
181 immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
182 immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
183 immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
184 immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
185 #endif /* PC_ENET_LBK */
186
187 /* Configure port C pins to enable CLSN and RENA.
188 */
189 immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
190 immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
191 immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
192
193 /* Configure port A for TCLK and RCLK.
194 */
195 immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
196 immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
197
198 /*
199 * Configure Serial Interface clock routing -- see section 16.7.5.3
200 * First, clear all SCC bits to zero, then set the ones we want.
201 */
202
203 immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
204 immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
205 #else
206 /*
207 * SCC2 receive clock is BRG2
208 * SCC2 transmit clock is BRG3
209 */
210 immr->im_cpm.cp_brgc2 = 0x0001000C;
211 immr->im_cpm.cp_brgc3 = 0x0001000C;
212
213 immr->im_cpm.cp_sicr &= ~0x00003F00;
214 immr->im_cpm.cp_sicr |= 0x00000a00;
215 #endif /* 0 */
216
217
218 /*
219 * Initialize SDCR -- see section 16.9.23.7
220 * SDMA configuration register
221 */
222 immr->im_siu_conf.sc_sdcr = 0x01;
223
224
225 /*
226 * Setup SCC Ethernet Parameter RAM
227 */
228
229 pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
230 pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
231
232 pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
233
234 pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
235 pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
236
237 /*
238 * Setup Receiver Buffer Descriptors (13.14.24.18)
239 * Settings:
240 * Empty, Wrap
241 */
242
243 for (i = 0; i < PKTBUFSRX; i++) {
244 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
245 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
246 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
247 }
248
249 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
250
251 /*
252 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
253 * Settings:
254 * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
255 */
256
257 for (i = 0; i < TX_BUF_CNT; i++) {
258 rtx->txbd[i].cbd_sc =
259 (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
260 rtx->txbd[i].cbd_datlen = 0; /* Reset */
261 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
262 }
263
264 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
265
266 /*
267 * Enter Command: Initialize Rx Params for SCC
268 */
269
270 do { /* Spin until ready to issue command */
271 __asm__ ("eieio");
272 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
273 /* Issue command */
274 immr->im_cpm.cp_cpcr =
275 ((CPM_CR_INIT_RX << 8) | (cpm_cr[scc_index] << 4) |
276 CPM_CR_FLG);
277 do { /* Spin until command processed */
278 __asm__ ("eieio");
279 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
280
281 /*
282 * Ethernet Specific Parameter RAM
283 * see table 13-16, pg. 660,
284 * pg. 681 (example with suggested settings)
285 */
286
287 pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
288 pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
289 pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
290 pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
291 pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
292 pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
293
294 pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
295 pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
296 pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
297
298 pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
299 pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
300
301 pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
302 pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
303 pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
304 pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
305
306 eth_getenv_enetaddr("ethaddr", ea);
307 pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
308 pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
309 pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
310
311 pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
312 pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
313 pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
314 pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
315 pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
316 pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
317 pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
318 pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
319
320 /*
321 * Enter Command: Initialize Tx Params for SCC
322 */
323
324 do { /* Spin until ready to issue command */
325 __asm__ ("eieio");
326 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
327 /* Issue command */
328 immr->im_cpm.cp_cpcr =
329 ((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) |
330 CPM_CR_FLG);
331 do { /* Spin until command processed */
332 __asm__ ("eieio");
333 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
334
335 /*
336 * Mask all Events in SCCM - we use polling mode
337 */
338 immr->im_cpm.cp_scc[scc_index].scc_sccm = 0;
339
340 /*
341 * Clear Events in SCCE -- Clear bits by writing 1's
342 */
343
344 immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0);
345
346
347 /*
348 * Initialize GSMR High 32-Bits
349 * Settings: Normal Mode
350 */
351
352 immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0;
353
354 /*
355 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
356 * Settings:
357 * TCI = Invert
358 * TPL = 48 bits
359 * TPP = Repeating 10's
360 * LOOP = Loopback
361 * MODE = Ethernet
362 */
363
364 immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI |
365 SCC_GSMRL_TPL_48 |
366 SCC_GSMRL_TPP_10 |
367 SCC_GSMRL_DIAG_LOOP |
368 SCC_GSMRL_MODE_ENET);
369
370 /*
371 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
372 */
373
374 immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555;
375
376 /*
377 * Initialize the PSMR
378 * Settings:
379 * CRC = 32-Bit CCITT
380 * NIB = Begin searching for SFD 22 bits after RENA
381 * LPB = Loopback Enable (Needed when FDE is set)
382 */
383 immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
384 SCC_PSMR_NIB22 | SCC_PSMR_LPB;
385
386 #if 0
387 /*
388 * Configure Ethernet TENA Signal
389 */
390
391 #if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
392 immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
393 immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
394 #elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
395 immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
396 immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
397 #else
398 #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
399 #endif
400
401 #if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
402 /*
403 * Port C is used to control the PHY,MC68160.
404 */
405 immr->im_ioport.iop_pcdir |=
406 (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
407
408 immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
409 immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
410 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
411 #endif /* MPC860ADS */
412
413 #if defined(CONFIG_AMX860)
414 /*
415 * Port B is used to control the PHY,MC68160.
416 */
417 immr->im_cpm.cp_pbdir |=
418 (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
419
420 immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
421 immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
422
423 immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
424 immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
425 #endif /* AMX860 */
426
427 #endif /* 0 */
428
429 #ifdef CONFIG_RPXCLASSIC
430 *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
431 *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
432 #endif
433
434 #ifdef CONFIG_RPXLITE
435 *((uchar *) BCSR0) |= BCSR0_ETHEN;
436 #endif
437
438 #ifdef CONFIG_MBX
439 board_ether_init ();
440 #endif
441
442 /*
443 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
444 */
445
446 immr->im_cpm.cp_scc[scc_index].scc_gsmrl |=
447 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
448
449 /*
450 * Work around transmit problem with first eth packet
451 */
452 #if defined (CONFIG_FADS)
453 udelay (10000); /* wait 10 ms */
454 #elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
455 udelay (100000); /* wait 100 ms */
456 #endif
457 }
458
scc_halt(int scc_index)459 static void scc_halt (int scc_index)
460 {
461 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
462
463 immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
464 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
465 immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
466 }
467
scc_send(int index,volatile void * packet,int length)468 static int scc_send (int index, volatile void *packet, int length)
469 {
470 int i, j = 0;
471
472 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
473 udelay (1); /* will also trigger Wd if needed */
474 j++;
475 }
476 if (j >= TOUT_LOOP)
477 printf ("TX not ready\n");
478 rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
479 rtx->txbd[txIdx].cbd_datlen = length;
480 rtx->txbd[txIdx].cbd_sc |=
481 (BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP);
482 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
483 udelay (1); /* will also trigger Wd if needed */
484 j++;
485 }
486 if (j >= TOUT_LOOP)
487 printf ("TX timeout\n");
488 i = (rtx->txbd[txIdx].
489 cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ;
490 return i;
491 }
492
scc_recv(int index,void * packet,int max_length)493 static int scc_recv (int index, void *packet, int max_length)
494 {
495 int length = -1;
496
497 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
498 goto Done; /* nothing received */
499 }
500
501 if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) {
502 length = rtx->rxbd[rxIdx].cbd_datlen - 4;
503 memcpy (packet,
504 (void *) (NetRxPackets[rxIdx]),
505 length < max_length ? length : max_length);
506 }
507
508 /* Give the buffer back to the SCC. */
509 rtx->rxbd[rxIdx].cbd_datlen = 0;
510
511 /* wrap around buffer index when necessary */
512 if ((rxIdx + 1) >= PKTBUFSRX) {
513 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
514 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
515 rxIdx = 0;
516 } else {
517 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
518 rxIdx++;
519 }
520
521 Done:
522 return length;
523 }
524
525 /*
526 * Test routines
527 */
528
packet_fill(char * packet,int length)529 static void packet_fill (char *packet, int length)
530 {
531 char c = (char) length;
532 int i;
533
534 packet[0] = 0xFF;
535 packet[1] = 0xFF;
536 packet[2] = 0xFF;
537 packet[3] = 0xFF;
538 packet[4] = 0xFF;
539 packet[5] = 0xFF;
540
541 for (i = 6; i < length; i++) {
542 packet[i] = c++;
543 }
544 }
545
packet_check(char * packet,int length)546 static int packet_check (char *packet, int length)
547 {
548 char c = (char) length;
549 int i;
550
551 for (i = 6; i < length; i++) {
552 if (packet[i] != c++)
553 return -1;
554 }
555
556 return 0;
557 }
558
test_ctlr(int ctlr,int index)559 static int test_ctlr (int ctlr, int index)
560 {
561 int res = -1;
562 char packet_send[MAX_PACKET_LENGTH];
563 char packet_recv[MAX_PACKET_LENGTH];
564 int length;
565 int i;
566 int l;
567
568 ctlr_proc[ctlr].init (index);
569
570 for (i = 0; i < TEST_NUM; i++) {
571 for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
572 packet_fill (packet_send, l);
573
574 ctlr_proc[ctlr].send (index, packet_send, l);
575
576 length = ctlr_proc[ctlr].recv (index, packet_recv,
577 MAX_PACKET_LENGTH);
578
579 if (length != l || packet_check (packet_recv, length) < 0) {
580 goto Done;
581 }
582 }
583 }
584
585 res = 0;
586
587 Done:
588
589 ctlr_proc[ctlr].halt (index);
590
591 /*
592 * SCC2 Ethernet parameter RAM space overlaps
593 * the SPI parameter RAM space. So we need to restore
594 * the SPI configuration after SCC2 ethernet test.
595 */
596 #if defined(CONFIG_SPI)
597 if (ctlr == CTLR_SCC && index == 1) {
598 spi_init_f ();
599 spi_init_r ();
600 }
601 #endif
602
603 if (res != 0) {
604 post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr],
605 index + 1);
606 }
607
608 return res;
609 }
610
ether_post_test(int flags)611 int ether_post_test (int flags)
612 {
613 int res = 0;
614 int i;
615
616 ctlr_proc[CTLR_SCC].init = scc_init;
617 ctlr_proc[CTLR_SCC].halt = scc_halt;
618 ctlr_proc[CTLR_SCC].send = scc_send;
619 ctlr_proc[CTLR_SCC].recv = scc_recv;
620
621 for (i = 0; i < CTRL_LIST_SIZE; i++) {
622 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
623 res = -1;
624 }
625 }
626
627 #if !defined(CONFIG_8xx_CONS_NONE)
628 serial_reinit_all ();
629 #endif
630 return res;
631 }
632
633 #endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */
634