1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2013 Xilinx, Inc.
4  * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
5  *
6  * Xilinx Zynq PS SPI controller driver (master mode only)
7  */
8 
9 #include <common.h>
10 #include <dm.h>
11 #include <malloc.h>
12 #include <spi.h>
13 #include <asm/io.h>
14 
15 DECLARE_GLOBAL_DATA_PTR;
16 
17 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
18 #define ZYNQ_SPI_CR_MSA_MASK		BIT(15)	/* Manual start enb */
19 #define ZYNQ_SPI_CR_MCS_MASK		BIT(14)	/* Manual chip select */
20 #define ZYNQ_SPI_CR_CS_MASK		GENMASK(13, 10)	/* Chip select */
21 #define ZYNQ_SPI_CR_BAUD_MASK		GENMASK(5, 3)	/* Baud rate div */
22 #define ZYNQ_SPI_CR_CPHA_MASK		BIT(2)	/* Clock phase */
23 #define ZYNQ_SPI_CR_CPOL_MASK		BIT(1)	/* Clock polarity */
24 #define ZYNQ_SPI_CR_MSTREN_MASK		BIT(0)	/* Mode select */
25 #define ZYNQ_SPI_IXR_RXNEMPTY_MASK	BIT(4)	/* RX_FIFO_not_empty */
26 #define ZYNQ_SPI_IXR_TXOW_MASK		BIT(2)	/* TX_FIFO_not_full */
27 #define ZYNQ_SPI_IXR_ALL_MASK		GENMASK(6, 0)	/* All IXR bits */
28 #define ZYNQ_SPI_ENR_SPI_EN_MASK	BIT(0)	/* SPI Enable */
29 
30 #define ZYNQ_SPI_CR_BAUD_MAX		8	/* Baud rate divisor max val */
31 #define ZYNQ_SPI_CR_BAUD_SHIFT		3	/* Baud rate divisor shift */
32 #define ZYNQ_SPI_CR_SS_SHIFT		10	/* Slave select shift */
33 
34 #define ZYNQ_SPI_FIFO_DEPTH		128
35 #ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
36 #define CONFIG_SYS_ZYNQ_SPI_WAIT	(CONFIG_SYS_HZ/100)	/* 10 ms */
37 #endif
38 
39 /* zynq spi register set */
40 struct zynq_spi_regs {
41 	u32 cr;		/* 0x00 */
42 	u32 isr;	/* 0x04 */
43 	u32 ier;	/* 0x08 */
44 	u32 idr;	/* 0x0C */
45 	u32 imr;	/* 0x10 */
46 	u32 enr;	/* 0x14 */
47 	u32 dr;		/* 0x18 */
48 	u32 txdr;	/* 0x1C */
49 	u32 rxdr;	/* 0x20 */
50 };
51 
52 
53 /* zynq spi platform data */
54 struct zynq_spi_platdata {
55 	struct zynq_spi_regs *regs;
56 	u32 frequency;		/* input frequency */
57 	u32 speed_hz;
58 	uint deactivate_delay_us;	/* Delay to wait after deactivate */
59 	uint activate_delay_us;		/* Delay to wait after activate */
60 };
61 
62 /* zynq spi priv */
63 struct zynq_spi_priv {
64 	struct zynq_spi_regs *regs;
65 	u8 cs;
66 	u8 mode;
67 	ulong last_transaction_us;	/* Time of last transaction end */
68 	u8 fifo_depth;
69 	u32 freq;		/* required frequency */
70 };
71 
zynq_spi_ofdata_to_platdata(struct udevice * bus)72 static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
73 {
74 	struct zynq_spi_platdata *plat = bus->platdata;
75 	const void *blob = gd->fdt_blob;
76 	int node = dev_of_offset(bus);
77 
78 	plat->regs = (struct zynq_spi_regs *)devfdt_get_addr(bus);
79 
80 	/* FIXME: Use 250MHz as a suitable default */
81 	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
82 					250000000);
83 	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
84 					"spi-deactivate-delay", 0);
85 	plat->activate_delay_us = fdtdec_get_int(blob, node,
86 						 "spi-activate-delay", 0);
87 	plat->speed_hz = plat->frequency / 2;
88 
89 	debug("%s: regs=%p max-frequency=%d\n", __func__,
90 	      plat->regs, plat->frequency);
91 
92 	return 0;
93 }
94 
zynq_spi_init_hw(struct zynq_spi_priv * priv)95 static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
96 {
97 	struct zynq_spi_regs *regs = priv->regs;
98 	u32 confr;
99 
100 	/* Disable SPI */
101 	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
102 	writel(~confr, &regs->enr);
103 
104 	/* Disable Interrupts */
105 	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
106 
107 	/* Clear RX FIFO */
108 	while (readl(&regs->isr) &
109 			ZYNQ_SPI_IXR_RXNEMPTY_MASK)
110 		readl(&regs->rxdr);
111 
112 	/* Clear Interrupts */
113 	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);
114 
115 	/* Manual slave select and Auto start */
116 	confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
117 		ZYNQ_SPI_CR_MSTREN_MASK;
118 	confr &= ~ZYNQ_SPI_CR_MSA_MASK;
119 	writel(confr, &regs->cr);
120 
121 	/* Enable SPI */
122 	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
123 }
124 
zynq_spi_probe(struct udevice * bus)125 static int zynq_spi_probe(struct udevice *bus)
126 {
127 	struct zynq_spi_platdata *plat = dev_get_platdata(bus);
128 	struct zynq_spi_priv *priv = dev_get_priv(bus);
129 
130 	priv->regs = plat->regs;
131 	priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
132 
133 	/* init the zynq spi hw */
134 	zynq_spi_init_hw(priv);
135 
136 	return 0;
137 }
138 
spi_cs_activate(struct udevice * dev)139 static void spi_cs_activate(struct udevice *dev)
140 {
141 	struct udevice *bus = dev->parent;
142 	struct zynq_spi_platdata *plat = bus->platdata;
143 	struct zynq_spi_priv *priv = dev_get_priv(bus);
144 	struct zynq_spi_regs *regs = priv->regs;
145 	u32 cr;
146 
147 	/* If it's too soon to do another transaction, wait */
148 	if (plat->deactivate_delay_us && priv->last_transaction_us) {
149 		ulong delay_us;		/* The delay completed so far */
150 		delay_us = timer_get_us() - priv->last_transaction_us;
151 		if (delay_us < plat->deactivate_delay_us)
152 			udelay(plat->deactivate_delay_us - delay_us);
153 	}
154 
155 	clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
156 	cr = readl(&regs->cr);
157 	/*
158 	 * CS cal logic: CS[13:10]
159 	 * xxx0	- cs0
160 	 * xx01	- cs1
161 	 * x011 - cs2
162 	 */
163 	cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
164 	writel(cr, &regs->cr);
165 
166 	if (plat->activate_delay_us)
167 		udelay(plat->activate_delay_us);
168 }
169 
spi_cs_deactivate(struct udevice * dev)170 static void spi_cs_deactivate(struct udevice *dev)
171 {
172 	struct udevice *bus = dev->parent;
173 	struct zynq_spi_platdata *plat = bus->platdata;
174 	struct zynq_spi_priv *priv = dev_get_priv(bus);
175 	struct zynq_spi_regs *regs = priv->regs;
176 
177 	setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
178 
179 	/* Remember time of this transaction so we can honour the bus delay */
180 	if (plat->deactivate_delay_us)
181 		priv->last_transaction_us = timer_get_us();
182 }
183 
zynq_spi_claim_bus(struct udevice * dev)184 static int zynq_spi_claim_bus(struct udevice *dev)
185 {
186 	struct udevice *bus = dev->parent;
187 	struct zynq_spi_priv *priv = dev_get_priv(bus);
188 	struct zynq_spi_regs *regs = priv->regs;
189 
190 	writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
191 
192 	return 0;
193 }
194 
zynq_spi_release_bus(struct udevice * dev)195 static int zynq_spi_release_bus(struct udevice *dev)
196 {
197 	struct udevice *bus = dev->parent;
198 	struct zynq_spi_priv *priv = dev_get_priv(bus);
199 	struct zynq_spi_regs *regs = priv->regs;
200 	u32 confr;
201 
202 	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
203 	writel(~confr, &regs->enr);
204 
205 	return 0;
206 }
207 
zynq_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)208 static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
209 			    const void *dout, void *din, unsigned long flags)
210 {
211 	struct udevice *bus = dev->parent;
212 	struct zynq_spi_priv *priv = dev_get_priv(bus);
213 	struct zynq_spi_regs *regs = priv->regs;
214 	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
215 	u32 len = bitlen / 8;
216 	u32 tx_len = len, rx_len = len, tx_tvl;
217 	const u8 *tx_buf = dout;
218 	u8 *rx_buf = din, buf;
219 	u32 ts, status;
220 
221 	debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
222 	      bus->seq, slave_plat->cs, bitlen, len, flags);
223 
224 	if (bitlen % 8) {
225 		debug("spi_xfer: Non byte aligned SPI transfer\n");
226 		return -1;
227 	}
228 
229 	priv->cs = slave_plat->cs;
230 	if (flags & SPI_XFER_BEGIN)
231 		spi_cs_activate(dev);
232 
233 	while (rx_len > 0) {
234 		/* Write the data into TX FIFO - tx threshold is fifo_depth */
235 		tx_tvl = 0;
236 		while ((tx_tvl < priv->fifo_depth) && tx_len) {
237 			if (tx_buf)
238 				buf = *tx_buf++;
239 			else
240 				buf = 0;
241 			writel(buf, &regs->txdr);
242 			tx_len--;
243 			tx_tvl++;
244 		}
245 
246 		/* Check TX FIFO completion */
247 		ts = get_timer(0);
248 		status = readl(&regs->isr);
249 		while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
250 			if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
251 				printf("spi_xfer: Timeout! TX FIFO not full\n");
252 				return -1;
253 			}
254 			status = readl(&regs->isr);
255 		}
256 
257 		/* Read the data from RX FIFO */
258 		status = readl(&regs->isr);
259 		while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
260 			buf = readl(&regs->rxdr);
261 			if (rx_buf)
262 				*rx_buf++ = buf;
263 			status = readl(&regs->isr);
264 			rx_len--;
265 		}
266 	}
267 
268 	if (flags & SPI_XFER_END)
269 		spi_cs_deactivate(dev);
270 
271 	return 0;
272 }
273 
zynq_spi_set_speed(struct udevice * bus,uint speed)274 static int zynq_spi_set_speed(struct udevice *bus, uint speed)
275 {
276 	struct zynq_spi_platdata *plat = bus->platdata;
277 	struct zynq_spi_priv *priv = dev_get_priv(bus);
278 	struct zynq_spi_regs *regs = priv->regs;
279 	uint32_t confr;
280 	u8 baud_rate_val = 0;
281 
282 	if (speed > plat->frequency)
283 		speed = plat->frequency;
284 
285 	/* Set the clock frequency */
286 	confr = readl(&regs->cr);
287 	if (speed == 0) {
288 		/* Set baudrate x8, if the freq is 0 */
289 		baud_rate_val = 0x2;
290 	} else if (plat->speed_hz != speed) {
291 		while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
292 				((plat->frequency /
293 				(2 << baud_rate_val)) > speed))
294 			baud_rate_val++;
295 		plat->speed_hz = speed / (2 << baud_rate_val);
296 	}
297 	confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
298 	confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
299 
300 	writel(confr, &regs->cr);
301 	priv->freq = speed;
302 
303 	debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
304 	      priv->regs, priv->freq);
305 
306 	return 0;
307 }
308 
zynq_spi_set_mode(struct udevice * bus,uint mode)309 static int zynq_spi_set_mode(struct udevice *bus, uint mode)
310 {
311 	struct zynq_spi_priv *priv = dev_get_priv(bus);
312 	struct zynq_spi_regs *regs = priv->regs;
313 	uint32_t confr;
314 
315 	/* Set the SPI Clock phase and polarities */
316 	confr = readl(&regs->cr);
317 	confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
318 
319 	if (mode & SPI_CPHA)
320 		confr |= ZYNQ_SPI_CR_CPHA_MASK;
321 	if (mode & SPI_CPOL)
322 		confr |= ZYNQ_SPI_CR_CPOL_MASK;
323 
324 	writel(confr, &regs->cr);
325 	priv->mode = mode;
326 
327 	debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
328 
329 	return 0;
330 }
331 
332 static const struct dm_spi_ops zynq_spi_ops = {
333 	.claim_bus	= zynq_spi_claim_bus,
334 	.release_bus	= zynq_spi_release_bus,
335 	.xfer		= zynq_spi_xfer,
336 	.set_speed	= zynq_spi_set_speed,
337 	.set_mode	= zynq_spi_set_mode,
338 };
339 
340 static const struct udevice_id zynq_spi_ids[] = {
341 	{ .compatible = "xlnx,zynq-spi-r1p6" },
342 	{ .compatible = "cdns,spi-r1p6" },
343 	{ }
344 };
345 
346 U_BOOT_DRIVER(zynq_spi) = {
347 	.name	= "zynq_spi",
348 	.id	= UCLASS_SPI,
349 	.of_match = zynq_spi_ids,
350 	.ops	= &zynq_spi_ops,
351 	.ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
352 	.platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
353 	.priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
354 	.probe	= zynq_spi_probe,
355 };
356