1 //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 /* Capstone Disassembly Engine */
11 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
12
13 #ifdef CAPSTONE_HAS_SYSZ
14
15 #include <capstone/platform.h>
16 #include "SystemZMCTargetDesc.h"
17
18 #define GET_REGINFO_ENUM
19 #include "SystemZGenRegisterInfo.inc"
20
21 const unsigned SystemZMC_GR32Regs[16] = {
22 SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L,
23 SystemZ_R4L, SystemZ_R5L, SystemZ_R6L, SystemZ_R7L,
24 SystemZ_R8L, SystemZ_R9L, SystemZ_R10L, SystemZ_R11L,
25 SystemZ_R12L, SystemZ_R13L, SystemZ_R14L, SystemZ_R15L
26 };
27
28 const unsigned SystemZMC_GRH32Regs[16] = {
29 SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H,
30 SystemZ_R4H, SystemZ_R5H, SystemZ_R6H, SystemZ_R7H,
31 SystemZ_R8H, SystemZ_R9H, SystemZ_R10H, SystemZ_R11H,
32 SystemZ_R12H, SystemZ_R13H, SystemZ_R14H, SystemZ_R15H
33 };
34
35 const unsigned SystemZMC_GR64Regs[16] = {
36 SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D,
37 SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D,
38 SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D,
39 SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D
40 };
41
42 const unsigned SystemZMC_GR128Regs[16] = {
43 SystemZ_R0Q, 0, SystemZ_R2Q, 0,
44 SystemZ_R4Q, 0, SystemZ_R6Q, 0,
45 SystemZ_R8Q, 0, SystemZ_R10Q, 0,
46 SystemZ_R12Q, 0, SystemZ_R14Q, 0
47 };
48
49 const unsigned SystemZMC_FP32Regs[16] = {
50 SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S,
51 SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S,
52 SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S,
53 SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S
54 };
55
56 const unsigned SystemZMC_FP64Regs[16] = {
57 SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D,
58 SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D,
59 SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D,
60 SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D
61 };
62
63 const unsigned SystemZMC_FP128Regs[16] = {
64 SystemZ_F0Q, SystemZ_F1Q, 0, 0,
65 SystemZ_F4Q, SystemZ_F5Q, 0, 0,
66 SystemZ_F8Q, SystemZ_F9Q, 0, 0,
67 SystemZ_F12Q, SystemZ_F13Q, 0, 0
68 };
69
70 const unsigned SystemZMC_VR32Regs[32] = {
71 SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S,
72 SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S,
73 SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S,
74 SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S,
75 SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S,
76 SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S,
77 SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S,
78 SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S
79 };
80
81 const unsigned SystemZMC_VR64Regs[32] = {
82 SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D,
83 SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D,
84 SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D,
85 SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D,
86 SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D,
87 SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D,
88 SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D,
89 SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D
90 };
91
92 const unsigned SystemZMC_VR128Regs[32] = {
93 SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3,
94 SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7,
95 SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11,
96 SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
97 SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19,
98 SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23,
99 SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27,
100 SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31
101 };
102
103 const unsigned SystemZMC_AR32Regs[16] = {
104 SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3,
105 SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7,
106 SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11,
107 SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15
108 };
109
110 const unsigned SystemZMC_CR64Regs[16] = {
111 SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3,
112 SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7,
113 SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11,
114 SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15
115 };
116
117 /* All register classes that have 0-15. */
118 #define DEF_REG16(N) \
119 [SystemZ_R ## N ## L] = N, \
120 [SystemZ_R ## N ## H] = N, \
121 [SystemZ_R ## N ## D] = N, \
122 [SystemZ_F ## N ## S] = N, \
123 [SystemZ_F ## N ## D] = N, \
124 [SystemZ_V ## N] = N, \
125 [SystemZ_A ## N] = N, \
126 [SystemZ_C ## N] = N
127
128 /* All register classes that (also) have 16-31. */
129 #define DEF_REG32(N) \
130 [SystemZ_F ## N ## S] = N, \
131 [SystemZ_F ## N ## D] = N, \
132 [SystemZ_V ## N] = N
133
134 static const uint8_t Map[SystemZ_NUM_TARGET_REGS] = {
135 DEF_REG16(0),
136 DEF_REG16(1),
137 DEF_REG16(2),
138 DEF_REG16(3),
139 DEF_REG16(4),
140 DEF_REG16(5),
141 DEF_REG16(6),
142 DEF_REG16(8),
143 DEF_REG16(9),
144 DEF_REG16(10),
145 DEF_REG16(11),
146 DEF_REG16(12),
147 DEF_REG16(13),
148 DEF_REG16(14),
149 DEF_REG16(15),
150
151 DEF_REG32(16),
152 DEF_REG32(17),
153 DEF_REG32(18),
154 DEF_REG32(19),
155 DEF_REG32(20),
156 DEF_REG32(21),
157 DEF_REG32(22),
158 DEF_REG32(23),
159 DEF_REG32(24),
160 DEF_REG32(25),
161 DEF_REG32(26),
162 DEF_REG32(27),
163 DEF_REG32(28),
164 DEF_REG32(29),
165 DEF_REG32(30),
166 DEF_REG32(31),
167
168 /* The float Q registers are non-sequential. */
169 [SystemZ_F0Q] = 0,
170 [SystemZ_F1Q] = 1,
171 [SystemZ_F4Q] = 4,
172 [SystemZ_F5Q] = 5,
173 [SystemZ_F8Q] = 8,
174 [SystemZ_F9Q] = 9,
175 [SystemZ_F12Q] = 12,
176 [SystemZ_F13Q] = 13,
177
178 /* The integer Q registers are all even. */
179 [SystemZ_R0Q] = 0,
180 [SystemZ_R2Q] = 2,
181 [SystemZ_R4Q] = 4,
182 [SystemZ_R6Q] = 6,
183 [SystemZ_R8Q] = 8,
184 [SystemZ_R10Q] = 10,
185 [SystemZ_R12Q] = 12,
186 [SystemZ_R14Q] = 14,
187 };
188
SystemZMC_getFirstReg(unsigned Reg)189 unsigned SystemZMC_getFirstReg(unsigned Reg)
190 {
191 // assert(Reg < SystemZ_NUM_TARGET_REGS);
192 return Map[Reg];
193 }
194
195 #endif
196